JPH0689270A - Parallel processing system - Google Patents

Abstract

PURPOSE:To provide a parallel processing system where a work rate can be increased so as to improve processing speed by reducing stand-by time for the data communication of the respective processors of the parallel processing system. CONSTITUTION:When data cannot be transmitted depending on the state of an inter-processor connection network or the transmission destination processor, the respective processors preserve transmission data in an output buffer memory 22 and execute a succeeding processing. When succeeding data is transmitted form another processor while the processor 25 is executing the processing, reception data is preserved in an input buffer memory 24 so that stand-by time is reduced, which is likely to be generated by the state of the inter-processor connection network when the processor 25 receives succeeding data. Thus, the work rate of the respective processors is increased and the processing speed of the parallel processing system is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing system composed of a plurality of processors.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing the configuration of each processor of a conventional parallel processing system of this type. In FIG.
Reference numerals 51, 52 and 53 are processors that perform divided processing, 54 is an inter-processor coupling network for transmitting and receiving data between the processors 51, 52 and 53, and 55, 56 and 57 are each processor 51, 52, 53
And input / output signal lines for transmitting signals between the inter-processor coupling network 54.

In the conventional parallel processing system configured as described above, each processor is connected to the inter-processor coupling network 54 and the input / output signal lines 55, 5 from any other processor configuring the parallel processing system.
Data is received via 6, 57, and the processed data is
By transmitting to any of the other processors configuring the parallel processing system via the interprocessor coupling network 54 and the input / output signal lines 55, 56, 57,
Proceed with processing.

[0004]

In the above parallel processing system, when each processor attempts to send data to any of the other processors constituting the parallel processing system, the processor of the transmission destination can receive the data. If it is not in such a state, or if the communication volume exceeds the communication capacity of the inter-processor coupling network, data cannot be transmitted and the processor cannot perform the next processing.
Further, when it is necessary to receive data from any of the other processors configuring the parallel processing system to perform the next processing, and when the communication volume exceeds the communication capacity of the interprocessor coupling network, Cannot receive data and cannot process it.

As described above, in the conventional parallel processing system,
When each processor tried to send or receive data, a waiting time was generated and the operating rate was lowered, and the processing speed could not be sufficiently improved.

The present invention eliminates such drawbacks and shortens the waiting time for data communication of each processor of a parallel processing system, thereby increasing the operating rate and thus the processing speed. The purpose is to provide a processing system.

[0007]

According to the present invention, in a parallel processing system for parallel processing of processes assigned to a plurality of processors, an input buffer memory for temporarily storing received data in each processor and the above It is characterized by comprising means for controlling the input buffer memory, output buffer memory for temporarily storing transmission data, and means for controlling the output buffer memory.

[0008]

According to the present invention, since each processor is provided with the output buffer memory, when the data is transmitted to any of the other processors constituting the parallel processing system, the destination processor is If it is not in a receivable state or the communication volume of the inter-processor coupling network exceeds the communication capacity, the following processing can be performed by temporarily storing the data in the output buffer memory. Since each processor has an input buffer memory, if the previous data is being processed when the data to be processed next is sent, the data to be processed next is temporarily stored in the input buffer memory. By saving, the waiting time that may occur due to the state of the inter-processor coupling network when the processing device receives the next data can be reduced, and the next data can be processed immediately. Therefore, the operating rate of each processor can be increased, and the processing speed of the entire system can be improved.

[0009]

EXAMPLES An example of the present invention will be described below.

FIG. 1 is a block diagram of a processor constituting a parallel processing system according to an embodiment of the present invention. FIG. 2 is an overall configuration diagram of a parallel processing system configured by connecting a plurality of processors shown in FIG. 3 is a flowchart showing the operation of the output control device in FIG. 1, and FIG. 4 is a flowchart showing the operation of the input control device in FIG.

In FIG. 1, reference numeral 21 is an output control device for transmitting data to any other processor constituting the parallel processing system, 22 is an output buffer memory for temporarily storing transmission data, and 23 is parallel processing. An input control device that receives data from any of the other processors that make up the system, and 24 is an input buffer memory that temporarily stores the data received from any of the other processors that make up the parallel processing system. , 25 is a processing device for performing divided processing, 26 is an input signal line for transmitting a signal between the input control device 23 and the inter-processor coupling network 2 of FIG. 2, 27 is between the output control device 21 and the processor of FIG. An output signal line for transmitting a signal to and from the coupling network 2.

In FIG. 2, 11, 12, 13, 14,
Reference numeral 15 is a processor having the configuration shown in FIG. 1, 2 is an inter-processor coupling network for transmitting and receiving data among the processors 11, 12, 13, 14, 15.
6a, 26b, 26c, 26d and 26e are the input signal lines 27a, 27b, 27c, 27d and 27 shown in FIG.
e is the output signal line 27 shown in FIG.

Next, the operation of this embodiment configured as described above will be described. First, the operation of the output control device 21 will be described with reference to the flowchart of FIG.

The output control device 21 receives the data transmission request from the processing device 25 to the processor (i) 13 (3
a), the state of the inter-processor coupling network 2 and the state of the transmission destination processor (i) 13 are examined, and the inter-processor coupling network 2 can communicate and the transmission destination processor (i) 13 can receive. If (3
b), data is transmitted to the destination processor (i) 13 (3c). If the inter-processor coupling network 2 is not communicable or the destination processor (i) 13 is not in the receivable state (3b), if the output buffer memory 22 has a free area (3d), the transmission data is transmitted. It is stored in the output buffer memory 22 (3e), and if there is no free space (3d), the processing device 25 indicates that data cannot be sent.
Tell (3f).

Next, it is checked whether or not the data is stored in the output buffer memory 22, and if the data to be transmitted to the processor (j) 14 is stored (3g), the state of the interprocessor coupling network 2 and the transmission The state of the preceding processor (j) 14 is checked, and if the inter-processor coupling network 2 is communicable and the destination processor is in the receivable state (3h), the data in the output buffer memory is transmitted to the destination. (3i).

Next, the operation of the input control device 23 will be described with reference to the flowchart of FIG. The input control device 23 is
When a data input request is received from another processor (i) 13 (4a), if the processing device 25 is not processing previous data or the input buffer memory 24 has a free area (4b), the data can be received. Processor (i) 13
(4c), the processing device 25 is not processing the previous data (4d), the data is received and transmitted to the processing device 25 (4e), and the processing device 25 is processing the previous data. If there is (4d), the data is received and stored in the input buffer memory 24 (4f). When the processing device 25 is processing the previous data and the input buffer memory 24 has no free space (4b), the processor (i) 13 is notified that the data cannot be received (4g). If there is data in the input buffer memory 24 (4h), the processing device 2
If 5 is not processing the previous data (4i), the data in the input buffer memory 24 is transmitted to the processing device 25.

As described above, each processor 11, 12,
13, 14 and 15 are interprocessor coupling networks 2
And input signal lines 26a, 26b, 26c, 26d, 26
e and output signal lines 27a, 27b, 27c, 27d, 2
7e to receive data from any of the other processors forming the parallel processing system and process the processed data to the inter-processor coupling network 2 and the input signal lines 26a, 26b, 26c, 26d and 26e. And the output signal line 27a, 27b, 27c, 27d, 27e to any of the other processors constituting the parallel processing system, thereby advancing the processing.

As described above, according to the present system, by reducing the waiting time for data communication between the processors forming the parallel processing system, the operating rate of each processor is increased and the processing speed of the entire system is improved. be able to.

[0019]

As described above, according to the present invention, the waiting time for data communication of each processor of the parallel processing system is shortened to increase the operating rate and thus the processing speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor configuring a parallel processing system according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a parallel processing system of the same embodiment.

FIG. 3 is a flowchart showing the operation of the output control device in the embodiment.

FIG. 4 is a flowchart showing the operation of the input control device in the embodiment.

FIG. 5 is a block diagram of a conventional parallel processing system.

[Explanation of symbols]

2 Inter-processor coupling network 11, 12, 13, 14, 15 Processor 21 Output control device 22 Output buffer memory 23 Input control device 24 Input buffer memory 25 Processing device 26, 26a, 26b, 26c, 26d, 26e Input signal line 27, 27a, 27b, 27c, 27d, 27e Output signal line

Claims (1)

[Claims] 1. A parallel processing system configured by connecting a plurality of processors in parallel and processing the processing assigned to each processor in parallel, wherein any one of the parallel processing system is configured in each processor. An input buffer memory for temporarily storing the data received from the processor, an output buffer memory for temporarily storing the data to be transmitted to any of the other processors constituting the parallel processing system; A parallel processing system comprising: a control means for controlling one buffer memory.