JPH0635865A - Parallel processing system - Google Patents

Abstract

PURPOSE:To provide a parallel processing system capable of accelerating processing speed by reducing waiting time for the data communication of the respective processors of the parallel processing system and thereby increasing a working rate. CONSTITUTION:When data can not be transmitted clue to the state of the processor as a transmission destination or an interprocessor connection network, the respective processors preserve transmission data at the leading address side of a buffer memory 21 and perform the next processing. Also, when the next data are transmitted from the other processor while the processor 24 is processing, reception data are preserved at the ending address side of the buffer memory 21 so that the waiting time possibly generated due to the state of the interprocessor connection network when the processor 24 receives the next data is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing system composed of a plurality of processors.

[0002]

2. Description of the Related Art A conventional parallel processing system will be described below with reference to the drawings. FIG. 7 is a block diagram showing the configuration of each processor of a conventional parallel processing system of this type. In the figure, 71, 72 and 73 are processors that perform divided processing, and 74 is each processor 71, 72 and 7
3 is an inter-processor coupling network for transmitting and receiving data between the three, and 75, 76 and 77 are input / output signal lines for transmitting signals between the processors 71, 72 and 73 and the inter-processor coupling network 74.

In the conventional parallel processing system having the above-mentioned components, the mutual relation and operation of the components will be described. Each processor 71, 72 or 73 is one of the other components constituting this parallel processing system. Data from one processor to another processor constituting this parallel processing system by receiving data via the interprocessor coupling network 74 and the input / output signal line 75, 76 or 77. The process proceeds by transmitting via the coupling network 74 and the input / output signal line 75, 76 or 77.

[0004]

In the above-mentioned conventional parallel processing system, when each processor attempts to send data to any of the other processors constituting this parallel processing system, the destination processor If it is not in the receivable state or the communication traffic exceeds the communication capacity of the inter-processor coupling network, the data cannot be transmitted and the processor cannot perform the next processing. Further, when it is necessary to receive data from any of the other processors that configure the parallel processing system to perform the next processing, when the communication amount exceeds the communication capacity of the interprocessor coupling network, Unable to receive data and process.

As described above, in the conventional parallel processing system,
There has been a problem that a waiting time occurs when each processor attempts to transmit or receive data, the operating rate is reduced, and the processing speed cannot be sufficiently improved. The present invention solves the above-mentioned conventional problems and reduces the waiting time for data communication of each processor of a parallel processing system, thereby increasing the operating rate and thus improving the processing speed. The purpose is to provide a processing system.

[0006]

In order to achieve the above-mentioned object, a parallel processing system of the present invention is a parallel processing system for processing in parallel the processing assigned to a plurality of processors, wherein A buffer memory for temporarily storing data received from any other processor configuring the parallel processing system and data to be transmitted to any other processor configuring the parallel processing system; The buffer memory has an input / output control means for controlling the area size for input data and the area size for output data to be variable.

[0007]

According to the present invention, in the above structure, each processor is provided with the buffer memory. Therefore, when transmitting data to any of the other processors constituting this parallel processing system, the destination processor is If the data is not in the receivable state or the communication volume of the inter-processor coupling network exceeds the communication capacity, the following processing can be performed by temporarily storing the data in the buffer memory. Further, when each processor is processing the previous data when the data to be processed next is sent, each processor temporarily stores the data to be processed next in the buffer memory, The latency that can occur due to the state of the interprocessor coupling network when the device receives the next data can be reduced and acts to process the next data immediately. Further, the buffer memory is divided into an area for input data and an area for output data, and the size of each area is made variable, so that it can effectively operate with a small memory capacity.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A parallel processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a processor constituting a parallel processing system according to an embodiment of the present invention,
FIG. 2 is an overall configuration diagram of a parallel processing system configured by connecting a plurality of processors shown in FIG.

In FIG. 1, reference numeral 21 denotes data to be transmitted to any other processor constituting this parallel processing system (hereinafter referred to as transmission data), and any other processor constituting this parallel processing system. A buffer memory for temporarily storing the data received from the server (hereinafter referred to as received data), and 22 is an input / output control device for controlling the buffer memory 21 so that the area size for input data and the area size for output data are variable. , 23 are input / output control devices 22
2 is a pointer storage unit for storing pointers A and B required for controlling the buffer memory, 24 is a processing device for performing divided processing, 25 is an input / output control device, and FIG.
Is an input / output signal line for transmitting a signal to and from the inter-processor coupling network 2.

In FIG. 2, reference numerals 11, 12, 13, 14 and 15 each denote a processor configured as shown in FIG. 1, and 2 denotes each processor 11, 12, 13, 14.
An inter-processor coupling network for transmitting and receiving data between the terminals 15 and 25, 25a, 25b, 25c,
25d and 25e are the input signal lines 25 shown in FIG.

Next, regarding the parallel processing system of one embodiment of the present invention, which comprises the above-mentioned components, the relation and operation of the components will be described. First, how to store the input data and the output data in the buffer memory 21 will be described with reference to the explanatory diagram showing how to use the buffer memory in FIG. FIG. 3 shows a state in which two pieces of input data and two pieces of output data are stored, 31 is an empty area, 32 is an input data area, 33 is an output data area, 3
4 is a pointer A indicating the start address of the free space 31, 3
5 is a pointer B indicating the end address of the free space 31, 3
6 is the start address of the buffer memory, and 37 is the end address of the buffer memory.

When the input data is saved, it is stored at the head address side in the empty area 31 of the buffer memory, and when the output data is saved, the empty area 3 of the buffer memory 3 is stored.
It is stored in the end address side within 1. Therefore, each time new input data is saved, the pointer A34 is moved to the end address 37 side of the buffer memory by the amount of that data, and each time new output data is saved, it is moved to the start address 36 side of the buffer memory by the amount of that data. Move the pointer B.

After the data stored in the buffer memory 21 is sent to the destination processor or processing unit 24, the data becomes unnecessary. Therefore, when the input data is sent to the processing unit 24, the remaining input data is buffered. When the pointer A34 is refilled to the head address 36 side of the memory, the pointer A34 is moved by the amount of the data sent to the head address 36 side of the buffer memory, and the output data is sent to another processor,
The remaining output data is transferred to the tail address 37 of the buffer memory.
The pointer B35 is moved to the end address 37 side of the buffer memory by the amount of data sent. When the input data or the output data is newly temporarily saved, the size of the saved data is limited so as not to exceed the size of the free area. In the following description, it is assumed that the data is stored in the buffer memory and is sent out as described above.

As shown in the flow chart of FIG. 4 showing the operation of the input / output control device in FIG. 1, the input / output control device 24 has output control A (4a) and output control B (4).
b), the input control A (4c), and the input control B (4d) are sequentially repeated. First, the output control A (4a) will be described with reference to the flowchart of FIG.
The process (4a) will be described.

The input / output control device 22 receives the data transmission request from the processing device 24 to the processor (i) 13 (5a), and determines the state of the interprocessor coupling network 2,
The state of the destination processor (i) 13 is checked, and if the interprocessor coupling network 2 is communicable and the destination processor (i) 13 is in the receivable state (5b), the destination processor (I) Data is transmitted to 13 (5c). If the inter-processor coupling network 2 is not communicable or the destination processor (i) 13 is not in a receivable state (5b), if there is an empty area in the buffer memory 21 (5d), the transmission data is From the address of pointer B to the buffer memory 21
(5e), the pointer B is moved (5g), and when there is no free space (5d), the processor 24 is notified that data cannot be sent (5f). The above is the output control A (4
This is the process a).

Next, the output control B (4) will be described with reference to the flowchart of FIG. 5 (b) showing the processing of the output control B (4b).
The processing of b) will be described. The input / output control device 22 checks whether the output data is stored in the buffer memory 21,
When the data to be transmitted to the processor (j) 14 is stored (5h), the state of the inter-processor coupling network 2 and the state of the destination processor (j) 14 are checked, and the inter-processor coupling network 2 can communicate. If there is, and the destination processor is ready to receive ((5
i), the data in the output buffer memory is transmitted to the destination processor (j) 14 (5j), the remaining output data in the buffer memory is repacked toward the end of the address, and the pointer B is moved (5k). . The above is the output control B (4
This is the process of b).

Next, the input control A (4) will be described with reference to the flowchart of FIG. 6 (a) showing the processing of the input control A (4c).
The processing of c) will be described. When the input / output control device 22 receives a data input request from another processor (i) 13 (6a), the processing device 24 is not processing the previous data or the buffer memory 21 has a free area. (6b), the processor (i) 13 that it is receivable
(6c), the processing device 24 is not processing the previous data (6d), the data is received and transmitted to the processing device 24 (6e), and the processing device 24 is processing the previous data. If so (6d), the data is received, stored in the buffer memory 21 from the address of the pointer A (6f), and the pointer A is moved (6g). When the processing device 24 is processing the previous data and the buffer memory 21 has no free area (6b), the processor (i) 13 is notified that the data cannot be received (6h). The above is input control A
It is the process of (4c).

Next, FIG. 6 showing the processing of the input control B
Input control B (4d) using the flowchart of (b)
The processing of will be described. When the input data is stored in the buffer memory 21 (6i), if the processing device 24 is not processing the previous data (6j), the input data in the buffer memory 21 is transmitted to the processing device 24 (6k), The remaining input data in the buffer memory is refilled in the direction of the head of the address, and the pointer A is moved (6 m). The above is the processing of the input control B (4d).

As described above, each processor 11, 12,
Reference numerals 13, 14 and 15 receive data from other processors via the interprocessor coupling network 2 and the input / output signal lines 25a, 25b, 25c, 25d and 25e, and process the processed data to the interprocessor coupling network 2 And the input signal lines 25a, 25b, 25c, 25d, and 25e to the other processors to proceed the processing.

In the above, the input / output control device 22 determines whether the input / output can be transmitted / received, and the pointer storage unit 23
The function of determining the storage location of is collectively referred to as input / output control means.

As described above, according to the present system, the buffer memory is effectively used and the waiting time for the data communication between the processors forming the parallel processing system is reduced, thereby increasing the operating rate of each processor and The overall processing speed can be improved.

The same effect can be obtained by storing the output data on the head address side and the input data on the tail address side of the buffer memory. The operation of the input / output control device is the same regardless of the order of the four processes of output control A (4a), output control B (4b), input control A (4c), and input control B (4d). The effect of is obtained.

[0023]

As described above, according to the parallel processing system of the present invention, by having the buffer memory and the input / output control means, the buffer memory is effectively utilized and each processor constituting the parallel processing system. The waiting time for data communication can be reduced, the operating rate of each processor is increased, and the processing speed of the entire system is improved.
Further, by dividing the buffer memory into an area for input data and an area for output data, and making the size of each area variable, the size of the buffer memory area for input data and the buffer memory area for output data The buffer memory can be effectively utilized as compared with the case where the size of and is fixed.

[Brief description of drawings]

FIG. 1 is a block diagram of a processor constituting a parallel processing system according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a parallel processing system of the same embodiment.

FIG. 3 is an explanatory diagram showing how to use a buffer memory of the parallel processing system of the embodiment.

FIG. 4 is a flowchart showing the operation of the input / output control device in the embodiment.

FIG. 5A is a flowchart showing a process of output control A of the input / output control device in the same embodiment. FIG. 5B is a flowchart showing a process of output control B of the input / output control device in the same embodiment.

FIG. 6A is a flowchart showing a process of input control A of the input / output control device in the same embodiment. FIG. 6B is a flowchart showing a process of input control B of the input / output control device in the same embodiment.

FIG. 7 is a block diagram of a conventional parallel processing system.

[Explanation of symbols]

2 Inter-processor coupling network 11 to 15 Processor 21 Buffer memory 22 Input / output control device 23 Pointer storage unit 24 Processing device 25, 25a, 25b, 25c, 25d, 25e Input / output signal line

Claims (1)

[Claims] 1. A configuration in which a plurality of processors are combined,
In a parallel processing system that processes the processes assigned to each processor in parallel, in each of the processors, the data received from any of the other processors configuring the parallel processing system and the parallel processing system are configured. Buffer memory for temporarily storing data to be transmitted to any other processor, and an input for controlling the buffer memory so that the area size for input data and the area size for output data are variable. A parallel processing system comprising an output control means.