JPH0686257A - Picture encoder - Google Patents

Abstract

PURPOSE:To realize the picture encoder data-compressing a video signal and high in picture quality, and to realize the encoder capable of a processing by switching a present TV signal to a high-definition TV signal. CONSTITUTION:The change of the content of a picture in plural frames is detected by block units by a block mode discriminating part 3, processed by a movement adaptive blocking processing part 2 which reduces the number of still blocks to be encoded, and data-compressed by a picture encoding circuit 4, so that the picture encoder of the high picture quality can be realized. And also, the high-definition TV signals processed by the movement adaptive blocking processing part 2 are distributed to plural channels, and a switching circuit which selects either one channel or the present TV signal is provided in the pre-stage of the picture encoding circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus used in a digital VTR or the like for digitally recording a video signal on a magnetic tape, and is particularly suitable for compressing a high definition video signal while maintaining high image quality. Further, the present invention relates to an image encoding device having a high data compression rate.

[0002]

2. Description of the Related Art As an image coding apparatus for compressing a video signal to reduce the amount of information, for example, IEE Transactions on Consumer.
Electronics Vol. 35, No. 3, August 1989, pp. 450-457 (IEEE Transactions on
Consumer Electronics, Vol. 35, No. 3 (August 198
9), pp. 450-457), an image coding apparatus used in the digital VTR is known.

This digital VTR is based on the current TV signal,
That is, a video signal having a total of 525 vertical lines in a frame and a frame frequency of 29.97 frames / second is data-compressed and recorded on a magnetic tape, and the recorded data is reproduced to expand the data to produce a video signal. It is what is output. The number of effective pixels in a frame recorded on the magnetic tape is 720 × 480 pixels, and the number of pixels to be processed per second (hereinafter referred to as a pixel rate) is about 10 M pixels / second.

The operation of the image coding apparatus used in this digital VTR is as follows. When encoding a video signal, an input video signal is converted from an analog signal to digital image data by A / D conversion, the image data is divided into two-dimensional blocks of a predetermined size for each frame, and a discrete cosine transform (DCT) is performed. ), Quantization, and image coding processing including variable-length coding. Further, when decoding a video signal, data is expanded by image decoding processing including variable length decoding, inverse quantization, and inverse discrete cosine transform (IDCT) to generate image data, and then the digital image data is converted. It is converted into an analog video signal by D / A conversion and output.

As described above, the image coding apparatus performs intra-frame coding using DCT for each frame independently of the video signal, that is, without referring to information of other frames.

[0006]

However, the above-mentioned image coding apparatus according to the prior art is for data compression of the current TV signal, and is compatible with a high-definition high-definition TV signal (hereinafter referred to as HDTV signal). Was not considered.

The HDTV signal has, for example, 1125 total vertical lines in a frame and a frame frequency of 30 frames / sec. The frame frequency is almost the same as the current TV signal, but the total number of vertical lines in the frame is more than double. In a typical example, the number of effective pixels in a frame is 1152 × 1040 pixels, and the pixel rate is about 35 M pixels / sec, which is about four times that of the current TV signal.

In the case of a digital VTR, HD
There is a demand to suppress the recording data rate of TV signals to about twice the recording data rate of current TV signals. In that case, it is necessary to increase the data compression rate of the image coding apparatus to about twice. However, in the image coding apparatus according to the above-mentioned conventional technique, if the data compression rate is increased in this way, coding distortion increases, and it cannot be put to practical use.

An object of the present invention is to solve the above-mentioned problems and to realize an image coding apparatus suitable for data compression of HDTV signals, which can realize a higher data compression rate while maintaining high image quality. Another object of the present invention is H
An object is to realize a high-quality image encoding device that supports data compression of both DTV signals and current TV signals.

[0010]

In order to achieve the above object, the present invention determines whether an HDTV signal, which is an input video signal, has a predetermined size whether or not there is a change (movement) in image content over a predetermined plurality of frames. For a still block that is detected in units of two-dimensional blocks and has no change in the image content, a motion adaptive block forming unit that reduces the number of blocks so that the block is encoded only once in a plurality of frames is used as image data. It is provided in front of the image encoding means for performing the data compression of.

In order to achieve the above-mentioned other object, the present invention provides a motion adaptive block forming means for performing the processing as described above on an input HDTV signal, and the output data thereof is distributed in block units to a plurality of channels. Block distributing means, a plurality of image encoding means for compressing the distributed data are provided, and in the HDTV signal processing mode, the above-mentioned motion adaptive block formation is performed before a specific one image encoding means. In the current TV signal processing mode, the HDTV signal preprocessed by the means and the block distributing means is provided with signal switching means for selecting the input current TV signal itself.

[0012]

The motion adaptive block forming means reduces the number of blocks so that a still block in which the image content does not change is encoded only once in a predetermined plurality of frames. A block located in a static background part where the image content does not change is processed as a static block.
The number of blocks to be data-compressed by the image coding means for a predetermined plurality of frames is reduced as compared with the conventional case. Therefore, the average compressed data amount assigned to each block becomes large, so that it is possible to realize an image encoding device that can achieve a higher data compression rate than in the past.

It is also possible to distribute the signal processed by the motion adaptive blocking means as described above to a plurality of channels by the block distributing means and individually compress each signal by the image coding means. At this time, the image coding means of one specific channel is made to correspond to the current TV signal, and the pixel rate of the HDTV signal distributed to that channel is almost the same as that of the current TV signal, or the image coding means of that channel. By setting the pixel rate that can be processed by, the HDTV signal or the current TV signal can be selected by the signal switching means as the input of the image encoding means of the channel. This allows
It is possible to realize a high-quality image encoding device capable of performing image encoding processing on both HDTV signals and current TV signals.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an encoding processing circuit of an image encoding apparatus which is a first embodiment of the present invention. Further, FIG. 2 is a block diagram of a decoding processing circuit of the image coding apparatus according to the first embodiment of the present invention. The encode processing circuit performs data compression of the video signal, and the decode processing circuit performs reverse data expansion.

In the encoding processing circuit of the image encoding apparatus shown in FIG. 1, 1 is an input terminal for image data of an HDTV signal, 2 is a motion adaptive blocking circuit, 3 is a block mode determination circuit, 4 is an image encoding circuit, Reference numeral 5 is an output terminal for compressed data. In the image coding circuit 4, 6 is a DCT circuit, 7 is a block memory, 8 is a quantization circuit, and 9 is a quantization circuit.
Is a variable length coding circuit, 10 is a buffer memory, and 11 is a quantization parameter generation circuit. In the decoding processing circuit of the image encoding device shown in FIG. 2, 12 is an input terminal for compressed data, 13 is an image decoding circuit, 14 is a motion adaptive block interpolation circuit, and 15 is an output terminal for image data of an HDTV signal. In the image decoding circuit 13, 16
Is a buffer memory, 17 is a variable length decoding circuit, 18 is an inverse quantization circuit, and 19 is an IDCT circuit.

The encoding processing circuit of the image encoding apparatus shown in FIG. 1 operates as follows. HDTV signal is 44.55
It is sampled at a sampling frequency of MHz, converted from an analog video signal to digital image data by an A / D conversion process, and then input from an input terminal 1 to an encoding processing circuit of an image encoding device. The number of effective pixels in one frame is 1152 × 1040 pixels. The block mode determination circuit 3 holds the image data of the HDTV signal input from the input terminal 1 for two frames, and stores the two consecutive image data.
The change (motion) of the image content between frames is detected in block units of 16 × 16 pixels, and the block mode of each block is determined. There are three types of block modes: a field mode, a frame mode, and a still mode. Blocks with large motion are in field mode, blocks with small motion are in frame mode, and blocks with little motion are in still mode. The block mode determination circuit 3 calculates the difference value of the image data between two frames for each pixel, and counts the number of pixels whose absolute value exceeds the threshold value within the block. When the number of pixels counted in the block exceeds the first threshold number, the field mode is output, when the number of pixels is less than the second threshold number, the still mode is output, and in the middle, the frame mode is output as the block mode. To do. The first threshold number is 32 and the second threshold number is 2.

The motion adaptive blocking circuit 2 has an input terminal 1
After holding the image data of the HDTV signal input from 2 frames for 2 frames, the processing method of rearranging the image data for each block and switching into blocks is switched according to the block mode determined by the block mode determination circuit 3.
FIG. 3 is a conceptual diagram of the operation of the motion adaptive blocking circuit 2. As shown in FIG. 3, the number of effective pixels in the frame is 115.
Two frames of an HDTV signal, which is 2 × 1040 pixels,
It is divided into blocks of 16 × 16 pixels. One frame is divided into 72 × 65 blocks. Two blocks at the same position on the screen form a pair, and a plurality of coded blocks of 8 × 8 pixels are generated from the pair of blocks. The coding block generation method from the block pair differs depending on the block mode. In the field mode, eight coded blocks are generated in units of fields, and in the frame mode, eight coded blocks are generated in units of frames. Further, in the still mode, four encoded blocks are generated with the screen in which two frames are mixed as a unit.

Details of the motion adaptive block formation processing in each block mode are shown in FIGS. 4, 5, and 6. Figure 4
Shows the processing in the field mode, FIG. 5 shows the processing in the frame mode, and FIG. 6 shows the processing in the still mode. H input
In the image data of the DTV signal, pixels are arranged in a grid pattern as shown on the left side of FIGS.
The frame is composed. However, two fields each having half the number of vertical lines with respect to the frame are overlapped with an offset in the vertical direction to form one frame. The solid lines indicate the lines forming the odd field, and the pixels in the odd field are indicated by circles. Also, the broken lines indicate the lines forming the even field, and the pixels in the even field are indicated by the triangle marks. Adjacent even fields and odd fields are images at times shifted by 1/60 seconds.

In the field mode, the motion adaptive blocking circuit 2 divides one frame into two screens, an odd field and an even field, that is, two frames are divided into four.
After the screen is divided into a number of screens, as shown in the right side of FIG. 4, each field is divided into coding blocks of a predetermined size and image data is output. The size of the coding block is illustrated as 4 × 4 pixels in FIG. 4, but is actually 8 × 8 pixels. Further, in the frame mode, the motion adaptive blocking circuit 2 sets a frame composed of an odd field and an even field as one screen and two frames as two screens, and then, as shown in the right side of FIG. Then, each frame is divided into coding blocks of a predetermined size, and image data is output. Although the size of the coding block is illustrated as 4 × 4 pixels in FIG. 5, it is actually 8 × 8 pixels. If the movement is large, the time difference between fields may cause
Since the image contents of the odd field and the even field change, it is not efficient to perform the image coding processing by performing the block formation on a frame basis. Therefore, the block formation is performed on a field basis. On the other hand, when the motion is small, the change in the image content between the odd field and the even field is small, so that the image code is blocked by the frame in which the pixel density in the vertical direction is high and the correlation between the pixels is high. It is more efficient to perform the chemical conversion process.

In the still mode, since the image contents hardly change over two frames, the images in the odd frame and the even frame have almost the same contents. Therefore, as shown in the right side of FIG. 6, pixels of odd-numbered frames and even-numbered frames are alternately extracted in a quincunx shape to generate a mixed screen, and a screen in which the two frames are mixed is used as a unit of a predetermined size. Divide into blocks and output image data. The size of the coding block is 4 × in FIG.
Although illustrated as 4 pixels, it is actually 8 × 8 pixels. As a result, the number of blocks in the still mode is half that in the field mode and the frame mode.

As described above, the image data blocked by the motion adaptive blocking circuit 2 is input to the image coding circuit 4 and is compressed while controlling the information amount in units of 26 block pairs. . First, the DCT circuit 6
Performs two-dimensional discrete cosine transform (DCT) on the image data in coding block units. DCT
Performs frequency analysis similarly to the Fourier transform, and the transform coefficient after DCT is divided into a DC coefficient corresponding to the pixel average value in the block and an AC coefficient having a different spatial frequency from low frequency to high frequency. The transform coefficients after DCT are stored in the block memory 7 for the 26 pairs of blocks. As shown in FIG. 3, from a pair of blocks, 8 in field mode and frame mode.
Coded blocks are generated, and in the still mode, 4 coded blocks are generated. Therefore, the number of coded blocks stored in the block memory 7 for controlling the amount of information to be constant is 104 at the minimum and 208 at the maximum.
The number of encoded blocks becomes variable.

The quantization parameter generation circuit 11 calculates the activity of each input coding block and further sets the sum as the total activity. Here, the activity of a coding block is an index indicating whether the coding block has a large amount of information or a small amount of information, and is obtained by performing a predetermined arithmetic process on the transform coefficient value of the coding block. . When a specific quantization parameter is set, there is a strong statistical correlation between the activity value and the amount of compressed data after data compression, and for a specific activity value, the quantization parameter and data compression were performed. Since the subsequent compressed data amount has a strong statistical correlation, the quantization parameter necessary for controlling the compressed data amount to a target value can be estimated for the coding block having a certain activity value. Here, the quantization parameter is a parameter indicating the fineness of quantization. The quantization parameter generation circuit 11 calculates the quantization parameter of each coding block according to the value of the calculated activity so that the total of the compressed data amount of each coding block stored in the block memory 7 becomes the target data amount. Is output to the quantization circuit 8.

104 stored in the block memory 7 once
The transform coefficient data of the code blocks of 208 to 208 are sequentially output from the block memory 7 after the quantization parameter for each coded block is generated by the quantization parameter generation circuit 11. Then, the quantization circuit 8 quantizes the transform coefficient of the coding block with the same quantization parameter according to the quantization parameter set for each coding block. However, in consideration of the human visual characteristic that the detection sensitivity of high-frequency information is lower than that of low-frequency information, when a certain quantization parameter is given, conversion after DCT is performed. Low frequency AC coefficient
The coefficients are quantized relatively finely, and the high frequency AC coefficients are quantized relatively coarsely. Further, the fineness of the quantization of the DC coefficient is always constant.

In the variable length coding circuit 9, the AC coefficient quantized by the quantizing circuit 8 is scanned from low frequency to high frequency, and the continuous number of coefficients having a value of 0 (run length) and 0.
After generating a pair of the value (level) of the coefficient having a value other than, the pair is Huffman-coded into a variable length code according to a predetermined Huffman coding table. The shorter the run length is and the lower the level is, the higher the probability of occurrence of the pair is, so the code length corresponding thereto is short, and in the opposite case, the code length is long. However, the DC coefficient is handled separately from the AC coefficient, and fixed-length codes are assigned. The variable-length encoded compressed data is stored in the buffer memory 10 and then output from the output terminal 5 as compressed data. However, the block mode and the quantization parameter are input to the buffer memory 10 on a block-by-block basis and on a coding block basis, and are multiplexed with the compressed data.

Next, the decoding processing circuit of the image coding apparatus shown in FIG. 2 operates as follows. The compressed data read from the magnetic tape is input from the input terminal 12 to the image decoding circuit 1
3 and the data is decompressed for each coding block. First, the compressed data is temporarily stored and held in the buffer memory 16, and then the variable length decoding circuit 17 decodes the variable length code of the pair of 0 run length and level to reproduce the original quantized transform coefficient. Next, the inverse quantization circuit 18 performs inverse quantization according to the quantization parameter that is multiplexed on the compressed data in units of coding blocks to reproduce transform coefficients,
The IDCT circuit 19 reproduces the original image data in coding block units by the two-dimensional inverse discrete cosine transform.

The motion adaptive block interpolating circuit 14 holds the image data reproduced by the above processing for two frames, and then, from the output terminal 15 to the HDT in accordance with the display scanning order.
Output as image data of V signal. However, the motion adaptive block interpolating circuit 14 performs the reverse processing of the motion adaptive blocking circuit 2 in FIG. 1, and switches its processing method according to the block mode multiplexed in block units in the compressed data. For the block in the field mode or the frame mode, the image decoding circuit 1
The image data reproduced in the coding block unit in 3 is output in the display scanning order after holding for 2 frames, but the block in the still mode is reproduced in the coding block unit in the image decoding circuit 13. The image data is treated as image data common to both the odd frame and the even frame, and the same image data is stored in the odd frame and the even frame forming the two frames, and then output in the display scanning order. In the still mode, the number of coded blocks reduced to half by the above block interpolation processing is restored.

Next, a second embodiment of the present invention will be described.
FIG. 7 is a block diagram of an encoding processing circuit of an image encoding apparatus which is a second embodiment of the present invention. Also, FIG.
FIG. 3 is a block diagram of a decoding processing circuit of the image encoding device. In the encoding processing circuit of the image encoding device shown in FIG. 7, 20 to 22 are three image encoding circuits, and 23 to
Reference numeral 25 is an output terminal for three compressed data, and 26 is a block distribution circuit. The HDTV image data input terminal 1, the motion adaptive blocking circuit 2, and the block mode determination circuit 3 are
This is the same as the case of the first embodiment of FIG. In the decoding processing circuit of the image coding apparatus shown in FIG.
Numerals 29 to 29 are input terminals for three compressed data, 3 to 32 are three image decoding circuits, and 33 is a block mixing circuit. The motion adaptive block interpolation circuit 14 and the HDTV image data output terminal 15 are the same as those in the first embodiment of FIG.

First, the operation of the encoding processing circuit of the image encoding apparatus shown in FIG. 7 will be described. The block mode determination circuit 3 detects a change (movement) in the image content over two frames from the image data of the HDTV signal input from the input terminal 1 and determines the block mode for each block of 16 × 16 pixels. The motion adaptive blocking circuit 2 switches the processing method according to the determined block mode, and blocks the blocks into eight or four coded blocks and outputs the image data. The size of the coding block is 8 × 8 pixels. The operations of the motion adaptive blocking circuit 2 and the block mode determination circuit 3 are the same as in the case of the first embodiment shown in FIG.

Then, the block distribution circuit 26 distributes the blocked image data to three channels in a unit of a pair of blocks forming eight or four encoded blocks. Since one frame is divided into 72 × 65 blocks, the image data of 2 frames is 4680.
It consists of pairs of blocks. Therefore, the coded block generated from the pair of 1560 blocks is distributed to each channel. In the still mode, the coded blocks are generated only once in two frames, so that the number of coded blocks normally processed in each channel is not uniform. The image data of each channel is
Data is compressed by one of the image coding circuits 20 to 22, and the compressed data is output from the output terminals 23 to 25.
The operation of the image coding circuits 20 to 22 is the same as that of the first embodiment shown in FIG. The block mode determined by the block mode determination circuit 3 is multiplexed on the compressed data in block units.

Next, the operation of the decoding processing circuit of the image coding apparatus shown in FIG. 8 will be described. The compressed data read from the magnetic tape is input to the three image decoding circuits 30 to 32 from the three input terminals 27 to 29, respectively, and the image data is reproduced by decompressing the data in encoded block units. The operations of these image decoding circuits 30 to 32 are the same as in the case of the first embodiment shown in FIG. The reproduced image data of each channel is mixed in block units in the block mixing circuit 33. This block mixing circuit 3
3 performs the reverse processing of the block distribution circuit 26 shown in FIG. The motion adaptive block interpolation circuit 14 restores the original image data while switching the processing method according to the block mode multiplexed in the compressed data, and outputs it as HDTV image data from the output terminal 15 in the display scanning order. The operation of the motion adaptive block interpolation circuit 15 is shown in FIG.
This is the same as the case of the first embodiment shown in FIG.

In this embodiment, since the image data is divided into three channels and the image encoding processing is performed, the operation speeds required for the image encoding circuits 20 to 22 and the image decoding circuits 30 to 32 are the same. About 1 / compared to the first embodiment
3 is enough.

Next, a third embodiment of the present invention will be described.
FIG. 9 is a block diagram of an encoding processing circuit of an image encoding apparatus which is a third embodiment of the present invention. However, the description of the decoding processing circuit for performing the reverse data expansion is omitted. In the encoding processing circuit of the image encoding device shown in FIG. 9, 34 is an input terminal for the image data of the current TV signal,
Reference numeral 35 is an input terminal for an operation mode signal indicating the HDTV signal processing mode or the current TV signal processing mode, 36 is a blocking circuit, and 37 is a data switching circuit. In addition, HDT
The operation of the input terminal 1 of the image data of the V signal, the motion adaptive blocking circuit 2, the block mode determination circuit 3, the block distribution circuit 26, the image encoding circuits 20 to 22 and the output terminals 23 to 25 of the compressed data are shown in FIG. Is exactly the same as the case of the second embodiment.

The block mode determination circuit 3 has an input terminal 1
From the image data of the HDTV signal input from, the change (motion) of the image content over two frames is detected, and the block mode is determined. The motion adaptive blocking circuit 2 switches the processing method according to the determined block mode and outputs the image data in blocks. And
The block distribution circuit 26 distributes the blocked image data to three channels in block units. Motion adaptive blocking circuit 2, block mode determination circuit 3,
The operation of the block distribution circuit 26 is the same as that of the second embodiment shown in FIG. The image data of each channel is compressed by one of the image encoding circuits 20 to 22. The operation of the image coding 20 to 22 is the same as that of the first embodiment shown in FIG.

Here, one specific image coding circuit 20
A data switching circuit 37 is provided on the input side of
1-channel H output from the block distribution circuit 26
The image data of the DTV signal and the image data of the current TV signal input from the input terminal 34 and blocked by the blocking circuit 36 are switched according to the operation mode signal supplied from the input terminal 35. The blocking circuit 36 holds the image data of the current TV signal for one frame, divides the one frame into one screen into 8 × 8 pixel blocks, and outputs the image data. Since the pixel rate of the HDTV signal is about four times that of the current TV signal, if the block distribution circuit 36 divides the image data of the HDTV signal into three channels as described above, the image data of one channel will be the current TV signal. The pixel rate is slightly more than 1 time higher than that of the image data. Therefore, if the horizontal and vertical blanking periods, which are not used in the current TV signal, are also used when processing the HDTV signal, the same image coding circuit 20 is used.
Can be shared.

Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram of an encoding processing circuit of an image encoding apparatus which is the fourth embodiment of the present invention. However, description of the decoding processing circuit is omitted. In the encoding processing circuit of the image encoding apparatus shown in FIG. 10, 1 is HD.
An input terminal for image data of a TV signal, 3 is a block mode determination circuit, 38 is a motion adaptive DCT circuit, 39 is a coefficient coding circuit, and 5 is an output terminal of compressed data. Here, in the motion adaptive DCT circuit 38, 40 is a motion adaptive block forming circuit, 6 is a DCT circuit, and 41 is a motion adaptive block thinning circuit. In the coefficient coding circuit 39, 7 is a block memory, 8 is a quantization circuit, 9 is a variable length coding circuit, 10 is a buffer memory, and 11 is a quantization parameter generation circuit.

The block mode determination circuit 3 has an input terminal 1
Holds only 2 frames of HDTV image data input from, and changes (movement) of image contents over 2 frames
Is detected to determine the block mode in block units.
The operation of the block mode determination circuit 3 is the same as that of the first embodiment shown in FIG. Next, the motion adaptive DCT circuit 38 performs HDT in accordance with the determined block mode.
The V image data is subjected to motion adaptive DCT processing in block units of 16 × 16 pixels. That is, first, the motion adaptive blocking circuit 40 divides the image data into blocks according to the block mode, and generates a plurality of coded blocks of 8 × 8 pixels. FIG. 11 shows how the blocks are formed. In the case of the field mode, as shown in (a)., The odd field and the even field are treated as different screens, and the fields are treated as one screen, and the blocks are divided into coding blocks. In the frame mode and the still mode, as shown in (b)., A frame composed of an odd field and an even frame is treated as one screen, and the coded block is divided into blocks. In any case, eight coded blocks are generated from a pair of blocks extracted from two frames. Unlike the motion adaptive blocking circuit 2 in the first embodiment of FIG. 1, the number of coding blocks in the still mode is not reduced.

Next, the image data blocked by the motion adaptive blocking circuit 40 is converted by the DCT circuit 6 into transform coefficient data by a two-dimensional discrete cosine transform in block units of 8 × 8 pixels. The operation of the DCT circuit 6 is exactly the same as that of the first embodiment shown in FIG. The motion adaptive block thinning circuit 41 thins the transform coefficient data in block units as shown in FIG. 12 only when the block mode is the still mode. As shown in FIG. 12, for a pair of blocks of odd frames and even frames whose image contents are almost the same, the blocks of even frames are thinned out, and only the blocks of odd frames are left and divided into four coding blocks. Output. However, in the field mode and the frame mode, all blocks are output without any processing. As a result, in the still mode, the number of blocks to be subjected to data compression processing is reduced to half.

DC output from the motion adaptive DCT circuit 38
The coefficient data after T is compressed by the coefficient coding circuit 39 in units of coding blocks, and the generated compressed data is output from the output terminal 5. First, a predetermined number of coded blocks of transform coefficient data are stored in the block memory 7. 104 to 208 coded blocks generated from 26 pairs of blocks are retained. The quantization parameter generation circuit 11 calculates the activity for each coding block and the sum thereof, and determines the quantization parameter of each coding block from these values. Then, the transform coefficient data of the predetermined number of coded blocks temporarily held in the block memory 7 is quantized by the quantization circuit 8 according to the determined quantization parameter. Variable length coding circuit 9
Then, the quantized transform coefficient is variable-length coded and output to the buffer memory 10. The block mode and the quantization parameter are also stored in the buffer memory 10 after being multiplexed with the variable-length encoded compressed data. The compressed data stored in the buffer memory 1 is sequentially output from the output terminal 5. The operations of the block memory 7, the quantization circuit 8, the variable length coding circuit 9, the buffer memory 10 and the quantization parameter generation circuit 11 are the same as those in the first embodiment of FIG.

Next, a fifth embodiment of the present invention will be described.
FIG. 13 is a block diagram of an encoding processing circuit of an image encoding device which is a fifth embodiment of the present invention. However, description of the decoding processing circuit is omitted. In the encoding processing circuit of the image encoding device shown in FIG.
Reference numeral 44 is three image coding circuits, 45 to 47 are output terminals for three compressed data, and 48 is a block distribution circuit. H
The input terminal 1 for DTV image data, the block mode determination circuit 3, and the motion adaptive DCT circuit 38 are the same as in the case of the fourth embodiment of FIG.

First, the block mode determination circuit 3 determines from the image data of the HDTV signal input from the input terminal 1
Detects changes (motion) in image content over two frames,
Determine the block mode. Motion adaptive DCT circuit 38
Outputs DCT processing and blocking processing of image data while switching the processing method according to the determined block mode. The operations of the block mode determination circuit 3 and the motion adaptive DCT circuit 38 are the same as in the case of the fourth embodiment shown in FIG. Then, the block distribution circuit 48
Assigns the conversion coefficient data to three channels in block units. The operation of the block distribution circuit 48 is the same as that of the block distribution circuit 26 in the second embodiment of FIG. 7 except that the data to be distributed is not the image data but the transform coefficient data. The transform coefficient data of each channel is data-compressed by one of the coefficient coding circuits 42 to 44. The operation of the coefficient coding circuits 42 to 44 is shown in FIG.
This is the same as the case of the fourth embodiment shown in FIG. The compressed data is output from the output terminals 45 to 47. The block mode determined by the block mode determination circuit 3 is multiplexed on the compressed data in block units.

Since this embodiment is equivalent to performing image coding processing by dividing image data into three channels, the operation speed of the coefficient coding circuits 42 to 44 is higher than that of the fourth embodiment. About 1/3.

Next, a sixth embodiment of the present invention will be described.
FIG. 14 is a block diagram of an encoding processing circuit of an image encoding apparatus which is a sixth embodiment of the present invention. However, the description of the decoding processing circuit for performing the reverse data expansion is omitted. In the encoding processing circuit of the image encoding apparatus shown in FIG. 14, 34 is an input terminal of image data of a current TV signal, 35 is an input terminal of an operation mode signal indicating an HDTV signal processing mode or a current TV signal processing mode, and 36 is A block circuit, 49 is a DCT circuit, and 50 is a data switching circuit. In addition, the input terminal 1 of the image data of the HDTV signal, the block mode determination circuit 3, the motion adaptive DCT circuit 3
8, block distribution circuit 48, coefficient coding circuits 42-4
4. The operation of the compressed data output terminals 45 to 47 is shown in FIG.
This is exactly the same as the case of the fifth embodiment.

The block mode determination circuit 3 has an input terminal 1
From the image data of the HDTV signal input from, the change (motion) of the image content over two frames is detected, and the block mode is determined. The motion adaptive DCT circuit 38 performs DCT processing and block processing of the image data while switching the processing method according to the determined block mode, and outputs the image data. Then, the block distribution circuit 48 distributes the transform coefficient data to the three channels in block units. The operations of the motion adaptive DCT circuit 38, the block mode determination circuit 3, and the block distribution circuit 48 are the same as those in the fifth embodiment shown in FIG. The transform coefficient data of each channel is data-compressed by one of the coefficient coding circuits 42 to 44. The operation of the coefficient coding circuits 42 to 44 is the same as in the case of the fourth embodiment shown in FIG.

Here, a specific one coefficient coding circuit 42
A data switching circuit 50 is provided on the input side of
1-channel H output from the block distribution circuit 48
The conversion coefficient data of the DTV signal and the DCT which is input from the input terminal 34 and then blocked by the blocking circuit 36.
The conversion coefficient data of the current TV signal DCT-processed by the circuit 49 is switched according to the operation mode signal given from the input terminal 35. Blocking circuit 36 is the current TV
The image data of the signal is held for one frame, and
A frame is regarded as one screen and divided into coding blocks of 8 × 8 pixels, and image data is output. Further, the DCT circuit 49 performs a two-dimensional discrete cosine transform for each coding block. The pixel rate of the HDTV signal is the current TV
Since the signal is about four times as large as the signal, if the block distribution circuit 48 divides the conversion coefficient data of the HDTV signal into three channels as described above, the conversion coefficient data of one channel is slightly more than one time that of the current TV signal. It becomes the data amount of. Therefore, the same coefficient encoding circuit 42 can be shared by using the horizontal and vertical blanking periods, which are not used in the current TV signal, when processing the HDTV signal.

The embodiments of the present invention have been described above in detail. As a method of motion adaptive blocking processing, which holds a plurality of frames, performs motion detection in units of blocks of a predetermined size, and switches the method of generating a plurality of coded blocks from each block according to the determined block mode, Various methods other than those described in the embodiments can be considered. For example, more than two frames may be processed, and the block size is 16 × 1.
It does not have to be 6 pixels. Further, the block size may be other than 8 × 8 pixels depending on the image encoding process.
The block mode is not limited to the three types described in the embodiments. Various methods can be applied as a method of block mode determination processing by motion detection.

Blocks are distributed to a plurality of channels,
When data is individually compressed by the image coding circuit, the number of channels does not have to be 3 as in the embodiment described above. Further, the blocks may be distributed unbalanced to each channel, the information amount allocation to each channel may be unbalanced, and the allocation state may be adaptively adjusted according to the characteristics of the signal. You may change to. There may be a data multiplexing circuit in which the compressed data of each output are multiplexed, and a data redistribution circuit that redistributes the compressed data into a plurality of channels may exist after the data multiplexing circuit.

The present invention can be similarly applied even if DCT is not used as the image coding processing method.
It goes without saying that the present invention can be applied to various cases such as a color signal including a luminance signal and two kinds of color difference signals as the video signal. In that case, the color difference signal may be sub-sampled with respect to the luminance signal. Luminance signal and 2
The present invention can be applied after the types of color difference signals are interleaved in predetermined data units. The image coding apparatus according to the present invention can be applied not only to recording / reproducing on a magnetic tape in a digital VTR, but also to recording / reproducing on an optical disk or transmission via a data communication line.

[0048]

According to the present invention, the input video signal H
With respect to the DTV signal, it is detected whether or not there is a change (movement) in the image content over a predetermined plurality of frames in units of a two-dimensional block having a predetermined size. By providing the motion adaptive blocking means for reducing the number of blocks so that the block is coded only once before the image coding means for compressing the image data, the amount of information that can be assigned to each block is reduced. Since the size is larger than that of the conventional method, it is possible to realize an image encoding apparatus having a higher data compression rate than the conventional method while maintaining high image quality.

Further, the motion adaptive block forming means for performing the processing as described above on the input HDTV signal, the block distributing means for distributing the output data thereof into a plurality of channels in block units, and the data compression for the distributed data. In the HDTV signal processing mode, an HDTV signal preprocessed by the motion adaptive blocking means and block distributing means is provided in front of a specific one of the image coding means. In the current TV signal processing mode, by providing a signal switching means for selecting the input current TV signal itself, the HDTV signal and the current T
It is possible to realize a high-quality image encoding device compatible with both V signals.

[Brief description of drawings]

FIG. 1 is a block diagram of an encoding processing circuit of an image encoding apparatus that is a first embodiment of the present invention.

FIG. 2 is a block diagram of a decoding processing circuit of the image coding apparatus according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram showing an operation of a motion adaptive block formation circuit in the image encoding device of FIG.

FIG. 4 is a conceptual diagram illustrating an operation of blocking processing in a field mode of a motion adaptive blocking circuit.

FIG. 5 is a conceptual diagram illustrating an operation of blocking processing in a frame mode of a motion adaptive blocking circuit.

[Fig. 6] Fig. 6 is a conceptual diagram illustrating an operation of blocking processing in a still mode of a motion adaptive blocking circuit.

FIG. 7 is a block diagram of an encoding processing circuit of an image encoding device which is a second embodiment of the present invention.

FIG. 8 is a block diagram of a decoding processing circuit of an image coding apparatus that is a second embodiment of the present invention.

FIG. 9 is a block diagram of an image coding apparatus that is a third embodiment of the present invention.

FIG. 10 is a block diagram of an image coding apparatus according to a fourth embodiment of the present invention.

11 is a conceptual diagram illustrating an operation of a motion adaptive block formation circuit in the image encoding device in FIG.

12 is a conceptual diagram illustrating an operation of a motion adaptive block thinning circuit in the image encoding device in FIG.

FIG. 13 is a block diagram of an image coding apparatus that is a fifth embodiment of the present invention.

FIG. 14 is a block diagram of an image coding apparatus that is a sixth embodiment of the present invention.

[Explanation of symbols]

3 ... Block mode determination circuit, 2/40 ... Motion adaptive block conversion circuit, 38 ... Motion adaptive DCT circuit, 41 ... Motion adaptive block thinning circuit, 14 ... Motion adaptive block interpolation circuit, 4.20-22 ... Image coding circuit , 13.30 ~ 3
2 ... Image decoding circuit, 39.42-44 ... Coefficient coding circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Ichige 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture

Claims (12)

[Claims] 1. An image encoding apparatus for compressing data of a video signal, the block mode detecting a change in image content over N frames (N is an integer of 2 or more) for the video signal in units of blocks of a predetermined size. According to the output signal from the determining means and the block mode determining means, in a still block having almost no change in image content, pixels are collected from the block only once in every N frames to obtain one or more encoded blocks. In the other blocks, the motion adaptive block forming unit that collects pixels from the block for each frame to form one or more encoded blocks, and compresses the output signal of the motion adaptive block forming unit. An image encoding device comprising an image encoding means. 2. The image coding apparatus according to claim 1, wherein the motion adaptive blocking means collects pixels from all N frames at a rate of 1 / N in all still blocks in which image content hardly changes. An image coding apparatus characterized by comprising one or more coding blocks as a whole. 3. The image coding apparatus according to claim 1, wherein the motion adaptive block forming means selects, in a still block with almost no change in image content, from the block in any one of N frames. An image coding apparatus characterized by extracting pixels to form one or more coding blocks. 4. The image coding apparatus according to claim 1, wherein the block mode determination means detects a change in the image content over two frames in units of blocks of a predetermined size, and the motion adaptive blocking means means the block mode determination means. An image coding apparatus, wherein pixels are collected from the block only once in every two frames or in every one frame in accordance with an output signal from the block to form one or more coded blocks. 5. An image coding apparatus for compressing data of a plurality of types of video signals having different resolutions, wherein the image content of N frames (N is an integer of 2 or more) of the first video signal having a high resolution is displayed. According to the block mode determination means for detecting a change in units of blocks of a predetermined size and the still block in which the image content hardly changes in accordance with the output signal from the block mode determination means, 1 per N frames.
Motion adaptation in which pixels are collected from the block only once to form one or more coded blocks, and in other blocks, pixels are collected from the block for each frame to form one or more coded blocks The image forming apparatus comprises block forming means, data distribution means for distributing the output signal of the motion adaptive block forming means to a plurality of channels, and a plurality of image encoding means for data compression of the output signal of the data distributing means to each channel. Further, in front of the specific one image coding means, one channel of the output signal of the data distribution means for the first video signal of high resolution and the second channel of low resolution
An image coding apparatus comprising a signal switching means for switching the video signal from the video signal after forming the coding block. 6. The image coding apparatus according to claim 5, wherein the data distribution means distributes the output signal of the motion adaptive blocking means for the first video signal to three channels. Encoding device. 7. An image coding apparatus for compressing data of a video signal, the block mode detecting a change in image content over N frames (N is an integer of 2 or more) for the video signal in block units of a predetermined size. According to the output signal from the determining means and the block mode determining means, in a still block having almost no change in image content, pixels are collected from the block only once in every N frames to obtain one or more encoded blocks. In addition to the configuration, each coding block is subjected to orthogonal transform to generate transform coefficient data, and in other blocks, pixels are collected from the block for each frame to configure one or more coding blocks. In addition, the motion adaptive orthogonal transform means for performing orthogonal transform on each coded block to generate transform coefficient data, and the motion adaptive orthogonal transform procedure. Image encoding apparatus comprising: a coefficient encoding means for data compressing the output signal. 8. The image coding apparatus according to claim 7, wherein the motion adaptive orthogonal transform means collects pixels from all N frames at a rate of 1 / N in all still blocks in which the image content hardly changes. An image coding apparatus, characterized in that one or more coding blocks are configured as described above, and each coding block is subjected to orthogonal transform to generate transform coefficient data. 9. The image coding apparatus according to claim 7, wherein the motion adaptive orthogonal transformation means selects a still block in which the image content hardly changes from the block in any one of N frames. An image coding apparatus, wherein pixels are extracted to form one or more coded blocks, and each coded block is subjected to orthogonal transform to generate transform coefficient data. 10. The image coding apparatus according to claim 7, wherein the block mode determination means detects a change in the image content over two frames in block units of a predetermined size, and the motion adaptive orthogonal transformation means performs the block mode determination means. Depending on the output signal from the block, the pixels are collected from the block only once in two frames or in each frame to form one or more coded blocks, and orthogonal transform is performed on each coded block. An image coding apparatus, which is configured to generate transform coefficient data according to the above method. 11. An image coding apparatus for compressing data of a plurality of types of video signals having different resolutions, the first having a high resolution.
Frames for N video signals (N is an integer of 2 or more)
Once in every N frames in the block mode judging means for detecting the change in the image content over a block of a predetermined size and the still block in which the image content hardly changes in accordance with the output signal from the block mode judging means. Pixels are collected from the block to form one or more coded blocks, and in other blocks, 1
Pixels are collected from the block for each frame to form one or more coded blocks, and the motion adaptive orthogonal transform means for generating transform coefficient data by subjecting each coded block to orthogonal transform, and the motion adaptive Data distribution means for distributing the output signal of the orthogonal transformation means to a plurality of channels, and a plurality of coefficient coding means for data compression of the output signal of the data distribution means to each channel are provided.
Before each coefficient coding means, a coding block is formed from one channel of the output signal of the data distribution means for the first video signal with high resolution and the second video signal with low resolution, and each coding block An image coding apparatus, comprising: a signal switching unit for switching between a signal after orthogonal transformation with respect to the signal. 12. An image coding apparatus according to claim 11, wherein the data distribution means distributes the output signal of the motion adaptive orthogonal transformation means for the first video signal to three channels. Encoding device.