JPH066777A - Picture encoding device - Google Patents

Abstract

PURPOSE:To decrease the cost of the picture encoding device which corresponds to the current TV and high definition TV by providing a frame synthesizing block circuit collecting picture elements from plural frames on the front of the picture encoding circuit performing data compression and constructing a two-dimensional block being the basic unit of encoding. CONSTITUTION:The sampling of high definition TV signals is performed by the sampling frequency of 44.55MHz with high resolution and the analog video signal is converted into the digital picture data by the A/D conversion processing and inputted from an input terminal 1 to a picture encoding device 3. In this case, one frame of effective picture element number is 1152X1040 picture elements. Then, two frames are synthesized for the picture data of a TV signal to generate one screen in a 2-frame synthesizing block processing circuit 2 to the input. Further, it is divided into blocks of the prescribed size and outputted to the circuit 3. In the circuit 3, the data compression is performed in a block unit of the prescribed size and the compression data amount is kept constant. Thus, either of the high definition TV signal or the current TV signal is selected, enabling the correspondence to both of them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus used in a digital VTR or the like for digitally recording a video signal on a magnetic tape, and particularly to a high quality image coding apparatus for data compression of a high definition video signal. Regarding

[0002]

2. Description of the Related Art As an image coding apparatus for compressing a video signal to reduce the amount of information, for example, IEE Transactions on Consumer.
Electronics Vol. 35, No. 3, August 1989, pp. 450-457 (IEEE Transactions on
Consumer Electronics, Vol. 35, No. 3 (August 198
9), pp. 450-457), an image coding apparatus used in the digital VTR is known.

This digital VTR is based on the current TV signal,
That is, a video signal having a total of 525 vertical lines in a frame and a frame frequency of 29.97 frames / second is data-compressed and recorded on a magnetic tape, and the recorded data is reproduced to expand the data to produce a video signal. It is what is output. The number of effective pixels in a frame recorded on the magnetic tape is 720 × 480 pixels, and the number of pixels that need to be processed in one second (hereinafter, referred to as a pixel rate) is about 10 M pixels / second.

The image coding apparatus, when coding a video signal, converts an input video signal from an analog signal into digital image data by A / D conversion, and converts the image data into a two-dimensional block of a predetermined size for each frame. Split,
Data compression is performed by an image coding process including discrete cosine transform (DCT), quantization, and variable length coding. Also, when decoding video signals, variable length decoding,
Data is expanded by image decoding processing including inverse quantization and inverse discrete cosine transform to generate image data, and then the digital image data is converted into D /
It is converted into an analog video signal by A conversion and output.

This is because each frame of the video signal is independently
That is, the intra frame coding using the DCT is performed without referring to the information of other frames.

[0006]

However, the above-mentioned image encoding device according to the prior art is for data compression of the current TV signal, and is compatible with a higher resolution high definition TV signal (hereinafter referred to as HDTV signal). Was not considered.

The HDTV signal has, for example, 1125 total vertical lines in the frame and a frame frequency of 30 frames / sec. The frame frequency is almost the same as that of the current TV signal, but the total vertical line number in the frame is It is more than double. In a typical example, the number of effective pixels in the frame is 1152 × 1040 pixels, and the pixel rate is about 35 M pixels / sec, which is about four times that of the current TV signal.

In the case of a digital VTR, HD
There is a demand to suppress the recording data rate of TV signals to about twice the recording data rate of current TV signals. In that case, it is necessary to increase the data compression rate of the image coding apparatus to about twice. However, in the image coding apparatus according to the above-mentioned conventional technique, if the data compression rate is increased in this way, coding distortion increases, and it cannot be put to practical use.

As an image coding process capable of increasing the data compression rate, a pixel-by-pixel difference between frames is generated and coded, that is, a predicted image of the current frame is generated from a previous frame and an actual current image is generated. Inter-frame coding is known in which a prediction error from a frame image is coded. In particular, motion compensation is often combined between detecting a motion vector between the previous frame and the current frame for each block of a predetermined size and shifting the previous frame by the detected motion vector to generate a predicted image of the current frame. .

However, in the inter-frame coding, since it is necessary for the coding side and the decoding side to hold the same image of the previous frame, the local decoding for generating the same reproduced image as that obtained on the decoding side. Processing is required on the encoding side.
Further, when the motion compensation is adopted, the motion vector detecting process for detecting the motion vector is required on the encoding side. Therefore, in the interframe coding process, the circuit scale of the image coding device is significantly increased as compared with the conventional intraframe coding.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to inexpensively realize an image coding apparatus for an HDTV signal which can realize a higher data compression rate while maintaining high image quality. Another object of the present invention is to inexpensively realize a high-quality image encoding device capable of performing image encoding processing on both HDTV signals and current TV signals.

[0012]

In order to achieve the above object, the present invention collects a predetermined number of pixels from a predetermined plurality of frames for an HDTV signal, which is a two-dimensional basic unit of encoding processing. A preprocessing circuit that performs a frame synthesis block forming process that constitutes a block is provided in front of the image coding circuit.

Further, in order to achieve the above-mentioned other object, the present invention performs the above-mentioned frame synthesis block forming process and a block distributing process for distributing the blocked signal to a plurality of channels for an HDTV signal. A preprocessing circuit and a plurality of image coding circuits for compressing the generated plurality of types of preprocessed signals are provided, and a specific one of them is provided.
A signal switching circuit for selecting the preprocessed signal in the HDTV signal processing mode and the current TV signal itself in the current TV signal processing mode is provided in front of each image coding circuit.

[0014]

In the frame synthesis block forming process, pixels are collected from a plurality of frames to form a two-dimensional block. Therefore, not only spatial correlation within a frame but also temporal correlation between frames exists between pixels in a block. Therefore, not only the spatial correlation but also the temporal correlation can be effectively used. Therefore, by performing the image coding processing by dividing into blocks as described above, it is possible to use the block in the frame more than the conventional method. A high data compression rate can be realized. This is a method of collectively compressing a plurality of frames and can be called intra-multiframe coding.

Further, it is also possible to distribute the signals subjected to the frame synthesis block processing as described above to a plurality of channels by the block distribution processing and individually perform the image coding processing on the respective signals. At this time, by setting the pixel rate of the HDTV signal of one specific channel to be substantially the same as that of the current TV signal, the signal switching circuit outputs H as an input to the image encoding circuit that processes the HDTV signal of that channel.
It is possible to switch between the DTV signal and the current TV signal. As a result, it is possible to inexpensively realize a high-quality image encoding device capable of performing image encoding processing on both HDTV signals and current TV signals.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an image coding apparatus which is a first embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 1, 1
Is an input terminal for image data of an HDTV signal, 2 is a 2-frame synthesizing block forming circuit, 3 is an image encoding circuit, and 4 is an output terminal for compressed data. In the image coding circuit 3, 5 is a block memory, 6 is a DCT circuit, 7 is a quantization circuit, 8 is a variable length coding circuit, 9 is a buffer memory,
Reference numeral 10 is a quantization parameter generation circuit.

The HDTV signal is sampled at a sampling frequency of 44.55 MHz, converted from an analog video signal to digital image data by an A / D conversion process, and then input from the input terminal 1 to the image coding apparatus. .
The number of effective pixels in one frame is 1152 × 1040 pixels. The two-frame synthesizing block circuit 2 synthesizes two frames with respect to the image data of the HDTV signal input from the input terminal 1 to generate one screen, and further divides it into blocks of a predetermined size to generate an image coding circuit. Output to 3. The image coding circuit 3 performs data compression processing in units of blocks of a predetermined size, and performs control so that the amount of compressed data becomes constant in units of a predetermined number of blocks.

FIG. 2 shows how the two-frame synthesis block forming circuit 2 performs processing. In the image data of the input HDTV signal, as shown on the left side of FIG. 2, pixels are arranged in a grid to form one frame. In the odd-numbered frame and the even-numbered frame which form two frames, the pixels in the odd-numbered frame are indicated by circles and the pixels in the even-numbered frame are indicated by triangles. Two fields, each having half the number of vertical lines with respect to the frame, are offset in the vertical direction and overlap each other to form one frame. The solid lines show the lines that make up the odd field, and the broken lines show the lines that make up the even field.
Adjacent even fields and odd fields are images at times shifted by 1/60 seconds.

The two-frame synthesizing / blocking circuit 2 alternately extracts lines from odd-numbered frames and even-numbered frames and synthesizes the lines to generate one screen, as shown in the right side of FIG. Then, the image data is divided into blocks of a predetermined size as shown by the bold line, and the data compression processing is subsequently performed in the image encoding circuit 3. By synthesizing two frames in this way and performing block division, the correlation between pixels in a block becomes higher and the data compression rate can be made higher than in the conventional case where block division is performed for each frame. it can.

The block image data input to the image encoding circuit 3 is first stored in the block memory 5 in a predetermined number of blocks. The quantization parameter generation circuit 10 calculates the activity of each input block, and sets the sum as the total activity. Here, the activity of a block is an index indicating whether the image content of the block is fine and has a large amount of information, or the image is flat and has a small amount of information, and the activity of the block is predetermined with respect to the pixel value of the block. It is obtained by performing arithmetic processing. If you set a certain quantization parameter,
There is a statistically strong correlation between the activity value and the amount of compressed data after data compression, and for a certain activity value, the quantization parameter and the amount of compressed data after data compression are statistically strongly correlated. Therefore, with respect to the block having a certain activity value, the quantization parameter necessary for controlling the compressed data amount to the target value can be estimated. Here, the quantization parameter is a parameter indicating the fineness of quantization. The quantization parameter generation circuit 10 allocates a target data amount of compressed data for a predetermined number of blocks to each block according to the value of the total activity and the activity of each block, determines the quantization parameter of each block, and then performs quantization. Output to the circuit 7.

The image data of a predetermined number of blocks once held in the block memory 5 is sequentially output from the block memory 10 after the quantization parameter for each block is generated by the quantization parameter generation circuit 10. Then, the DCT circuit 6 performs a two-dimensional discrete cosine transform (DCT) on the image data in block units. The DCT performs frequency analysis similarly to the Fourier transform, and the transform coefficient after the DCT is divided into a DC coefficient corresponding to the pixel average value in the block and an AC coefficient having a different spatial frequency from low frequency to high frequency. . The quantization circuit 7 quantizes the transform coefficient of a block with the same quantization parameter according to the quantization parameter set for each block. However, in consideration of the human visual characteristic that the detection sensitivity of high-frequency information is lower than that of low-frequency information, when a certain quantization parameter is given, conversion after DCT is performed. Coefficient low frequency A
The C coefficient is relatively fine and the high frequency AC coefficient is relatively coarsely quantized. Further, the fineness of the quantization of the DC coefficient is always constant.

The variable-length coding circuit 8 scans the AC coefficients quantized by the quantizing circuit 7 from low frequencies to high frequencies, and determines the number of consecutive coefficients having a value of 0 (run length) and 0.
After generating a pair of the value (level) of the coefficient having a value other than, the pair is Huffman-coded into a variable length code according to a predetermined Huffman coding table. The shorter the run length is and the lower the level is, the higher the probability of occurrence of the pair is, so the code length corresponding thereto is short, and in the opposite case, the code length is long. However, the DC coefficient is handled separately from the AC coefficient, and fixed-length codes are assigned. The variable-length encoded compressed data is stored in the buffer memory 9 and then output from the output terminal 4 as compressed data. However, the quantization parameter of each block is also input to the buffer memory 9 and multiplexed with the compressed data.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram of an image coding apparatus which is a second embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 3, 11 to 14 are four image coding circuits, 15 to 18 are output terminals for four compressed data, and 19 is a block distribution circuit. The same components as those in FIG. 1 are designated by the same reference numerals as in FIG.

The 2-frame synthesizing block circuit 2 converts the image data of the HDTV signal input from the input terminal 1 into 2
It is divided into blocks of a predetermined size in the frame. The operation of the 2-frame synthesis block forming circuit 2 is the same as that of the first embodiment shown in FIG. Then, the block distribution circuit 19 evenly distributes the block-divided image data to four channels in block units. The image data of each channel is respectively image coding circuits 11-1.
The data is compressed by one of the four. Image encoding circuit 11
Operations 14 to 14 are the same as in the case of the first embodiment shown in FIG.

In the present embodiment, the image data is divided into four channels and the image encoding processing is performed, so that the operation speed of the image encoding circuits 11 to 14 is 1/4 times that of the first embodiment. Good.

Next, a third embodiment of the present invention will be described.
FIG. 4 is a block diagram of an image coding apparatus which is a third embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 4, 20 is an input terminal for image data of a current TV signal, 21 is an input terminal for an operation mode signal indicating the HDTV signal processing mode or the current TV signal processing mode, and 22 is a data switching circuit. is there. Note that FIG.
Constituent elements that are the same as the above are denoted by the same reference numerals as in FIG.

The two-frame synthesizing block division circuit 2 converts the image data of the HDTV signal input from the input terminal 1 into
The image data is divided into blocks of a predetermined size in two frames, and the block distribution circuit 19 evenly distributes the divided image data to four channels in block units. The operations of the 2-frame synthesizing block forming circuit 2 and the block distributing circuit 19 are the same as in the case of the second embodiment shown in FIG. The image data of each channel is compressed by one of the image encoding circuits 11-14. The operation of the image coding circuits 11 to 14 is the same as that of the first embodiment shown in FIG.

Here, one specific image encoding circuit 11
A data switching circuit 22 is provided on the input side of
1-channel H output from the block distribution circuit 19
The image data of the DTV signal and the image data of the current TV signal input from the input terminal 20 are switched according to the operation mode signal supplied from the input terminal 21. However, it is assumed that the image data of the current TV signal input from the input terminal 20 has already been divided into blocks. HDT
Since the pixel rate of the V signal is about four times that of the current TV signal, if the block distribution circuit 19 divides the image data of the HDTV signal into four channels as described above, the image data of one channel will be the current TV signal. The pixel rate is the same as that of the image data. Therefore, the same image encoding circuit 11 can be shared.

In the above-described first to third embodiments, the 2-frame synthesizing block forming circuit 2 collects pixels from 2 frames to form a block, but it is not limited to 2 frames but 4 frames or the like. May be.

Next, a fourth embodiment of the present invention will be described. FIG. 5 is a block diagram of an image coding apparatus which is the fourth embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 5, 1 is an input terminal for image data of an HDTV signal, 4 is an output terminal for compressed data, and 2 is an output terminal.
Reference numeral 3 is an offset sampling circuit, 24 is a 2-frame synthesizing block forming circuit, and 25 is an image encoding circuit.

The offset sampling circuit 23 arranges pixels in the image data of the HDTV signal input from the input terminal 1 so that the grid-like sampling pattern of each frame becomes a five-eye sampling pattern. Cut in half. FIG. 6 shows the state of this processing. In the image data of the input HDTV signal, as shown on the left side of FIG. 6, pixels are arranged in a grid to form one frame. In the odd and even frames that make up the two frames,
Pixels in odd frames are indicated by circles and pixels in even frames are indicated by triangles.

The offset sampling circuit 23 thins out the pixels of the frame of the grid-like sampling pattern by half to generate an output signal of the five-eye sampling pattern as shown on the right side of FIG. Pixel positions of the odd field shown by the solid line and the even field shown by the broken line are in a state with offsets in both the horizontal and vertical directions. Further, the pixel positions due to the five-eye sampling pattern are deviated between the odd-numbered frame and the even-numbered frame.
As a result, when the two frames are superposed, the original lattice-shaped sampling pattern is obtained. This output signal has the same frame frequency as the input signal, but the number of pixels in one frame is 1 /
It has been reduced by a factor of two.

The two-frame synthesizing block forming circuit 24 synthesizes two frames with respect to the image data output from the offset sampling circuit 23 to generate one screen, and further divides it into blocks of a predetermined size for image coding. Circuit 2
Output to 5. The image encoding circuit 25 performs a data compression process in units of blocks of a predetermined size, and performs control so that the amount of compressed data becomes constant in units of a predetermined number of blocks. FIG. 7 shows how the two-frame synthesis block forming circuit 24 performs processing. As shown on the left side of FIG. 7, the input image data has one frame in which pixels are arranged in a quincunx shape. In the odd-numbered frame and the even-numbered frame which form two frames, the pixels in the odd-numbered frame are indicated by circles and the pixels in the even-numbered frame are indicated by triangles.

The two-frame synthesis block forming circuit 2 superimposes the odd-numbered frame and the even-numbered frame, that is, embeds the pixels of the even-numbered frame in the vacant pixel positions in the odd-numbered frame, as shown in the right side of FIG. , One screen having a grid-like sampling pattern is generated. Then, the image data is divided into blocks of a predetermined size as shown by the thick line, and the data compression processing is subsequently performed in the image encoding circuit 25.

By synthesizing two frames and performing block division in this way, the correlation between pixels in a block becomes higher and the data compression rate becomes higher than in the conventional case where block division is performed frame by frame. can do.

Next, a fifth embodiment of the present invention will be described.
FIG. 8 is a block diagram of an image coding apparatus which is a fifth embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 8, 26 is a data distribution circuit, 27 and 28 are image coding circuits, and 29 and 30 are output terminals for compressed data. The same components as those in FIG. 5 are designated by the same reference numerals as those in FIG.

The offset sampling circuit 23 thins out the image data of the HDTV signal input from the input terminal 1 from the grid-like sampling pattern into a five-eyed sampling pattern to reduce the number of pixels by half. To do. The 2-frame synthesis block forming circuit 24 includes an offset sampling circuit 23.
The image data output from is divided into blocks of a predetermined size in two frames. The operation of the offset sampling circuit 23 and the two-frame synthesizing block circuit 24 is the same as that of the fourth embodiment shown in FIG. And
The block distribution circuit 26 evenly distributes the block-divided image data to two channels in block units. The image data of each channel is compressed by one of the image coding circuits 27 and 28. The operation of the image coding circuits 27 and 28 is the same as that of the first embodiment shown in FIG.

In this embodiment, since the image data is divided into two channels and the image encoding processing is performed, the operation speed of the image encoding circuits 27 and 28 is 1/2 times that of the fourth embodiment. Good.

Next, a sixth embodiment of the present invention will be described.
FIG. 9 is a block diagram of an image coding apparatus which is a sixth embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 9, 20 is an input terminal for a current TV signal, 21 is an HDTV signal processing mode or a current TV.
Input terminal for operation mode signal indicating signal processing mode, 3
1 is a data switching circuit. The same components as those in FIG. 8 are designated by the same reference numerals as those in FIG.

The offset sampling circuit 23 thins out the image data of the HDTV signal input from the input terminal 1 from the lattice-shaped sampling pattern into a five-eyed sampling pattern to reduce the number of pixels by half. To do. The two-frame synthesis block division circuit 24 includes the offset sampling circuit 2
The image data output from 3 is divided into blocks of a predetermined size in 2 frames, and the block distribution circuit 26
The image data divided into blocks is evenly distributed to two channels in block units. The operations of the offset sampling circuit 23, the two-frame combining block forming circuit 24, and the block distributing circuit 26 are the same as in the case of the fifth embodiment shown in FIG. The image data of each channel is compressed by one of the image coding circuits 27 and 28. The operation of the image coding circuits 27 and 28 is the same as that of the first embodiment shown in FIG.

Here, one specific image encoding circuit 27
A data switching circuit 31 is provided on the input side of
1-channel H output from the block distribution circuit 26
The image data of the DTV signal and the image data of the current TV signal input from the input terminal 20 are switched according to the operation mode signal supplied from the input terminal 21. However, it is assumed that the image data of the current TV signal input from the input terminal 20 has already been divided into blocks. HDT
Since the pixel rate of the V signal is about 4 times that of the current TV signal and the pixel rate of the output signal of the offset sampling circuit 23 is about twice that of the current TV signal, the block distribution circuit 26 uses the image data of the HDTV signal as described above. If divided into two channels, the image data of the one channel has a pixel rate equivalent to that of the image data of the current TV signal. Therefore, the same image encoding circuit 27 can be shared.

Next, a seventh embodiment of the present invention will be described.
FIG. 10 is a block diagram of an image coding apparatus which is a seventh embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted.
In the image coding apparatus shown in FIG. 10, 32 is a 4-frame synthesizing block circuit. The same components as those in FIG. 5 are designated by the same reference numerals as those in FIG.

The offset sampling circuit 23 thins out the image data of the HDTV signal input from the input terminal 1 from the lattice-shaped sampling pattern into a five-eyed sampling pattern to reduce the number of pixels by half. To do. The 4-frame synthesizing block forming circuit 32 includes an offset sampling circuit 23.
With respect to the image data output from, the four frames are combined to generate one screen, which is further divided into blocks of a predetermined size and output to the image encoding circuit 25. The image encoding circuit 25 performs a data compression process in units of blocks of a predetermined size, and performs control so that the amount of compressed data becomes constant in units of a predetermined number of blocks. FIG. 11 shows how the 4-frame synthesis block forming circuit 32 performs processing. As shown on the left side of FIG. 11, the input image data has pixels arranged in a quincunx shape to form one frame. In the first to fourth frames forming the four frames, the pixels of the first frame are white circles, the pixels of the second frame are white triangles, and the pixels of the third frame are black circles.
The pixels of the frame are indicated by black triangles.

In the 4-frame synthesis block forming circuit 32,
First, in the same manner as the operation of the two-frame synthesizing block forming circuit 24 in the fourth embodiment shown in FIG. 7, the first frame and the second frame are overlapped, and one sheet having a grid-like sampling pattern is formed. Generate the screen. Further, the third frame and the fourth frame are overlapped to generate one screen having a grid-like sampling pattern. Then, with respect to the two screens having the grid-like sampling pattern generated in this way, in the same manner as the operation of the two-frame synthesizing block forming circuit 2 in the first embodiment shown in FIG. Lines are alternately extracted from both screens and combined, and as shown in the right side of FIG.
Generates one screen. Then, the image data is divided into blocks of a predetermined size as shown by the thick line, and the data compression processing is subsequently performed in the image encoding circuit 25.

In this embodiment, the offset-sampled image data is divided into blocks by synthesizing four frames. Therefore, as compared with the fourth embodiment in which two frames are synthesized and the blocks are divided, The correlation between pixels is high and the data compression rate is high. As in the fifth embodiment, the present embodiment may be modified so that a block distribution circuit and a plurality of image coding circuits are provided. Further, similar to the sixth embodiment, in addition to the present embodiment, the current TV signal input terminal, the operation mode signal input terminal,
And changes may be made to provide a data switching circuit.

In the above fourth to seventh embodiments, the two-frame synthesis block forming circuit 24 collects pixels from two frames to form a block, or the four-frame synthesis block forming circuit 32 collects pixels from four frames. However, the number of frames is not limited to 2 or 4 and may be other.

Next, an eighth embodiment of the present invention will be described.
FIG. 12 is a block diagram of an image coding apparatus which is an eighth embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted.
In the image coding apparatus shown in FIG. 12, 1 is an input terminal for image data of an HDTV signal, 33 is a multi-frame synthesis block circuit, 34 is a block mode determination circuit, 3
Is an image encoding circuit, and 4 is an output terminal for compressed data.

Multi-frame synthesis block forming circuit 33
Switches the two frames of the image data of the HDTV signal input from the input terminal 1 into blocks by switching the block configuration according to the blocking mode which is switched according to the local property of the image data. FIG. 13 shows a block configuration of a processing result of the multi-frame synthesis block forming circuit 33. Pixels in odd frames are indicated by circles and pixels in even frames are indicated by triangles. A shown on the left of FIG.
Is a 2-frame mode, and like the operation of the 2-frame synthesizing block forming circuit 2 in the first embodiment shown in FIG. 1, pixels are collected from 2 frames to form a block.
Further, B shown on the right side of FIG. 13 is a one-frame mode, and blocks are obtained by taking blocks from each of two frames as in the conventional case. The image coding circuit 2 that follows the block shown in bold
The data compression processing in 5 is performed. The operation of the image coding circuit 25 is the same as that of the first embodiment shown in FIG.

The blocking mode determination circuit 34 analyzes the HDTV signal input from the input terminal 1 to determine the blocking mode. Normally, 2 frame mode is used,
If the image contents of the two frames are significantly different due to a scene change or extremely violent movement, the one frame mode is set. In the special case like the latter, since there is almost no temporal correlation between two frames, when the blocks are formed in the two-frame mode, the correlation between pixels in the block becomes lower than in the one-frame mode. This is because the data compression rate is reduced.

In this embodiment, since the processing mode of frame synthesis block formation is adaptively switched according to the nature of the image, it is possible to compare with the first embodiment in a special scene such as scene change or intense movement. The data compression rate can be increased.

Finally, a ninth embodiment of the present invention will be described. FIG. 14 is a block diagram of an image coding apparatus which is a ninth embodiment of the present invention. However, only the part related to the encoding process for data compression is shown. A description of the decoding process for performing the reverse data decompression will be omitted. In the image coding apparatus shown in FIG. 14, 1 is HDT
V signal image data input terminal, 23 is an offset sampling circuit, 35 is a multi-frame synthesis block circuit, 36 is a block mode determination circuit, 25 is an image coding circuit, and 4 is a compressed data output terminal.

The offset sampling circuit 23 thins out the image data of the HDTV signal input from the input terminal 1 from the lattice-shaped sampling pattern into a five-eye sampling pattern to reduce the number of pixels by half. To do. The operation of the offset sampling circuit 23 is the same as in the case of the fourth embodiment shown in FIG. Multi-frame synthesis block circuit 3
Reference numeral 5 blocks the four frames of the image data of the HDTV signal subjected to the offset sampling, by switching the block configuration according to the blocking mode which is switched by the local property of the image data. FIG. 15 shows a block configuration of the processing result of the multi-frame synthesis block forming circuit 35. Pixels in the first frame forming the four frames are indicated by white circles, pixels in the second frame are indicated by white triangles, and are indicated in the third frame.
Pixels in the frame are indicated by black circles, and pixels in the fourth frame are indicated by black triangles. A shown on the left side of FIG. 15 is 4
In the frame mode, pixels are collected from four frames to form blocks, as in the operation of the four-frame synthesis block circuit 32 in the seventh embodiment shown in FIG. Further, B shown on the right side of FIG. 15 is a 2-frame mode, and like the operation of the 2-frame synthesis block forming circuit 24 in the fourth embodiment shown in FIG. Pixels are collected from inside to be blocked. The data compression processing in the image coding circuit 25 is subsequently performed on the blocks which are divided into blocks as shown by the thick lines. The operation of the image coding circuit 25 is the same as that of the first embodiment shown in FIG.

The blocking mode determination circuit 36 analyzes the offset-sampled HDTV signal to determine the blocking mode. Normally, the 4-frame mode is used, but in the case of a scene change or extremely intense movement, the 2-frame mode is used. This is because in a special case such as the latter, when the block is formed in the 4-frame mode, the correlation between pixels in the block becomes lower than that in the 2-frame mode, and the data compression rate is lowered.

In this embodiment, since the processing modes of frame synthesis block formation are adaptively switched according to the nature of the image, it is possible to compare with the fourth embodiment in a special scene such as scene change or intense movement. The data compression rate can be increased.

In the eighth and ninth embodiments described above, there are two types of blocking modes of the multi-frame synthesis blocking circuits 33 and 35, but more blocking modes may exist. A blocking mode in which pixels are collected from the number of frames other than 2 frames and 4 frames to form blocks is also conceivable.

The embodiments of the present invention have been described in detail above. Various processing methods other than those described in the embodiments are conceivable as a processing method for frame synthesis block formation in which pixels are collected from a plurality of frames to form a block. Further, the present invention can be similarly applied to the case of processing in units of fields instead of processing in units of frames.

Blocks are distributed to a plurality of channels,
When the data is individually compressed by the image coding circuit, the compressed data may be unbalancedly distributed to each channel. Further, the allocation of the information amount to each channel can be unbalanced, and the allocation state may be adaptively changed according to the property of the signal. Further, there may be a data multiplexing circuit in which compressed data of each output is multiplexed, and after the data multiplexing circuit,
There may be a data redistribution circuit that redistributes the compressed data into multiple channels. The processing method of offset sampling may be different from the inter-field offset sampling method described above. Further, it is effective to provide a prefilter to prevent aliasing of high frequency components during offset sampling.

The present invention can be similarly applied even if the DCT is not used as the image encoding processing method for the output signal of the frame synthesizing block forming circuit which collects pixels from a plurality of frames to form a block. . It goes without saying that the present invention can be applied to various cases such as a color signal including a luminance signal and two kinds of color difference signals as the video signal. In that case, the color difference signal may be sub-sampled with respect to the luminance signal. The image coding apparatus according to the present invention can be applied not only to recording / reproducing on a magnetic tape in a digital VTR, but also to recording / reproducing on an optical disk or transmission via a data communication line.

[0059]

According to the present invention, the HDTV signal is subjected to the frame synthesis block forming process for collecting pixels from a plurality of frames to form a two-dimensional block, and then the data compression is performed by the image encoding circuit. As a result, the correlation between pixels in a block becomes high, so that it is possible to inexpensively realize an image encoding device having a higher data compression rate than the conventional method.

Further, after the above-described frame composition block forming processing is performed on the HDTV signal, the image data of the blocked HDTV signal is divided into a plurality of channels and individually compressed by the image encoding circuit. A specific one of the image coding circuits performs the data compression by switching one channel of the image data of the HDTV signal or the image data of the current TV signal according to the operation mode and compressing the data. A high-quality image encoding device compatible with both TV signals can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of an image coding apparatus that is a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an operation of a 2-frame synthesizing block forming circuit in the image encoding device shown in FIG.

FIG. 3 is a block diagram of an image coding apparatus that is a second embodiment of the present invention.

FIG. 4 is a block diagram of an image coding apparatus that is a third embodiment of the present invention.

FIG. 5 is a block diagram of an image coding apparatus that is a fourth embodiment of the present invention.

6 is a conceptual diagram showing an operation of an offset sampling circuit in the image coding apparatus of FIG.

7 is a conceptual diagram showing an operation of a 2-frame synthesis block forming circuit in the image encoding device of FIG.

FIG. 8 is a block diagram of an image coding apparatus that is a fifth embodiment of the present invention.

FIG. 9 is a block diagram of an image coding apparatus which is a sixth embodiment of the present invention.

FIG. 10 is a block diagram of an image encoding device that is a seventh embodiment of the present invention.

11 is a conceptual diagram showing an operation of a 4-frame synthesis block forming circuit in the image encoding apparatus of FIG.

FIG. 12 is a block diagram of an image coding apparatus which is an eighth embodiment of the present invention.

13 is a conceptual diagram showing an operation of a multi-frame synthesis block forming circuit in the image encoding device of FIG.

FIG. 14 is a block diagram of an image encoding device that is a ninth embodiment of the present invention.

15 is a conceptual diagram showing an operation of a multi-frame synthesis block forming circuit in the image encoding device of FIG.

[Explanation of symbols]

2.24 ... 2 frame synthesizing block circuit, 32 ... 4 frame synthesizing block circuit, 33. 35 ... Multi-frame synthesizing block circuit, 19.26 ... Block distribution circuit, 23 ... Offset sampling circuit, 3.11-1
4/25/27/28 ... Image coding circuit, 34/36 ...
Blocking mode determination circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Ichige 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture

Claims (12)

[Claims] 1. An image coding apparatus for compressing video signal data, comprising a frame for forming a two-dimensional block by collecting a plurality of pixels from N frames (N is an integer of 2 or more) for the video signal. An image coding apparatus comprising: a composite block forming means; and an image encoding means for data-compressing a block signal generated by the frame composite block forming means. 2. The image coding apparatus according to claim 1, wherein the frame synthesizing block forming means cyclically extracts each line from the N frames to generate one screen, and then generates one screen. The image coding apparatus is characterized in that the screen is divided into blocks. 3. The image coding device according to claim 2, wherein the frame synthesis block forming means forms a block from two frames. 4. The image coding apparatus according to claim 1, further comprising blocking mode determination means for determining a block configuration method in the frame synthesis blocking means.
An image coding apparatus, wherein the frame synthesis block forming means switches a block forming method when collecting a plurality of pixels from N frames to form a block according to an output signal from the block forming mode determining means. 5. An image coding apparatus for compressing video signal data, wherein an offset for converting an input video signal into a lattice-like five-eye sampling structure to reduce the number of pixels by half. Sampling means, and a frame synthesis block forming means for collecting a plurality of pixels from N frames (N is an integer of 2 or more) of the output signal of the offset sampling means to form a block having a two-dimensional lattice-like pixel array, An image coding apparatus comprising image coding means for data-compressing the block signal generated by the frame synthesis block coding means. 6. The image coding apparatus according to claim 5, wherein the frame synthesizing / blocking means arranges two frames having a five-eye sampling structure in one of the five eyes. By generating the generated pixels into the vacant pixel positions of the other frame to generate one grid-shaped screen, the generated one screen is divided into blocks. Image encoding device. 7. The image coding apparatus according to claim 5, wherein the frame synthesizing block forming means is arranged in an odd-numbered five-eye pattern with respect to four frames having a five-eye sampling structure. 2 pixels having a grid-like sampling structure by inserting the pixels in the vacant pixel positions of an even frame, and extracting each line alternately from the 2 screens An image coding apparatus, characterized in that, after generating a screen, one generated screen is divided into blocks. 8. The image coding apparatus according to claim 5, further comprising blocking mode determination means for determining a block configuration method in the frame synthesis blocking means.
An image coding apparatus, wherein the frame synthesis block forming means switches a block forming method when collecting a plurality of pixels from N frames to form a block according to an output signal from the block forming mode determining means. 9. An image coding apparatus for compressing data of a plurality of types of video signals having different resolutions, wherein a plurality of pixels from N frames (N is an integer of 2 or more) for a first video signal having a high resolution. And a data synthesizing means for distributing the blocked signals generated by the frame synthesizing and blocking means to a plurality of channels, and an output of the data allocating means. A plurality of image coding means for data-compressing the blocked signal of each channel are provided, and further, before the specific one image coding means, the output of the data distribution means for the first video signal having a high resolution. The image coding apparatus is provided with a signal switching means for switching between the first channel and the second video signal having a low resolution. 10. The image coding apparatus according to claim 9, wherein the data distribution means distributes the blocked signal of the first video signal to four channels. 11. An image coding apparatus for compressing data of a plurality of types of video signals having different resolutions, the first having a high resolution.
Offset sampling means for reducing the number of pixels by half by converting from a lattice-like to a five-eye sampling structure for the image signal of, and a plurality of N frames (N is an integer of 2 or more) after offset sampling. Frame synthesizing block forming means that collects the pixels of 2 to form a block having a two-dimensional lattice-like pixel array, and data distributing means that distributes the block forming signal generated by the frame synthesizing block forming means to a plurality of channels. , A plurality of image coding means for data-compressing the blocked signal of each channel which is the output of the data distributing means, and further a first image having a high resolution in front of one specific image coding means. An image characterized by including signal switching means for switching between one channel of the output of the data distributing means for a signal and a second video signal having a low resolution. Goka apparatus. 12. The image coding apparatus according to claim 11, wherein the data distribution unit distributes the blocked signal of the first video signal into two channels.