JP3218744B2 - Digital image signal transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal transmitting apparatus using orthogonal transform, for example, cosine transform.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head, for example, is known. Because of the large amount of digital video signal information,
High-efficiency coding for compressing the transmission data amount is often adopted. Among various high efficiency codings, DC
The practical use of T (Discrete Cosine Transform) is in progress.

[0003] DCT converts an image of one frame into, for example, (8
.Times.8), and the block is subjected to cosine transform, which is a type of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to a variable length coding process such as a run length code and a Huffman code. At the time of transmission, in order to facilitate data processing on the reproduction side, a code signal which is an encoded output is inserted into a data area of a fixed-length sync block, and a synchronization signal, I signal
A frame forming a sync block to which the D signal is added is formed.

Since video signals are generally interlaced, it is necessary to convert input data into a block structure before DCT. That is, in the case of (8 × 8), the (4 × 8) area of the first field and the (4 × 8) area of the second field are combined to form an (8 × 8) block in the frame. Is formed.

If there is movement between fields, vertical edges in the block become jagged at line intervals, and D
When the CT conversion is performed, many high-frequency components in the vertical direction appear. As a result, compression efficiency is reduced. To avoid this, intra-field DCT is preferred for blocks with inter-field motion. Specifically, (8 × 8)
Are subjected to DCT transform separately as two (4 × 8) blocks for each original field. as a result,
Two sets of (4 × 8) coefficient data are generated.

[0006]

As a result of intra-field DCT, DC component data (for example, 9 bits) is generated in each block. Normally, the DC component is transmitted as it is without quantization and variable length coding. If the quantization and variable length coding of the coefficient data generated in the intra-frame DCT and the intra-field DCT are performed independently,
There is no particular problem. However, this leads to an increase in the size of the hardware.

[0007] It is preferable that quantization and variable length coding be performed uniformly between the intra-frame DCT and the intra-field DCT. In that case, one of the two DC components generated in the DCT in the field is treated in the same manner as the data for the AC component. However, the value of the DC component data is much larger than the AC component, and quantization results in a problem that quantization distortion increases. Of course, when buffering is performed to control the data amount for a predetermined period including the coefficient data of a plurality of blocks to be equal to or less than the target value, the original data amount increases due to the presence of DC component data, and coarse quantization is performed. Be forced to. As a result, the quality of the restored image deteriorates.

In order to unify quantization and variable-length coding between intra-frame DCT and intra-field DCT, there is another problem that the arrangement of coefficient data in blocks is different. The (8 × 8) coefficient data generated by the intra-frame DCT has a two-dimensional array in which high-frequency components are located diagonally from the DC component. DC in field
The coefficient data generated at T has a similar tendency in a (4 × 8) two-dimensional array. However, the (8 × 8) array obtained by combining the two (4 × 8) arrays has a different tendency of the frequency change from (8 × 8) of the intra-frame DCT.

[0009] Variable-length coding is performed by using (8)
The compression efficiency is optimized for the coefficient data of × 8). Therefore, there is a problem that the above-mentioned difference in the tendency leads to a decrease in the efficiency of the variable length coding. In addition, the differences in the above tendencies detract from the advantages of adaptive quantization when performing adaptive quantization, where the quantization step for higher frequency components is larger than that for lower frequency components.

Therefore, an object of the present invention is to provide a method for controlling the in-frame D
It is an object of the present invention to provide a digital image signal transmission apparatus which enables the processing of generated coefficient data to be performed in a unified manner when performing CT and in-field DCT selectively.

[0011]

According to the first aspect of the present invention, there is provided a digital image signal transmitting apparatus for encoding a digital image signal by orthogonal transformation and variable length code and transmitting an encoded output. To a predetermined block structure, a detecting means for detecting the stillness / movement of the blocked digital image signal, and a blocking means, which is responsive to the output of the detecting means. An intra-frame orthogonal transformation for an n × m block composed of pixels in a frame of a digital image signal, and an intra-field orthogonal transformation for an n / 2 × m block composed of pixels in a field of a digital image signal. Orthogonal transform means for selectively performing the orthogonal transform, and the orthogonal transform means for performing the first orthogonal transform when the intra-field orthogonal transform is performed. Means for generating a difference between data of a first DC component generated from a block of a field and data of a second DC component generated from a block of a second field temporally continuous with the first field; When the conversion is performed, n / 2 × m generated from the block of the first field and n / 2 generated from the block of the second field including a difference between the generated DC data.
/ X × m data and a means for generating n × m data, and an orthogonal transform means, so that the DCT
Outputs the AC data generated by zigzag scan
And the data for the AC generated by the DCT in the field.
And the difference data into the first field block and the second field block.
Output means for alternately performing zigzag scans from the output block, and one quantizing means for commonly quantizing the AC data from the output means or the AC and difference data of the combined data. , A digital image signal transmission apparatus comprising a quantization means and a variable length coding means.

Further, according to the invention of claim 2 , DC in the frame is provided.
Quantizing the AC data from the orthogonal transform means generated in T with a quantization pattern adapted to the position in the block ,
A quantization pattern that adapts the data of the AC and the difference data generated by the intra-field DCT to the position in the block of the first field, and the quantization pattern in the block of the second field.
The quantization is performed using a quantization pattern adapted to the position .

Further, the invention according to claim 3 is an orthogonal transformation means.
Exchange of exchange data or summarized data from
Flow and difference data are quantized by the same quantization control.
It becomes something.

[0014]

According to the orthogonal transformation in the field, two sets of coefficient data are generated. One of the DC components of each set is transmitted as it is, and the other is replaced with DC difference data. Due to the image correlation between the fields, the value of this difference data is extremely small in most cases. Even if this difference data is treated in the same way as the data for the AC, it is possible to prevent the quantization distortion from increasing.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a video data processing circuit provided on the recording side of a digital VTR. FIG.
In the figure, digitized video data is supplied to an input terminal indicated by 1. This video data is supplied to the blocking circuit 2. In the blocking circuit 2, the video data in the order of interlaced scanning is (8 × 8)
Is converted to data having a DCT block structure. That is, (8 × 8) blocks are formed by combining two (4 × 8) blocks at the same spatial position in the first and second fields that are temporally continuous. In the (8 × 8) block, pixel data on odd-numbered lines is included in the first field, and pixel data on even-numbered lines is included in the second field.

The output of the blocking circuit 2 is supplied to a shuffling circuit 3. In the shuffling circuit 3, errors are concentrated due to dropouts, scratches on the tape, head clogs, etc., so that deterioration of the image quality is not noticeable.
Within one frame, a plurality of macroblocks are used as a unit.
The process of making the spatial position different from the original one,
Shuffling is performed. In this example, the shuffling unit and the buffering unit are equal, and are set to 5 macroblocks. The output of the shuffling circuit 3 is supplied to a DCT (cosine transform) circuit 4 and a motion detection circuit 5.
The DCT circuit 4 generates (8 × 8) coefficient data (that is, coefficient data of DC component DC and AC component AC). As will be described later, the DCT circuit 4 includes a motion block included in an (8 × 8) block (4 × 8).
The block is switched to perform the intra-field DCT for the block 8).

A macroblock is a collection of a plurality of (8 × 8) coefficient data per DCT block. For example, in the case of video data of the component system (Y: U: V = 4: 1: 1) of the 525/60 system, as shown in FIG.
A total of six blocks of four Y blocks, one U block and one V block constitute one macro block. When the sampling frequency is 4 fsc (fsc: color subcarrier frequency), an image of one frame is (910 samples × 525 lines), and the effective data is (720 samples × 480 lines). In the case of the above-described component system, the total number of blocks in one frame is (720 × 6/4) × 480 ÷ (8 × 8) = 81.
00. Therefore, 8100 ÷ 6 = 135
0 is the number of macroblocks in one frame.

In the case of component system (Y: U: V = 4: 2: 0) video data of the 625/50 system, as shown in FIG. 2B, four video data at the same position in one frame are provided. A total of six blocks including the Y block, one U block, and one V block constitute one macro block.

The DC component DC of the (8 × 8) coefficient data generated by the DCT circuit 4 is transmitted to the subsequent circuit without being compressed, and 63 AC components thereof are quantized via the buffer 6 through the buffer 6. Is supplied to the conversion circuit 7. As shown in FIG. 3, the coefficient data of the AC component is transmitted in the zigzag scanning order from the AC component having the lower order to the component having the higher order. Also,
The coefficient data of this AC is used as the activity detection circuit 8
And the data amount estimator 9. Buffer 6
Is provided to delay the coefficient data for a time necessary for the estimator 9 to determine an appropriate quantization number QNo, and to output the respective coefficient data of the still block and the motion block in a predetermined order. ing. The quantization number QNo from the estimator 9 is supplied to the quantization circuit 7 and transmitted to the subsequent stage.

The generation of the coefficient data from the DCT circuit 4 is the case of the DCT transform in the frame.
When the motion detection circuit 5 detects that there is motion,
The processing of the DCT in the field is selected. That is,
The intra-field DCT performs DCT for every two (4 × 8) blocks at the same position in the first and second fields that are temporally continuous. If the motion detection circuit 5 detects that there is a motion between fields with respect to the block, the intra-frame DCT is changed to the intra-field DCT in response to this detection. The motion detection circuit 5 (8
The still / movement determination is performed for each block based on the coefficient data in the vertical direction when the image data of the × 8) block is subjected to Hadamard transform. Alternatively, the motion detection may be performed based on the absolute value of the field difference.

In the case of intra-field DCT, (4 × 8) coefficient data for the first field and (4 × 8) coefficient data for the second field are generated.
These are located at the top and bottom (8 ×
8) is handled as an array. The DC data DC1 is included in the coefficient data of the first field. The DC component DC2 is similarly included in the second field. When the coefficient data of each of these fields is handled separately,
Subsequent processing must be performed separately for the CT and the intra-field DCT. As a result, problems such as an increase in hardware scale occur. Therefore, in this embodiment, instead of the DC component DC2 of the second field, the difference DC component ΔDC2
(= DC1-DC2). The detection signal (motion flag) M from the motion detection circuit 5 is supplied to the data amount estimator 9 and transmitted to the subsequent stage. The processing when there is this movement will be described later in more detail.

The quantizing circuit 7 quantizes an AC component in the coefficient data. That is, the coefficient data for the AC is divided by an appropriate quantization step, and the quotient is converted to an integer.
This quantization step corresponds to the quantization number QN from the estimator 9.
o. In the case of a digital VTR,
Since processing such as editing is performed in units of one field or one frame, the amount of generated data per one field or one frame must be equal to or less than a target value. Since the amount of data generated by DCT and variable-length coding varies depending on the pattern to be coded, one field or one field is used.
A buffering process is performed to reduce the amount of data generated in a buffering unit shorter than the frame period to a target value or less. The reason for shortening the buffering unit is to simplify the buffering circuit, for example, by reducing the memory capacity for buffering. In this example, five macroblocks (= 30 DCT blocks) are set as buffering units.

As will be described later, the activity detecting circuit 8 examines the fineness of the picture in units of DCT blocks, classifies the activities of the DCT blocks into four stages, and outputs two bits indicating the classes. Generates an activity code AT. Detection result is estimator 9
, And the activity code AT is transmitted to the subsequent stage.

The output of the quantization circuit 7 is the variable length coding circuit 1
1 for run-length coding, Huffman coding and the like. For example, a two-dimensional Huffman coding that generates a variable-length code (encoded output) by giving a run length, which is a continuous number of coefficient data “0”, and a value of the coefficient data to a Huffman table stored in a ROM is adopted. Is done. The code signal from the variable length encoding circuit 11 is supplied to the subsequent stage.

In connection with the estimator 9, the same Huffman table 12 as that referred to in the variable length coding circuit 11 is provided. The Huffman table 12 generates bit number data of an output code when variable length coding is performed.
The estimator 9 determines an optimal set of quantization steps, and the determination output is supplied to the selector 10. Selector 10
Controls the quantization circuit 7 to quantize the coefficient data in this set of quantization steps. At the same time, a quantization number QNo for identifying a set of quantization steps is transmitted to the subsequent stage.

Although not shown, data (DC component data, variable-length coded output, quantization number QN
o, the motion flag M, and the activity code AT) are subjected to error correction coding processing and conversion processing of recording data into a frame structure in a framing circuit at the subsequent stage. From the framing circuit, data of a sync block configuration appears. The recording data is supplied to two rotating heads via a channel encoding circuit and a recording amplifier, and is recorded on a magnetic tape.

FIG. 5 shows a data array of one sync block in this embodiment. The length of one sync block is, for example, 90 bytes. The block synchronization signal SYNC (2 bytes) is located at the head of the sync block, and thereafter the ID signal is located. The ID signal includes a 2-byte ID signal (ID0, ID1) and a parity IDP (1 byte) for the ID signal. 77 bytes of the remaining 85 bytes are the data area, and the last 8 bytes
The byte is the parity of the inner code of the product code. At the head of the data area, a 1-byte quantization number QNo and an auxiliary code AUX for identifying a quantization step are located. The subsequent 75 bytes are data (variable length code or outer-coded parity).

One sync block includes a code signal and one DC signal for one macro block (YYYY, U, V).
The activity code AT and the motion flag M for the T block are inserted. The motion flag M is DCT
This is a 1-bit flag indicating the presence or absence of a motion detected for each block.

The 75-byte area is divided into four areas each having a length of d (for example, 18 bytes) and a fractional head area. For each d, a DC component (9 bits) generated in four DCT blocks of one macroblock is arranged, and thereafter, a motion flag M and an activity code AT are arranged. Each area of length d is divided into areas of a (for example, 12 bytes) and d / 2 (6 bytes). As a result, eight areas are formed.

The first area is a fixed AC-H area. The next area of length a including the DC component is Y AC-
L-area and a / 2-length area is fixed AC-H
Area. In the next area of length d, the AC of Y
-L area and an area for a DC component of C (for example, U), a motion flag M, an activity code AT, and an AC-L. Furthermore, the area of the next d length is Y
And the fixed AC-H area, and the last d-length area is the Y-AC-L area, C (for example, V) DC component, motion flag M, activity code AT, AC -L. The AC-H components protruding from each AC-L area are packed in order from the first AC-H area. If a free area, that is, a variable AC area exists in the AC-L area, the protruding AC-H component is also packed here.

The ID signal includes a frame ID, a format identification bit, two bits indicating the type of recording data, a sync block address, and a parity byte IDP. The frame ID is inverted for each frame. The identification bits identify the format for the digital VTR of this embodiment and other formats, for example, the format of the data storage device. When this is "1", the digital VT
This means a format for R, and when this is "0", it means another format. The recording data identification bit is
Indicates the type of recording data (video, audio, etc.). Furthermore, the sync block address is an address that is serially numbered for all sync blocks that include one frame of data and are divided and recorded on a plurality of tracks.

Further, the auxiliary code AU in the data area
X is also a kind of ID signal and has information such as a broadcast format of a video signal and an audio mode. The reason why the quantization number QNo and the auxiliary code AUX are recorded in the data area is that the error correction code relating to the data in the data area has a higher correction capability than the error correction code of the ID signal.

In the quantization circuit 7, as described above, the coefficient data is divided by the quantization step, and the quotient is rounded to an integer. Assuming that the absolute value of the coefficient data is C and the value of the quantization step is D, the value Q (C) after rounding is represented by the following equation. Q (C) = INT [{C + (D / 2)} / D] FIG. 6A shows the processing when the quantization step is 16.

This rounding process is a general one, and mathematically, the quantization distortion can be minimized as a whole. However, considering the visual effect, the above-described rounding process may not always be the best. In this embodiment, at the time of quantization, high-frequency coefficient data is coarsely quantized. Normally, since the high-frequency component has a small value, all the values of the high-frequency component become 0 after quantization by the above-described rounding. This increases the efficiency of the subsequent variable length coding.

However, depending on the picture, a large high-frequency coefficient may appear. For example, a coefficient value of 8 corresponds to FIG.
As can be seen from FIG. This is equivalent to amplifying the high frequency coefficient, becomes visually noise, and degrades the image quality. To improve this problem, a rounding process as shown in FIG. 6B is preferable.

This processing is performed when the area number to be described later is <4, that is, for the low-frequency coefficient, the same rounding of Q (C) = INT [{C + (D / 2)} / D] as described above. I do. If the area number is a high frequency coefficient of ≧ 4, the following processing is performed. If D <8, Q (C)) = INT [{C + (D / 2)} / D] In the other cases (D ≧ 8) (FIG. 6B is an example) Q (C)) = INT [｛C + INT (D / 3)｝ / D]

As described above, when the value of the quantization step is smaller than 8, normal rounding is performed, and when the value is 8 or more, irregular rounding is performed. This makes it possible to reduce visual noise while maintaining the SN ratio.

In the quantization circuit 7, activity detection is performed to perform optimal quantization. FIG. 7 shows an example of the activity detection circuit 8. Input terminal 21
, Coefficient data for the AC is sequentially supplied. This input data is supplied to the scan circuit 22 and the absolute value conversion circuit 24. The scan circuit 22 selectively outputs to the absolute value conversion circuit 23 the 25 coefficient data on the high frequency side as shown as a dot area in FIG. 8A. As shown in FIG. 8B, all coefficient data other than the DC component is supplied to the absolute value conversion circuit 24.

The coefficient data converted into absolute values by the absolute value conversion circuits 23 and 24 are supplied to comparison circuits 25 and 26, respectively. The threshold values TH1 and TH2 are supplied to the comparison circuits 25 and 26, respectively. When the coefficient data is equal to or greater than TH1, the comparison output generated from the comparison circuit 25
The counter 27 is enabled. When the coefficient data is equal to or larger than the threshold value TH2, the comparison output generated from the comparison circuit 26 is latched by the flip-flop 28. As an example, TH1 = 4 and TH2 = 235. Counter 2
7 and the flip-flop 28 are cleared for each DCT block.

The count value NH of the counter 27 is supplied to comparison circuits 29, 30, and 31. The comparison circuits 29, 30,
31 are supplied with threshold values TH3, TH4, and TH5, respectively. As an example, TH3 = 1, TH4 = 5, T
H5 = 10. Comparison circuits 29, 30, 31
Generates a comparison output that goes high when the count value NH is equal to or greater than the corresponding threshold value. The outputs of the comparison circuits 29 and 30 are supplied to the logic 33, and the comparison circuit 31
Is supplied to the OR gate 32.

As the other input of the OR gate 32, the comparison output NF from the flip-flop 28 is supplied. O
The output of the R gate 32 is supplied to the logic 33. The logic 33 generates an activity code AT indicating the activity class of the DCT block at the output terminal 34 from the input signal.

In this example, activities are classified as shown in FIG. That is, NH = 0, class 0 (AT = 00) NH ≧ 1, class 1 (AT = 01) NH ≧ 5, class 2 (AT = 10) NH ≧ 10, or NF = 1, class 3 (AT = 11) )

Class 0 has the lowest activity,
Activities are high in order of 1, 2, and 3. By NF = 1, large coefficient data of TH2 or more is coarsely quantized (class 3 is applied). This is done in order to suppress the value of the coefficient data within the range of values specified in the Huffman table for variable length coding.

The activity detection is to detect the fineness of the picture of each DCT block. Visually, the fine pattern (high activity) block,
Even if the quantization step is coarse, distortion is not conspicuous. on the other hand,
When a flat picture (low activity) block is coarsely quantized, distortion is easily noticeable. Therefore, in a buffering unit (30 DCT block) in which the total number of bits is controlled to be equal to or less than a predetermined value, the quantization for a high activity block is coarse, and the quantization for a low activity block is fine. Is effective.

Although it has been described that distortion is not conspicuous even when a block having a high activity is coarsely quantized, this does not hold when the block includes edge information. Rather, fine quantization is preferable for edge information. It is preferable to determine that only a block that includes a fine pattern as a whole has high activity. In consideration of this point, the coefficient data used for activity detection is limited to high-frequency data in a pattern as shown in FIG. 8A.

That is, as shown in FIG. 10A, when a block including a vertical edge is subjected to DCT conversion, coefficient data is generated only in the first row. Therefore, the coefficient data in the first row is excluded from the targets of activity detection. In addition, as shown in FIG. 10B, in a block including a horizontal edge, coefficient data is generated only in the first column. Therefore, the coefficient data in the first column is excluded from the targets of activity detection. Also, when there is some movement in the image including the vertical edge and the intra-frame DCT is performed, as shown in FIG. 10C, the high frequency component in the vertical direction increases, and the value of the coefficient data in the lower left corner increases. Become. This part is excluded to reduce the effect of this movement. As a result, the detection target range shown in FIG. 8A is set. It should be noted that the motion flag M is supplied to the logic 33, and the motion block detected by the motion detection circuit 5 is uniquely classified as class 0.

The data amount estimator 9 is capable of reducing the amount of data generated in the buffering unit (5 macroblocks) to a target value or less, and determines a quantization step having a value as small as possible. The estimator 9 performs quantization according to the activity class, further divides an area in the block into, for example, eight, and performs quantization according to each area. FIG. 11 shows an example of the estimator 9. Prior to the description of FIG. 11, quantization in consideration of activity and area will be described.

FIG. 12 shows an example of area division of coefficient data for a still block. Each number from 0 to 7 assigned to each coefficient data represents an area number. The area number is defined such that the coefficient data becomes higher as the area number increases. The area division is based on the point that, when quantizing the coefficient data, the higher the band of the coefficient data, the less the quality of the restored image deteriorates even if the quantization is coarser. As can be seen from FIGS. 3 and 12, the area numbers change in ascending order according to the scanning (output) order of the coefficient data.

FIG. 13 shows a quantization table of this example. In FIG. 13, SQ is an approximate value of the square root of 2 (= 1 + 1/4)
+1/8 +1/32). Here, a set of 16 types of quantization steps identified by quantization numbers QNo of 0 to 15 is prepared. Each set consists of quantization steps corresponding to each of the areas 0-7. For example, quantization number QNo = 0
Are set as (1,1,1, SQ, 2,2
* SQ, 4, 4 * SQ). The quantization table shown in FIG. 13 has a change in which the quantization step increases as the quantization number QNo increases. In other words, when the quantization number QNo increases, the quantization changes to a coarse one. Since all the quantization steps are represented by powers of two, a simple circuit can be used as a circuit for dividing the coefficient data in these quantization steps.

FIG. 14 illustrates the quantization in consideration of the activity and the quantization in consideration of the difference between the luminance data and the color data. Each DCT block is classified into any one of the activity classes 0, 1, 2, and 3 by the above-described classification of the activity detection circuit 8. When one quantization number is set to q, the quantization number is adjusted according to the activity class. For classes 2 and 3 with higher activities, the quantization numbers are changed to q + 1, q + 2, and for class 0 with lower activities, the quantization numbers are q−1
Is changed to As a result, the quantization step can be controlled according to the level of the activity. In this adjustment, if the quantization number becomes negative or becomes 16 or more, the quantization number is clipped to 0 or 15.

In general, since the deterioration of the resolution of a color signal is less conspicuous than that of a luminance signal, the process of lowering the frequency characteristics of the color signal and redirecting the resulting margin to the luminance signal is an area shift. It is. The area shift cannot be used for the luminance (Y) signal (N / A in FIG. 14).
). For the color signals (U, V), an area shift is performed in accordance with the activity class. The number of the area shift in FIG. 14 is a value added to the original area number. Addition results exceeding 7 are clipped to 7.

[0052] In estimator 9 shown in FIG. 11, 40 ₁
４０40 _n are quantization circuits each having the quantization table shown in FIG. n corresponds to the number of sets of quantization steps in the quantization table (n = 16 in this example). These quantization circuit 40 ₁ to 40 _n is the controller 41, the quantization operation is controlled respectively.
The activity code AT and the motion flag M from the activity detection circuit 8 are supplied to the controller 41. Output data of the quantizing circuit 40 ₁ to 40 _n is supplied to the scan circuit 42 ₁ through 42 _n. The scan circuit controls the output order of the coefficient data of the motion block to a predetermined order, as described later, by switching the output order of the quantization circuit in response to the motion flag M.

[0053] The output of the scan circuit 42 ₁ through 42 _n are supplied to the variable length coding circuit 43 ₁ ~ 43 _n. The variable length encoding circuit performs, for example, two-dimensional Huffman encoding with reference to the Huffman table 12. This Huffman table 12
Is a table which is the same as that used in the variable length coding circuit 11 for the main signal, but in which the number of output bits is known to obtain only the data amount. Encoded output of the variable length coding circuit is supplied to the buffer 44 ₁ ~ 44 _n.
These buffers are reset every 5 macroblocks and accumulate the amount of data for 5 macroblocks.

The accumulated data obtained in the buffer is supplied to the decision circuit 45, and a quantization circuit in which the amount of data generated in five macro blocks is equal to or smaller than a predetermined value is determined. The determination output generated at the output terminal 46 is supplied to the selector 10 (see FIG. 1), and the selector 10 specifies a set of quantization steps of the quantization circuit 7. At the same time, the quantization number Q
No is output. The estimator 9 is not limited to the configuration shown in FIG. 11, but may employ various configurations such as a method of sequentially performing quantization in different quantization steps.

To the quantizers 40 ₁ to 40 _n of the estimator 9, the coefficient data via the switch circuit 47 is supplied. To the input terminal a of the switch circuit 47, coefficient data for AC is supplied, and to the other input terminal b, output data of the subtraction circuit 48 is supplied. Switch circuit 47
Is controlled by a control signal CT. The DC component DC2 of the current field is supplied to the subtraction circuit 48, and the DC component DC1 of the previous field from the delay circuit 49 is subtracted. The subtraction circuit 48 generates difference DC data ΔDC2. When the intra-field DCT is performed for the motion block, the switch circuit 47 selects the difference DC data ΔDC2 instead of the DC component DC2 of the second field (see FIG. 4).

One purpose of forming the differential DC data in the in-field DCT is to reduce the value to prevent the coefficient data from being coarsely quantized. Another object is to reduce the effect of quantization distortion by reducing the value. Except for the case where a scene change occurs between fields, there is a field correlation, so in most cases, the value of the differential DC data ΔDC2 is 0
These values are extremely small, and can achieve these objects.

The quantization circuits 40 ₁ to 40 _n take charge of quantization for each set of quantization steps. Controller 4
1 is shown in FIG. 14, to perform the above-described adaptive quantization, and controls the quantization circuit 40 ₁ to 40 _n. The controller 41 receives the activity code AT (2 bits) and adjusts the quantization number QNo. Since the order of the coefficient data is known, the area is defined according to the position of the coefficient data in one block in the time series. In the case of a motion block, since the intra-field DCT is performed, the distribution of coefficient data in the (8 × 8) block is different from the intra-frame DCT. Therefore, the area definition is different from the intra-frame DCT shown in FIG.
Change to the one shown in FIG. When the controller 41 receives the motion flag M, the area definition shown in FIG. 15 can be performed. In this area definition, a small area number is assigned to the low-frequency coefficient data, as in the case of the still block, and the area definition is the same between the two fields. Further, since the luminance signal and the color signal are known at positions in the time series, it is possible to control the area shift for the color signal.

The scan circuits 42 _{1 to} 42 _n sequentially output coefficient data by zigzag scanning shown in FIG. 3 in the case of intra-frame DCT. If this output order is applied to the coefficient data of the motion block, the length of the 0-run (run length) becomes shorter, and the efficiency of the subsequent variable-length coding is reduced. Therefore, in the case of a motion block, FIG.
The scan circuit outputs the coefficient data in the order of the numbers shown in FIG.

The coefficient data of the motion block output in the order shown in FIG. 16 is different from the still block in that the area numbers with respect to the output order are not completely regular. For example, focusing on the area numbers from the first coefficient data to the sixth coefficient data, (DC, 0, 0, 1, 0, 1) is obtained. Therefore,
The controller 41 changes the quantization control according to the area between the still block and the motion block according to the motion flag M.

FIG. 17 shows another example of the area definition of the motion block. In this example, the area definition between the two fields is not the same. However, by outputting the coefficient data of FIG. 17 in the order shown by the numbers in FIG. 18, the area numbers change regularly in the output order. For example, focusing on the first to eighth elements, (DC, 0, 0, 0, 0, 0, 1,.
1). Therefore, the quantization control in the data amount estimator 9 and the quantization circuit 7 for the main signal can be the same between the still block and the motion block. The output order of the main line signal is controlled by the buffer 6 in FIG.

Further, unlike this embodiment, the DCT circuit 4
An interlacing circuit may be provided at the subsequent stage, and a process of converting the coefficient data obtained by the intra-field DCT into the same order as in the interlaced scanning may be performed. By this method, the subsequent processing can be performed without distinguishing between a still block and a moving block, and the control and circuit can be simplified.

The above embodiment is an example of a digital VTR for recording a digital video signal on a magnetic tape. However, the present invention can be applied to a case where a medium such as a disk other than a tape is used.

[0063]

According to the present invention, in-field DCT
Is converted into differential data. Therefore, it is possible to prevent an increase in quantization distortion and an undesirable increase in the number of quantization steps when performing buffering. Further, since the present invention changes the output order of data generated in the intra-field DCT and the definition of the area number, the quantization and variable-length coding after the DCT are performed in the same manner as the intra-frame DCT data. It can be carried out.

[Brief description of the drawings]

FIG. 1 is a block diagram of a recording data processing circuit of a digital VTR to which the present invention is applied.

FIG. 2 is a schematic diagram used for describing a macroblock.

FIG. 3 is a schematic diagram illustrating an example of an output order of DCT coefficient data.

FIG. 4 is a schematic diagram showing processing of DCT in a field.

FIG. 5 is a schematic diagram illustrating a configuration of a sync block of print data.

FIG. 6 is a schematic diagram for explaining a rounding process in quantization.

FIG. 7 is a block diagram illustrating an example of an activity detection circuit;

FIG. 8 is a schematic diagram illustrating an activity detection area.

FIG. 9 is a schematic diagram for explaining activity detection.

FIG. 10 is a schematic diagram for explaining coefficients generated in DCT.

FIG. 11 is a block diagram illustrating an example of an estimator.

FIG. 12 is a schematic diagram illustrating an example of area definition.

FIG. 13 is a schematic diagram illustrating an example of a quantization table.

FIG. 14 is a schematic diagram for explaining adaptive quantization.

FIG. 15 is a schematic diagram illustrating an example of area definition of a motion block.

FIG. 16 is a schematic diagram illustrating an example of an output order of coefficient data of a motion block.

FIG. 17 is a schematic diagram for explaining another example of the area definition of the motion block.

FIG. 18 is a schematic diagram for explaining another example of the output order of coefficient data of a motion block.

[Explanation of symbols]

 Reference Signs List 4 DCT circuit 5 Motion detection circuit 7 Quantization circuit 8 Activity detection circuit 9 Estimator

Continuation of the front page (56) References JP-A-4-108270 (JP, A) JP-A-63-234788 (JP, A) JP-A-3-1688 (JP, A) JP-A-1-251197 (JP, A) U.S. Pat. No. 5,091,782 (US, A) Hiroshi Yasuda, "International Standard for Multimedia Coding" (Hira 3-6-30) 18-24 (General description of JPEG encoding) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^7/ 24-7/68

Claims (3)

(57) [Claims] 1. A digital image signal transmitting apparatus which encodes a digital image signal by orthogonal transformation and variable length code and transmits the encoded output, wherein the digital image signal is converted into a predetermined block structure. Means for blocking the digital image signal,
Detecting means for detecting motion; and an intra-frame orthogonal for an n × m block composed of pixels in a frame of the digital image signal, responsive to an output of the detecting means, coupled to the blocking means. Orthogonal transform means for selectively performing a transform and an intra-field orthogonal transform for an n / 2 × m block composed of pixels in a field of the digital image signal; and When the intra-field orthogonal transformation is performed, data of the first DC component generated from the block of the first field and data of the second DC component generated from the block of the second field temporally continuous with the first field. And n / 2 × m data generated from the block of the first field when the intra-field orthogonal transformation is performed. Means for generating n × m data by combining n / 2 × m data generated from the block of the second field including the generated DC component data difference, and the orthogonal transform means Occurs in DCT in frame
The data of the exchanged data is output by zigzag scan, and
The data for the above AC generated by DCT in the field and
And the difference data described above is stored in the first field block and the second field block.
Output means for alternately performing zigzag scans from the block of the field and outputting the data; and for commonly quantizing the AC data from the output means or the AC data of the combined data and the difference data. A digital image signal transmission device, comprising: one of quantization means; and a variable-length encoding means coupled to the quantization means. 2. A digital image signal transmitting apparatus which encodes a digital image signal by orthogonal transformation and variable length code, and transmits the encoded output, wherein the digital image signal is converted into a predetermined block structure. Means for blocking the digital image signal,
Detecting means for detecting motion; and an intra-frame orthogonal for an n × m block composed of pixels in a frame of the digital image signal, responsive to an output of the detecting means, coupled to the blocking means. Orthogonal transform means for selectively performing a transform and an intra-field orthogonal transform for an n / 2 × m block composed of pixels in a field of the digital image signal; and When the intra-field orthogonal transformation is performed, data of the first DC component generated from the block of the first field and data of the second DC component generated from the block of the second field temporally continuous with the first field. And n / 2 × m data generated from the block of the first field when the intra-field orthogonal transformation is performed. Means for generating n × m data by combining n / 2 × m data generated from the block of the second field including the generated DC component data difference, and n × m data generated by the intra-frame DCT. The quantum of the AC data from the orthogonal transform means
The data of the alternating current and the data of the difference generated by the in-field DCT are quantized by the
Quantization pattern adapted to the position of the field in the block
And the amount adapted to the position in the block of the second field
An apparatus for transmitting a digital image signal, comprising: one quantizing means for quantizing with a quantization pattern; and a variable-length coding means coupled to the quantizing means. 3. A digital image signal transmitting apparatus which encodes a digital image signal by orthogonal transform and variable length code, and transmits the encoded output, wherein the digital image signal is converted into a predetermined block structure. Means for blocking the digital image signal,
Detecting means for detecting motion; and an intra-frame orthogonal for an n × m block composed of pixels in a frame of the digital image signal, responsive to an output of the detecting means, coupled to the blocking means. Orthogonal transform means for selectively performing transform, and intra-field orthogonal transform for an n / 2 × m block constituted by pixels of each field constituting the nxm block; When the intra-field orthogonal transformation is performed, the first DC component data generated from the first field block and the second DC data generated from the second field block temporally continuous with the first field are combined. Means for generating a difference from DC data; and n / 2 × m generated from the block of the first field when the intra-field orthogonal transformation is performed. Means for generating n × m data by combining the data and n / 2 × m data generated from the block of the second field including the difference between the generated DC components; and the orthogonal transformation means. Generated by DCT in the frame
The data of the exchanged data is output by zigzag scan, and
The data for the above AC generated by DCT in the field and
And the difference data described above is stored in the first field block and the second field block.
Output means for alternately performing zigzag scanning from the block of the field, and the same quantization control for the AC data from the orthogonal transformation means or the AC data of the combined data and the difference data. A digital image signal transmitting apparatus, comprising: a quantizing means for quantizing by a variable length coding means coupled to the quantizing means.