JPH0686223A - Still video reproducing device - Google Patents

Abstract

PURPOSE:To eliminate the influence of the discontinuous part of a signal by comprising a reproducing device of a video signal reading means, a means to store a read video signal, a means to generate a pulse signal to write a video signal based on a horizontal synchronizing signal included in the video signal, and a means to control the generation of the pulse signal. CONSTITUTION:The video signal recorded on a magnetic disk 10 is read by a magnetic head 12, and it is amplified by a head amplifier 20, and is inputted to an AGC amplifier 21, and is supplied to a demodulation circuit 22, and a frequency-modulated reproducing signal is demodulated to an ordinary base band signal. A luminance signal including a synchronizing signal demodulated at the circuit 22 is inputted to an A/D converter 26 and a synchronizing separator circuit 24, and the synchronizing signal is taken out at the circuit 24, and a write pulse is generated from a write sampling pulse generation circuit 30 based on the signal. Simultaneously, the synchronizing signal is sent to a (mu) computer 100, and the A/D converters 25, 26 are controlled based on the write pulse, and a color difference line sequential signal and the luminance signal including the synchronizing signal are converted to digital signals, respectively, and they are written on memory 27, 28, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still video reproducing device, and more particularly to a still video reproducing device for reading and reproducing a still image signal recorded on a recording medium such as a magnetic disk.

[0002]

2. Description of the Related Art Conventionally, there is known a device for reproducing a still image signal recorded on a recording medium and displaying it on a display. Generally, a magnetic disk is used as the recording medium. As shown in FIG. 2, the magnetic disk has a plurality of tracks, and a video signal for one field is recorded on each track. According to the NTSC standard,
The display screen is composed of 525 scanning lines and adopts the interlace system. That is, an image for one field is composed of 262.5 scanning lines. Therefore, a video signal for 262.5H is recorded on one track of the magnetic disk. In other words, the video signal corresponds to one field, the vertical synchronization signal is once, and the horizontal synchronization signal is 262.5.
It will be included once. The output to the display is
It is performed based on the synchronization signal included in the recorded signal.

The horizontal synchronizing signal appears every 1H, but the horizontal synchronizing signal does not appear at the last 0.5H of the video signal for one field. Therefore, when the video signal recorded on the magnetic disk is reproduced. In addition, there is a problem that a signal discontinuity occurs in each field, and a skew distortion occurs in a reproduced image.

[0004]

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to perform image reproduction capable of reproducing a still image signal recorded on a recording medium without being affected by a discontinuous portion of the signal. To provide a device.

[0005]

Therefore, in the present invention, a reading means for reading a video signal recorded on a recording medium, a storage means for storing the read video signal, and a reading means for storing the read video signal are included. Signal generator for generating a pulse signal for writing a video signal in the storage means on the basis of the horizontal synchronization signal, and the signal generator ignores the horizontal synchronization signal in the vicinity of the point where the phase of the horizontal synchronization signal changes. It is characterized by having a control means for controlling so as to generate a pulse signal.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a still video reproducing apparatus 1 which is an embodiment of the present invention. In this embodiment, a 2-inch magnetic disk 10 is used as the recording medium. The magnetic disk 10 generally has the specifications shown in FIG. In FIG. 2, DSP (data starting position) indicates the first position to write data. The writing start of the vertical synchronization signal (V-SYNC) appears at the rear of θ with respect to the rotation direction of the disk 10. In one track of disk 10,
A video signal for one field is recorded. here,
As for θ, an error is recognized in the range of θ = 7 ± 2H.

The PG coil 11 detects the DSP and outputs a signal. Based on the detection signal of the PG coil 11, the spindle motor 14 is rotationally driven by the servo circuit 15 at a predetermined speed.

The video signal recorded on the magnetic disk 10 is read by the head 12. Also, the head 12
Are moved in the radial direction (tracking direction) of the disk 10 by the tracking motor 13.

The signal read by the head 12 is amplified by the head amplifier 20. The output of the head amplifier 20 is further input to an AGC (automatic gain adjustment) amplifier 21, amplified to a predetermined level, and then input to a demodulation circuit 22. The demodulation circuit 22 demodulates the FM-modulated reproduction signal into an ordinary baseband signal.

The demodulation circuit 22 demodulates and outputs Y + S (luminance signal including a synchronizing signal) and LSC (color difference line sequential) signal in which RY and BY alternate alternately every 1H. Since the Y + S signal and the LSC signal have different demodulation circuits, there is a time difference between the demodulated Y + S signal and the LSC signal (the LSC signal is delayed). Therefore, the Y + S signal passes through the delay line (delay element) 23 to eliminate the time difference.

The Y + S signal demodulated by the demodulation circuit 22 is
It is put in the A / D converter 26 and the sync separation circuit 24. In the sync separation circuit 24, the sync signal (V-SYNC,
H-SYNC) is taken out, and based on this, the write sampling pulse generating circuit 30 generates a write sampling pulse. At the same time, the synchronization signal is also sent to the microcomputer 100. Based on the write sampling pulse generated by the write sampling pulse generation circuit 30, the A / D converters 25, 26
Are controlled to convert the LSC signal and the Y + S signal from analog signals into digital signals. The LSC signal and Y + S signal converted into digital signals are respectively LSC
Is written in the memory 27 for Y and the memory 28 for Y + S. The address at the time of memory writing is generated by the write address generation circuit 31 based on the output of the write sampling pulse generation circuit 30. After the data is written in the memories 27 and 28, the output signal to the display is performed by reading the data in the memories 27 and 28, so that the drive system of the disk 10 and the demodulation / amplification of the reproduction signal are stopped. May be.

Control of signal writing to the memories 27 and 28 is executed by a write enable signal from the microcomputer 100. The readout of the video signal recorded in the memories 27 and 28 is performed by the microcomputer 1
Controlled by the read enable signal from 00. After a stable synchronizing signal is generated by the reference synchronizing signal generating circuit 42, the reading sampling pulse generating circuit 41 generates a reading sampling pulse based on this,
In synchronization with this, the read address generating circuit 40 generates an address signal, and the recorded video signal is read from the memories 27 and 28. The reproduction processing circuit 50 produces RY, BY, and Y + S signals in the form of digital signals, which are converted into analog signals by the D / A converters 60, 61, and 62, and an NTSC composite signal by the encoder 63. Is generated and output.

As described above, in the reproducing apparatus of this embodiment, the read video signal is once written in the memory. In the case of the conventional still video reproducing apparatus, although the still image is reproduced, the motor must be rotated (that is, the disk should be rotated) to repeatedly read the same data. In this case, by repeatedly reproducing the same track, there are problems such as power consumption by the motor and head / disk consumption. Also, because there is fluctuation (jitter) in the rotation of the spindle motor,
There was also a problem that the still image appears to shake. In the present case, once the video signal is read and stored in the memory, the rotation of the spindle motor is stopped, and the signal output to the display uses the data in the memory. As a result, the above problems can be avoided.

FIG. 3 is a block diagram showing the configuration of the write sampling pulse generating circuit 30. A conventional sampling pulse generating circuit is simply an H-SYN with a known PLL circuit configuration including a phase comparator, an LPF (low pass filter), a VCO (voltage controlled oscillator) and a frequency divider.
The sampling pulse was obtained by the frequency-divided output of C and VCO. However, as described above, since the H-SYNC has a discontinuity of 0.5H, in the conventional method,
There is a problem that the phase of H-SYNC is shifted and the control voltage of VCO is disturbed.

The write sampling pulse generating circuit 30 of FIG. 3 has a phase comparator 30 similar to a normal PLL circuit.
3, LPF 304, VCO 305, and frequency divider 306, but further includes a control pulse generator 307 and a switch 3.
01 and 302 are provided. V-SYNC and H-SYNC are input to the control pulse generator 307. Based on this, the control pulse generator 307 generates a plurality of different pulse signals. The pulse signal output from the control pulse generator 307 controls the input signal to the phase comparator 303.

Next, the input signal control to the phase comparator 303 will be described with reference to the timing chart of FIG. In FIG. 4, C-SYNC is a sync separation circuit 2
4, V-S, first separated from the Y + S signal
It is a composite sync signal including YNC and H-SYNC.

As described above, the H.SYNC 0.
Since there is a shift of 5H, synchronization cannot be achieved. Therefore, in the present invention, the sampling pulse is not generated from H-SYNC in the vicinity of 262.5H, counting from V-SINC. The problem here is the positional relationship between the DSP and V-SYNC.
As described above, V-SYNC is separated from the DSP by 7H, but an error of ± 2H is allowed in this distance.

Therefore, first, VSYNC to 252H
count. At this point, the position of 262.5H counted from the DSP is present between 1.5H and 5.5H (3.5H ± 2H) behind.

Here, the control pulse generator 307 generates the pulse A. The length of pulse A is about 0.5
H minutes. Next, at the falling edge of pulse A, pulse B '
Is generated. At the same time, the pulse B is also generated.

At the rising edge of the pulse B, the switch 301 is switched to stop the H-SYNC signal entering the phase comparator 303. At this time, just at 252H, the phase comparator 3
When the input of H-SYNC to 03 is stopped, as shown in FIG. 5, when the phase of the divided frequency of the VCO lags behind H-SYNC, the phase difference between the two becomes infinite,
The control voltage of the VCO 305 is disturbed. For this reason, as shown in FIG. 6, the pulse A is delayed by 0.5H and then the pulse B is raised, so that the H-SYNC
After comparing the output of the frequency divider 306 with that of the frequency divider 306, the phase comparator 3
The input to 03 is stopped.

While the pulse B'is rising, 6 H's are counted. That is, the pulse B'is at least 6
It has a length of H minutes. While this B'is standing up,
After taking into account the error of 4H, the fractional 0.5H can be skipped.

When 6 H-SYNCs are counted, the pulse C'is generated immediately. At the rising edge of pulse C ', pulse B is set to "L", and at the same time about 1.5H
Generate a pulse C of length

When the pulse B becomes "L", the switch 30
1 switches to the L side. Further, while the pulse C is rising, the switch 302 is switched to the H side. Therefore, the signal (H-SYNC) having the same phase is input to both the input terminals R and L of the phase comparator 303. Therefore, the phase error is zero. In other words, the phase comparator 303 is reset.

Here, when the pulse C rises, the H-SYNC input to the phase comparator 303 is incomplete H.
Since it is -SYNC (from the middle of H-SYNC), it is possible that the phase comparator 303 cannot be completely reset. For this reason, as shown in FIG. 7, the period of the pulse C is set to be long, and the H-SYNC that appears next is controlled so as to be input, so that the reset is surely executed.

After resetting, the normal P
Perform LL operation. Further, V-SYNC is input to the control pulse generator 307, and is reset every 1V.

FIG. 8 is a diagram showing waveforms of V-SYNC, H-SYNC, the output of the frequency divider 306, and the VCO control voltage when the discontinuous portion is read as it is. At the discontinuous portion, the phase of the output of the H-SYNC and the output of the frequency division 306 is significantly deviated, so that the VCO control voltage is greatly disturbed.

FIG. 9 shows the output of V-SYNC, H-SYNC and frequency divider 306 when H-SYNC is not input to the phase comparator near the DSP by applying this embodiment. It is a figure which shows the waveform of the pulse B corresponding to the VCO control voltage and the mask of a discontinuous part. As is clear from the figure, since the output of the frequency divider 306 and the phase of H-SYNC do not shift, the VOC control voltage shows a stable linear waveform.

As described above, according to the still video reproducing apparatus of the present invention, the write sampling pulse at the time of writing a signal to the memory is PLL based on H-SYNC.
Although it is generated by the (phase locked loop) circuit, it is PL at the discontinuous portion of the H-SYNC phase in the DSP of the disk.
Since it is controlled so that the phase comparison by L is not performed, a stable sampling pulse can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a still video playback device.

FIG. 2 is a diagram illustrating specifications of a magnetic disk.

FIG. 3 is a block diagram of a write sampling generator circuit.

FIG. 4 is a timing chart illustrating the operation of the present invention.

5 is a diagram for explaining a pulse A together with FIG. 6. FIG.

6 is a diagram for explaining a pulse A together with FIG. 5. FIG.

FIG. 7 is a diagram illustrating resetting of a phase comparator.

FIG. 8 is a diagram showing a disturbance of a VCO control voltage due to a discontinuous portion of H-SYNC.

FIG. 9 is a diagram showing a VCO control voltage when the present invention is applied.

[Explanation of symbols]

 303 Phase comparator 305 VCO 306 Frequency divider 307 Control pulse generator

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H04N 9/79 G 7916-5C

Claims (3)

[Claims] 1. A reading means for reading a video signal recorded on a recording medium, a storage means for storing the read video signal, and an image stored in the storage means based on a horizontal synchronizing signal included in the read video signal. Signal generating means for generating a pulse signal for writing a signal, and control means for controlling the signal generating means to ignore the horizontal synchronizing signal and generate a pulse signal in the vicinity of the point where the phase of the horizontal synchronizing signal changes. A still video playback device characterized by having. 2. The still video reproducing apparatus according to claim 1, wherein the recording medium is a magnetic disk. 3. The point where the phase of the horizontal synchronizing signal changes is a DSP (data recording start position) of the magnetic disk.
The still video reproducing apparatus according to claim 2, wherein