JPH0685620A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a single-phase clock shift register by providing independently a clock output terminal which outputs the clock signals of the same of reverse phases in response to the clock signal inputted from the outside. CONSTITUTION:The clock signal inputted through a clock input terminal 56 is supplied to a clock input terminal CK of an FF circuit 15 via a wiring 101. When the FF circuits 14 and 15 set the input data signals through the rising change of the clock signal, the clock signal is first inputted to the circuit 15 of the next stage and then to the circuit 14 of the precedent stage via a winding 102 after a delay equivalent to a load delay. Therefore the data signal that is set and outputted by the circuit 14 varies in a state a sufficient holding time is secured after the input data signal is set by the circuit 15. Thus the circuit 15 never causes an insufficient holding time of the data signal and therefore the malfunction of a shift register circuit can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit, and more particularly to a flip-flop circuit formed by a semi-custom type semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional flip-flop circuit of this type, as shown in FIG. 3, has transfer gates 17, 18 corresponding to a data input terminal 58, a clock input terminal 59, and data output terminals 60 and 61. And a master side latch circuit 16 including inverters 19 and 20, transfer gates 22 and 23, and inverters 24 and 2.
Slave side latch circuit 21 including 5 and inverter 2
And a clock driver circuit 26 including 7 and 28.

FIG. 4 is a block diagram showing an example in which a shift register circuit using a single-phase clock is constructed by using the flip-flop circuit shown in FIG. In FIG.
The clock input terminals of the two flip-flop circuits 29 and 30 are the clock input terminals 6 of the shift register itself.
3 connected in common, and the flip-flop circuit 2 of the previous stage
The data input terminal 9 is connected to the data input terminal 62 of the shift register itself. Flip-flop circuit 2
The data output terminal 9 is connected to the flip-flop circuit 3 in the subsequent stage.
0 is connected to the data input terminal, and the data output terminal of the flip-flop circuit 30 is connected to the output terminal of the shift register. Note that the operation of the shift register shown in FIG. 4 is generally well known and is not directly related to the content of the present invention, so its explanation is omitted.

[0004]

In the conventional flip-flop circuit described above, as shown in FIG. 3, since the only terminal related to the clock signal is the clock input terminal 59, the single terminal as shown in FIG. When configuring a shift register circuit using a phase clock, the clock input terminals of the flip-flop circuits 29 and 30 are commonly connected to the clock input terminal 63 of the shift register circuit, as described above. However, in the shift register circuit, the load delay due to the wiring length with respect to the clock input terminal of the flip-flop circuit 30 in the subsequent stage is caused by the flip-flop circuit 29 in the preceding stage
If the load delay due to the wiring length with respect to the clock input terminal is larger, the change in the output data of the front-stage flip-flop circuit 29 and the input clock of the rear-stage flip-flop circuit 30 compete with each other, and the rear-stage flip-flop circuit 30.
In, the data hold time becomes insufficient,
There is a drawback that the shift register circuit malfunctions.

Further, in the semi-custom type semiconductor integrated circuit, it is difficult to predict the wiring length in advance and prevent the above-mentioned malfunction because the wiring for the clock input terminal is automatically performed by the computer. In addition, since the wiring has many branches, there is a drawback that it is difficult to correct the wiring length.

[0006]

A flip-flop circuit of the present invention is a flip-flop circuit formed by a semi-custom type semiconductor integrated circuit, which corresponds to a clock signal input from the outside through a predetermined clock input terminal. In addition to the clock input terminal, a clock output terminal for outputting a clock signal having the same or opposite phase to the clock signal to the outside is provided separately from the clock input terminal. In addition,
A flip-flop circuit of the present invention is a master side latch circuit corresponding to a predetermined data input terminal, a slave side latch circuit corresponding to a predetermined pair of data output terminals, and a clock signal input via the clock input terminal. And a clock driver circuit that receives and supplies the master side latch circuit and the slave side latch circuit,
An output terminal of the clock driver circuit may be connected to the clock output terminal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment has a data input terminal 51, a clock input terminal 52, and a data output terminal 5.
A master-side latch circuit 1 including transfer gates 2 and 3, inverters 4 and 5, and a slave-side latch circuit 6 including transfer gates 7 and 8 and inverters 9 and 10 corresponding to 3, 54 and a clock output terminal 55. , A clock which includes inverters 12 and 13 and drives transfer gates 2, 3, 7 and 8.
And a driver circuit 11. Also, FIG.
Are flip-flop circuits 14 and 1 according to the present embodiment.
6 is a block diagram showing a single-phase clock shift register circuit configured by using FIG.

As is apparent from FIG. 1, the difference from the conventional example of the present invention is that the clock signal output from the clock driver circuit 11 via the inverters 12 and 13 is output to the outside. That is, the terminal 55 is newly provided. Other than that, the configuration and operation of the flip-flop circuit itself are exactly the same as those of the conventional example. By providing the clock output terminal in this manner, when the single-phase clock shift register circuit shown in FIG. 2 is configured, it is possible to obtain the effect of avoiding a malfunction in the shift register circuit. The operation of the shift register circuit shown in FIG. 2 will be described below.

In FIG. 2, the clock signal input from the clock input terminal 56 is input to the clock input terminal 52 (see FIG. 1) of the flip-flop circuit 15 via the wiring 101. In the flip-flop circuit 15, the data signal output from the flip-flop circuit 14 is set through this rising change of the clock signal, and then the data signal is passed through the clock driver 11 (see FIG. 1) in the flip-flop circuit 15. Output from the clock output terminal 55 of the flip-flop circuit 15 (see FIG. 1) and the clock input terminal 5 of the flip-flop circuit 14 via the wiring 102.
2 (see FIG. 1). Flip-flop circuit 1
In 4, the data signal input from the data input terminal 56 of the shift register is set in the flip-flop 14 in response to this clock signal.

As described above, in the two flip-flop circuits 14 and 15 which are adjacent to each other in the preceding stage and the succeeding stage, when the input data signal is set in each flip-flop circuit through the rising change of the clock signal. , The clock signal is first input to the flip-flop circuit 15 in the subsequent stage, then passes through the wiring 102, and is input to the flip-flop circuit 14 in the previous stage after a delay of the load delay of the wiring 102. Therefore, the data signal that is set and output in the front-stage flip-flop circuit 14 is output to the rear-stage flip-flop circuit 15.
At, the input data signal is set and changes in a state where a sufficient hold time is secured. Therefore, in the flip-flop circuit 15 in the subsequent stage, the situation where the hold time of the data signal is insufficient does not occur, and malfunction of the shift register circuit is prevented.

Further, even if the load length of the wiring with respect to the clock input terminal of the flip-flop circuit 15 increases due to the increase in the wiring length of the wiring 102, the margin for the hold time of the data signal tends to increase. Therefore, in the automatic wiring in the semi-custom type semiconductor integrated circuit, it is not necessary to care about the wiring length and it is not necessary to predict the wiring length in advance. Further, the wiring 102 only connects the clock input terminal of the front stage flip-flop circuit 14 and the clock output terminal of the rear stage flip-flop circuit 15, and there is no other branch, so the wiring length is adjusted. Can be easily corrected.

In the flip-flop circuit described above, as shown in FIG. 1, the clock output terminal 55 is connected to the clock input terminal 52 via the clock driver circuit 11 including the inverters 12 and 13. However, the same effect can be obtained even if the clock output terminal 55 is directly connected to the clock input terminal 52 or is separately connected via a delay circuit. To be

Further, the single-phase clock shift register circuit according to the above description is exemplified by a shift register composed of two sets of flip-flop circuits, but if the wiring for the clock terminal is the same, The same effect can be obtained regardless of the number of stages of shift register circuits without this.

[0015]

As described above, the flip-flop circuit of the present invention is provided with the clock output terminal for outputting a specific clock signal corresponding to the clock signal input to the clock input terminal. Applied to a shift register configured to input the clock signal output from the clock output terminal of the subsequent flip-flop circuit to the clock input terminal of the previous flip-flop circuit in relation to each other. Therefore, there is an effect that the malfunction of the shift register can be prevented.

Further, even in the state where the wiring length between the clock terminals of each flip-flop is long, in the semi-custom type semiconductor integrated circuit, it is not necessary to pay attention to the wiring length by the automatic wiring, and the wiring length is set in advance. This has the effect of eliminating the need for prediction.

Furthermore, since the wirings for the clock input terminal and the clock output terminal of each flip-flop circuit are the wirings only connecting the clock input terminal and the clock output terminal of each flip-flop circuit, there is no branching, so that Therefore, there is an effect that the correction for adjusting the wiring length can be easily performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a shift register configured according to this embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a block diagram showing a shift register configured by a conventional example.

[Explanation of symbols]

1, 16 Master side latch circuit 2, 3, 7, 8, 17, 18, 22, 23 Transfer gate 4, 5, 9, 10, 12, 13, 19, 20, 24, 2
5, 27, 28 Inverter 6, 21 Slave side latch circuit 11, 26 Clock driver circuit 14, 15, 29, 30 Flip-flop circuit

Claims (2)

[Claims] 1. A flip-flop circuit formed by a semi-custom type semiconductor integrated circuit, which corresponds to a clock signal input from the outside through a predetermined clock input terminal, and which is in-phase or anti-phase with the clock signal. A flip-flop circuit comprising a clock output terminal for outputting a signal to the outside, separately from the clock input terminal. 2. A master side latch circuit corresponding to a predetermined data input terminal, a slave side latch circuit corresponding to a predetermined pair of data output terminals, and a clock signal input through the clock input terminal. The flip-flop circuit according to claim 1, further comprising: a clock driver circuit that supplies the master-side latch circuit and the slave-side latch circuit, wherein an output end of the clock driver circuit is connected to the clock output terminal. .