JPH0685280B2 - On-chip memory inspection circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an on-chip ECC (Error Correcting Circuit) in a dynamic RAM (DRAM), and particularly to an on-chip memory inspection circuit capable of setting its initial condition. Regarding

[Technical background of the invention]

In general, the integration of RAM has been achieved mainly by reducing the memory cell area, centering on the progress of circuit technology and minute process technology that handle minute signals. However, as a result, the problem of soft error caused by the decrease of the charge storage amount of the memory cell is caused.

In order to solve this problem, an on-chip ECC that automatically corrects a bit error such as a soft error in a memory has been proposed. As a self-correction method for such on-chip ECC, a horizontal / vertical parity method, a Hamming code method, etc. are mainly used.

As shown in FIG. 6, the horizontal / vertical parity method is 1
A large number of information bits read out when the word line WL of one book is selected is divided into m blocks every n bits,
In this method, vertical parity and vertical parity calculated in a matrix of m rows and n columns in which these are virtually arranged in parallel are stored in the check bits. When reading, the same operation is performed, and the newly calculated horizontal parity and vertical parity are compared with the information already stored in the check bit, and when both horizontal and vertical parity do not match, it is at the intersection. The information bit is determined to be defective and the data is inverted and corrected. At this time, it is clear from the fact that the memory itself is configured in 2 ⁿ rows × 2 ⁿ columns, that the m rows and n columns rows and columns that are virtually set are always even numbers.

[Problems of background technology]

By the way, the cell plate potential of a normal DRAM is set to V _cc (power supply potential) or V _ss (ground potential). Then, after the power is turned on, when the cell plate reaches the set potential, all the cell nodes have a potential close to the plate potential depending on the plate potential. However, even if the information is read from the cell of the same potential, the output data “1”, “0” will be different depending on which bit line pair (BL, ▲ ▼) is connected to the sense amplifier. different.

When the matrix of m rows and n columns as described above is considered, the value of each information bit immediately after power-on is either "1" or all "0". At this time, since both m and n are even numbers,
The calculated horizontal and vertical parity should always be "0". However, since the information of the check bit also depends on which of the bit line pairs connected to the sense amplifier is attached, like the value of each information bit, if the content of each information bit is "1", All check bit contents are also "1"
Become. Therefore, before the ECC is activated for the first time after the power is turned on, it is necessary to perform initialization so that the information bit and the check bit can be correlated with each other. The time required for this initialization becomes longer as the RAM is highly integrated, and a countermeasure against it is desired.

[Object of the Invention]

The present invention has been made in view of the above circumstances,
An object of the invention is to provide an on-chip memory inspection circuit which can make the information bit and the inspection bit inconsistent at the time of power-on and does not require initialization.

[Outline of Invention]

That is, in order to achieve the above object, the present invention is provided with a switching circuit for converting the information of the check bit using the word line selection address so that the information of the check bit is always correlated with the information bit.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. A bit line pair BL, ▲ ▼ is connected to both ends of the sense amplifiers 11 in FIG. 1, and an input / output circuit (not shown) is connected thereto. Memory cells 12, 12, ... Are provided at respective intersecting positions of the bit line pair BL, ▲ and the word lines WL, WL. Each memory cell 12
Is composed of a transfer MOS transistor Q and an information storage capacitor C, and is selected by the outputs of the row decoders 13 ₁ and 13 ₂ . Each of the row decoders 13 ₁ and 13 ₂ has a word line selection address signal. Is supplied with this signal Depending on which of the bit line pair BL and ▲ ▼ the memory cell 12 associated with is selected, is selected. Therefore, the word line selection address signal If the side where the check bit is "1" is inverted when the power is turned on, the content of the check bit becomes "0" and the correlation with the information bit can be obtained. For example, the word line selection address signal FIG. 2 shows an example of a read circuit when the check bit becomes "1" when is selected.

In FIG. 2, the switch circuit 14 is supplied with horizontal or vertical parity information A and B in the check bit, and the word line selection address signal is supplied. Based on the above, the horizontal or vertical parity information A, B is directly supplied to the exclusive OR gates 15 ₁ , 15 ₂ in the next stage or inverted and supplied by the inverters 16 ₁ , 16 ₂ . Exclusive OR gate 15 ₁ , 15 _{2 above}
Calculated horizontal or vertical parity A ', B'is supplied to the other input terminal of the
Supplied to 17. The output of the AND gate 17 is supplied to the exclusive OR gate 18 together with the information C in the selected memory cell, and the rewriting information C'to the memory cell after the error check is obtained from the output end of the exclusive OR gate 18. It will consist of

In the above configuration, the word line selection address signal N channel type MOS transistors Q ₁ , Q ₂ and Q ₃ , Q
₄ conduction control, word line selection address signal When is selected, the inverter 16 ₁ inverts the parity and supplies it to the exclusive OR gate 15 ₁ . Then, it is determined whether or not the information to be read is an error by comparing it with the calculated value A'of the information bit, and when there is an error, it is corrected. By doing so, the information bit and the check bit can be correlated after the power is turned on.

By the way, if the contents of the check bits are inverted at the time of reading, it is necessary to invert the information when the information is stored in the check bits. FIG. 3 shows that when information is stored in the check bit,
Word line selection address signal Horizontal or vertical parity A ', B'calculated based on
An example of a write circuit for selecting whether to write as it is or to invert and write is shown. That is, the word line selection signal The N-channel type MOS transistors Q ₅ and Q ₆ are controlled to be conductive by the word line selection signal. Is "1" level, the horizontal or vertical parity A ', B'is inverted by the inverter 19 and supplied to the check bit. On the other hand, when the word line selection signal A _i is at "1" level, the horizontal or vertical parity A ', B'is directly supplied to the check bit. By using such a circuit, the word line selection signal Inversion information can be stored in the check bit when is selected, and the check bit and the information bit can always be correlated.

With such a configuration, the content of the check bit can be always correlated with the content of the information bit by using the word line selection address signal.

That is, if the content of the check bit cannot be correlated with the content of the information bit after the power is turned on, it is considered that the content of the check bit is inverted and then read or inverted and then written. Therefore, the troublesome initialization after turning on the power to the RAM is not necessary, and the initialization time can be greatly reduced.

FIG. 4 shows another example of the configuration of the read circuit shown in FIG. 2, and the exclusive OR gates 15 ₁ and 15 ₂
After comparing the horizontal or vertical parity A, B in the check bit with the calculated horizontal or vertical parity A ', B', the outputs of the exclusive OR gates 15 ₁ , 15 ₂ are directly output. The switching circuit 14 selects whether to use or invert. 4, the same components as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the above configuration, if the content of the check bit is "1", it does not always match the calculated value of the information bit. Therefore, even with such a configuration, the same operation as that of the circuit of FIG. To be

The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the N-channel type MOS transistor in FIGS. 2, 3, and 4 is changed to the P-channel type. , Word line selection address signal You can change to. Further, if the exclusive OR circuit 20 as shown in FIG. 5 is used instead of the switching circuit shown in FIGS. 2, 3, and 4, it is possible to make only one address input.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain the on-chip memory inspection circuit which can make the information bit and the inspection bit inconsistent at the same time when power is turned on and does not require initialization.

[Brief description of drawings]

1 to 3 are views for explaining an on-chip memory inspection circuit according to an embodiment of the present invention, and FIGS. 4 and 5 are respectively for explaining other embodiments of the present invention. 6 and 6 are diagrams for explaining a conventional on-chip memory inspection circuit. 14 ... Switching circuit, ... word line selection address signal, A, B ... horizontal or vertical parity information in check bit, A ', B' ... calculated horizontal or vertical parity, C ... information in selected memory cell, C '... Information rewritten to the memory cell after the error check.

Front page continuation (72) Inventor Toru Furuyama 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute Co., Ltd. (72) Inventor Masaki Ogihara 2-11, Higashida-cho, Kawasaki-ku, Kanagawa Prefecture Toshiba Microcomputer Engineering Co., Ltd. (56) Reference JP-A-58-182194 (JP, A)

Claims (3)

[Claims] 1. In a dynamic RAM having a horizontal / vertical parity type error correction circuit provided on a semiconductor substrate, a bit line pair is associated with a cell selected on the basis of a word line selection address signal. A switching circuit is provided to select whether to invert the horizontal and vertical parity information read from the check bit and the horizontal and vertical parity information to be written to the check bit. When reading data, the output of this switching circuit and the calculated horizontal And vertical parity information are compared to determine whether or not the data of the information bit to be read is an error, and when the error occurs, the data of the information bit is corrected and rewritten. Write the output to the check bit as the horizontal and vertical parity information above. The on-chip memory test circuit, characterized in that correlating the examination of bit information and the information of the bit information. 2. The switching circuit selects whether or not to invert the horizontal and vertical parity information of the check bit based on the word line selection address signal, and matches the logic of the check bit information and the information bit information. The on-chip memory inspection circuit according to claim 1, wherein the on-chip memory inspection circuit is a circuit. 3. The switching circuit correlates the horizontal and vertical parity information of the check bit with the information of the information bit by switching the error correction signal corresponding to the word line selection address signal. The on-chip memory inspection circuit according to claim 1, characterized in that.