JP2642094B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] A semiconductor memory device having a built-in error correction circuit for automatically correcting a bit error occurring in a memory.
Paying attention to the storage information of the memory cell which is automatically set, the parity of the error correction code group to which the memory cell connected to one bit line of the bit line pair belongs, even or odd, and the other of the bit line pair. By setting the parity of the error correction code group to which the memory cell connected to the bit line belongs to an even number or an odd number, the initial setting of the test cell information is not required. By grounding, the physical "0" state, that is, the initial setting can be automatically performed regardless of the time after the power is turned on.

[Industrial applications]

The present invention relates to a semiconductor memory device having a built-in error correction circuit for automatically correcting a bit error occurring in a memory, and more particularly to a semiconductor memory device that does not require initial setting of inspection information.

[Conventional technology]

As a conventional semiconductor memory device of this type, a semiconductor memory device that automatically corrects a bit error by applying a horizontal / vertical parity code to a plurality of memory cells connected to one word line has been proposed. (Japanese Patent Application No. 56-37)
No. 223, JP-A-57-152597). FIG. 3 shows an example of the configuration, and FIG. 4 shows the principle of error correction using horizontal and vertical parity codes. First, the principle of error correction will be described with reference to FIG. The output bit 30 to be read is bit information forming one error correction code, and this bit information is developed into a two-dimensional matrix shown on the right side of FIG. Reference numeral 28 denotes one vertical group, 29 denotes one horizontal group, and the parity of each vertical group and each horizontal group is constant (for example, even parity is established). Therefore, in the present embodiment, the independent bit information is 16 out of 25 bit information, 31 is 4 horizontal parity bits, 32 is 4 vertical parity bits, and
33 is a horizontal and vertical parity bit. Now, when reading the bit information of the output bit 30 to be read, the parity of the vertical group 28 and the horizontal group 29 to which the bit information of the output bit 30 to be read belongs is checked. When a parity error occurs in both cases, this means an error in the bit information of the output bit 30 to be read, so that the output bit 30 to be read is
Is inverted, that is, corrected and output. This is the principle of error correction by the horizontal / vertical parity code, and corresponds to, for example, memory cell information connected to the same word line, for which 27 horizontal / vertical parity codes are simultaneously accessed.

In the configuration example shown in FIG. 3, 1 is a memory cell, 2 is a test cell for storing parity information, 3-1 and 3-2 are a pair of bit lines connected to a sense circuit indicated by 7, and 4-1. , 4-
2 is a pair of test bit lines connected to the test sense circuit indicated by 8, 5-1 and 5-2 are word lines in the cell array indicated by 6-1 and 6-2, and 9 is a row including a word driver. A decoder, 10 is a row address signal, 1 and 12 are a horizontal group selector for selecting a horizontal group 29 (shown in FIG. 4) and a vertical group selector for selecting a vertical group 28, 13 is a memory cell multiplexer, and 14 is a test. Cell multiplexer, 15, 16 are horizontal group parity check circuit and vertical group parity check circuit, 17-1 is AND gate, 18, 22, 23-1, 23-2, 23-3 is E
An OR gate, 19 is an output terminal, 20 is an input terminal, 21 is a switch which is turned on at the time of writing, and 34 is a test cell information initial setting circuit. In this configuration example, the read memory cell information is selected by the 13 multiplexers at the time of reading,
One horizontal group and one vertical group to which the read memory cell information belongs are selected by the selectors 11 and 12, and the parity is checked by the parity check circuits 15 and 16. In this example, the circuit configuration is based on the assumption of even parity, and only when a parity error occurs in both of the parity check circuits 15 and 16 is 17-
The output of the 1 AND gate becomes "1", and the read memory cell information is corrected and output by the 18 EOR gates. At the time of writing, simultaneously with the writing operation to the memory cell 1, the horizontal parity bit of the horizontal group and the vertical parity bit of the vertical group of the write memory cell only when the previous storage information of the write memory cell differs from the write data. , And the horizontal and vertical parity bits, the test cell multiplexer 14, the EOR gates 22, 23-1, 23-2 and 23-3.
Use to invert. As a result, the even parity is maintained.

[Problems to be solved by the invention]

In the configuration of the conventional semiconductor memory device, the test cell information is updated using the parity relationship at the time of writing, so that all memory cells and all test cells are initially set to "0" so that even parity is established. Therefore, an additional circuit or an additional external terminal such as the test cell information initial setting circuit shown in FIG. 3 is required. Initial setting of all memory cells and all test cells is performed as follows. First, EOR circuits 23-1, 23-2 and 23-3 (hereinafter 23-1 to 23-3) are set so that the check cells which are parity bits (horizontal parity bit, vertical parity bit, and horizontal / vertical parity bit) are not updated. 3) is suppressed from affecting the test cell multiplexer 14. Next, one bit of the memory cell is forcibly initialized to "0". Further, the test cell corresponding to the initialized memory cell is forcibly initialized to “0”. The compulsory initialization is performed for all the memory cells and the test cells corresponding to each memory cell. At this time, although redundant, the test cell is updated many times. Assuming that the information bit width is (2m) × (2k), the initialization is performed the number of times. Since the initial setting to the memory cell can be performed from the input terminal 20, the test cell information initial setting circuit 34 has other functions. The signal input from the output of the test cell information initial setting circuit 34 to the test cell multiplexer 14 in FIG.
A control signal for suppressing the influence of the output signals of the EOR circuits 23-1, 23-2 and 23-3 (hereinafter referred to as 23-1 to 3-3) on the test cell multiplexer 14, the test cell information signal and the address of the test cell. Signal. The test cell information initial setting circuit 34 does not operate during normal writing.

[Means for solving the problem]

The present invention focuses on the storage information of a memory cell that is automatically set after power-on, and removes a memory connected to one bit line of a bit line pair to an error detection circuit. In each case of the cell information check and the memory cell information check connected to the other bit line, the even and odd parity of the bit line information and the check bit line information belonging to the same error correction code group are checked. ,
It is characterized by comprising means for setting opposite to each other.

[Action]

According to the present invention, the parity of the parity of the error correction code group to which the memory cell connected to one bit line of the bit line pair belongs, and the error to which the memory cell connected to the other bit line of the bit line pair belongs. By setting the evenness and oddness of the parity of the correction code group in reverse, the initial setting of the inspection cell information becomes unnecessary. "The state, that is, the initial setting can be automatically performed.
This will be described below with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and the same reference numerals as those in FIG. 3 denote the same parts. The difference from the conventional configuration shown in FIG.
And 10-1 is one of the row address signals, which is "1" when selecting the cell array 6-1 and "0" when selecting the cell array 6-2. Signal. The circuits 15 'and 16' are the same as the parity check circuits 15 and 16 in FIG. 3, but the number of input bits is increased by one each.

By the way, assuming that the cell plate potential of the node N2 of the memory cell 1 and the test cell 2 is the power supply voltage Vcc, the potential of the node N1 in the memory cell indicated by 1 and the test cell indicated by 2 after the power is turned on is the power supply voltage Vcc. The voltage is raised to the level, and after several tens of seconds, it reaches the 0V level due to discharge such as leakage. When the cell plate potential of the memory cell 1 and the test cell 2 is set to Vss, that is, the ground level, the node N
The potential of 1 settles to 0V level immediately after power-on. Therefore, the state of all memory cells and all test cells after power-on is physically “0” (Low state) or physical “1” (High state).
State).

Paying attention to this fact, the read operation of the memory cell information existing in the cell array 6-1 and the cell array 6-2 in FIG. 1 will be described below assuming that the cell plate potential is 0V. When the word line 5-1 in the cell array 6-1 is selected, the physical "0" information of the memory cell 1 and the test cell 2 connected to the word line 5-1 is transmitted to the bit line 3-1 and the test cell. Appears on bit line 4-1. Thereafter, the sense circuit 7 and the test sense circuit 8 perform an amplification operation based on the reference signal on the bit line 3-2, and the bit line 3-1 and the test bit line 4 are amplified.
The small signal on -1 is amplified and supplied to the horizontal and vertical group selectors 11 and 12 or the memory cell multiplexer 13 through the bit line 3-2 or the like.

In a semiconductor memory device of this type, two
One bit line forms a pair, and a memory cell is connected to each bit line. On the other hand, since the input / output circuit is connected to either line of the bit line pair, when the cell data is viewed from the input / output side, the cell array data on one side is “0” as logical information through the sense circuit, and In the cell array data of "1", "1" is initialized as logical information.

That is, the signal on the bit line 3-2 is changed to the bit line 3-1.
Are all "1" states.

Therefore, when these pieces of information are rearranged two-dimensionally as shown in FIG. 4, the information bit width is usually (2m) × (2
k) (m and k are integers) and are even numbers, so that considering that there is one check bit in each of the horizontal and vertical groups, the total number of bits is odd and each bit is “1”. In this state, odd parity is established in all the horizontal groups and the vertical groups.

On the other hand, in FIG. 1, the parity setting row address signal 10-1 is "1" because the cell array 6-1 is selected.
Signal.

When the odd group of the horizontal group and the vertical group is destroyed, the even group becomes the even group with only the horizontal group or the vertical group, and the odd parity is established in addition to the parity setting address signal “1”. Therefore, when the odd parity of the horizontal group and the vertical group are both destroyed, the error detection circuit 24
Since the output of -1 becomes "1", the output is corrected by the EOR gate 18.

On the other hand, when the word line 5-2 in the cell array 6-2 is selected, the physical "0" information of the memory cell and the test cell connected to the word line appears on the bit line indicated by 3-2. In this case, after the operation of the sense circuit 7, the bit lines 3-2 are all in the "0" state, and all the horizontal groups and vertical sources of the horizontal and vertical parity codes constituted by such information establish even-numbered parity. However, in this case, since the row address signal of 10-1 is "0",
A conventional even parity check is performed in the horizontal and vertical group parity circuits 15 'and 16'. When a parity error occurs, the output of the error detection circuit 24-1 becomes "1". Gate 18 corrects the output.

Next, with respect to the write operation, as in the conventional example, the write operation to the memory cell 1 and the horizontal group to which the write memory cell belongs are performed only when the previous storage information of the write memory cell and the write data are different. The three information of only the horizontal parity bit, the vertical parity bit of the vertical group, and the horizontal / vertical parity bit are input to the test cell multiplexer 14 and the EOR gate 2.
Invert using 2, 23-1, 23-2 and 23-3. As a result, the same parity as in the conventional example is maintained. There is no difference in whether the original parity is even parity or odd parity.

FIG. 2 shows an embodiment of a main part of the present invention, that is, an embodiment corresponding to the error detection circuit 24-1 in FIG.
Is an AND gate, 17-2 is a NOR gate, 26 is a switch controlled by one of the row address signals indicated by 10-1.
When the signal -1 is "1", the output line 25- of the NOR gate 17-2 is output.
2 and the signal to the output line 25-1 of the AND gate 17-1 when the signal of 10-1 is "0" is 18 EORs.
Input to the gate. The logic of the error detection circuit indicated by 24-2 is the same as the logic of the error detection circuit of 24-1 in FIG. 1, and it is apparent that this embodiment does not require an additional circuit for initial setting. Out.

By the way, in FIG. 1, a symmetrical bit line configuration which is easy to understand is described as an example. However, the same applies to a folded bit line configuration. By
No initial settings are required.

〔The invention's effect〕

As described above, the present invention focuses on the storage information of a memory cell that is automatically set after power-on, and determines the error correction code group to which the memory cell connected to one bit line of the bit line pair belongs. Since the even and odd parity of the error correction code group to which the memory cell connected to the other bit line of the bit line pair belongs to the even or odd parity, the check cell information is initialized. This has the advantage of eliminating the need for additional circuits.

Further, by grounding the cell plate potential, there is an advantage that the physical "0" state, that is, the initial setting can be automatically performed regardless of the time after the power is turned on.

[Brief description of the drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2 is an embodiment of an error detecting circuit of a main part of the present invention, FIG. 3 is a configuration example of a conventional semiconductor memory device, and FIG. 4 is a principle diagram of error correction. is there. 1 ... memory cell, 2 ... test cell, 3-1, 3-2 ...
Bit line pairs, 4-1 and 4-2 ... Inspection bit line pairs, 5-1 and 5
-2 ... word line, 6-1, 6-2 ... cell array, 7 ...
... Sense circuit, 8... Inspection circuit, 9... Row decoder including word driver, 10... Row address signal, 10-1... One of row address signals, 11... Horizontal group selector, 12. … Vertical group selector, 13 …… Multiplexer for memory cells, 14 …… Multiplexer for test cells, 1
5,15 '... Horizontal group parity check circuit, 16,16' ...
Vertical group parity check circuit, 17-1 ... AND gate, 1
7-2… NOR gate, 18, 22, 23-1, 23-2, 23-3, EO
R gate, 19 ... output terminal, 20 ... input terminal, 24-1, 2 ...
... Error detection circuit, 25-1, 25-2 ... Output line, 26 ... Switch, 27 ... Horizontal / vertical parity code, 28 ... Vertical group, 29
… Horizontal group, 30… Output bit, 31… Horizontal parity bit, 32… Vertical parity bit, 33… Horizontal vertical parity bit, 34… Additional circuit for initial setting.

Claims (2)

(57) [Claims] 1. A plurality of memory cells for storing information, a plurality of check cells for storing parity information for detecting a bit error occurring in a memory cell portion, and a plurality of check cells connected to the memory cells and connected via a sense circuit. A plurality of pairs of bit lines for exchanging information connected to each other, a plurality of pairs of test bit lines for exchanging parity information connected to the test cell and connected via a sense circuit, and a memory cell to be inspected An error detection circuit for checking the presence / absence of an error in the memory cell information to be inspected by means for examining the parity of the even-numbered bit line information and the parity of one inspection bit line information belonging to the error correction code group to which the error correction code group belongs; An error correction circuit for correcting the memory cell information to be inspected based on the output of the detection circuit is provided. In the semiconductor memory device having the state of "", the error detection circuit, when inspecting information of a memory cell connected to one bit line of the bit line pair, the bit line information belonging to the same error correction code group and Means for checking the even (or odd) parity of the check bit line information; and checking the memory cell information connected to the other bit line of the bit line pair, the bit line information belonging to the same error correction code group and Means for examining the odd (or even) parity of the check bit line information, so that the parity of the error correction code group to which each of the memory cells connected to the one bit line and the other bit line of the bit line pair belongs. Even number of
A semiconductor memory device wherein odd numbers are set opposite to each other. 2. The memory cell according to claim 1, wherein said memory cell and said test cell are one-transistor type memory cells having a cell plate potential at a ground level.
13. The semiconductor memory device according to claim 1.