JPH0560197B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

2. Description of the Related Art Conventionally, as part of information theory, a circuit (hereinafter referred to as an ECC circuit) that corrects errors in data using an error correcting code has been known.

Prior to this development, the inventor of the present application considered incorporating an ECC circuit into a one-chip semiconductor memory device to relieve defective memory cells and improve the yield thereof. In this case, an ECC circuit with a 1-bit error correction function requires, for example, 4 bits of parity for 8 bits of data, 6 bits of parity for 32 bits of data, and 100 bits of parity. 8-bit parity is required for the data. As described above, when the number of data bits is small, the ratio of parity bits to the total number becomes large, and the actual storage capacity of the memory array becomes small. On the other hand, increasing the number of data bits requires a large number of external terminals for data output, so in semiconductor memory devices,
It becomes impossible to incorporate the above ECC circuit.

Therefore, an object of the present invention is to reduce the number of external terminals while increasing the actual storage capacity.
An object of the present invention is to provide a semiconductor memory device with a built-in ECC circuit.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1A shows a block diagram of an embodiment in which the present invention is applied to a mask type ROM.

In the figure, although not particularly limited, memory cells of approximately 1 megabit are arranged in memory arrays (M-ARY _{1 to M-ARY 4 )} each having a storage capacity of 512 columns (rows) x 608 rows (columns) = 311,296 bits. A circuit configuration diagram of a mask-type ROM arranged separately is shown. The main blocks in this figure are drawn according to their actual geometry. In addition, each block is a MOSFET formed on a single semiconductor substrate using known semiconductor integrated circuit technology.
It is made up of.

Each memory array M-ARY ₁ to M-ARY ₄
is constituted by a dynamic circuit and includes a dummy array for forming a read reference voltage.

The address buffer ADB, which receives address signals A ₀ to A ₁₆ from the outside, is constituted by a static type circuit, and on the other hand, internal complementary address signals A ₀ , ₀ to A 16 that are transmitted to the address decoder.
Form a ₁₆ , ₁₆ . It should be noted that, although not particularly limited, the address signals _A0 to _A16 are accepted by an external chip selection signal.

_{Among the} complementary address signals _a0,0 to _a16,16 , _{address signals a0,0 to a9,9 are transmitted} to the X decoders _DCR1 , _{DCR2 .} Further, the remaining address signals a ₁₀ , ₁₀ to a ₁₆ , ₁₆ are transmitted to the Y decoders Y ₁ DCR and Y ₂ DCR.

Although not particularly limited, the above address decoder
XDCR ₁ to Y ₂ DCR are constituted by static type circuits.

The above memory array M-ARY ₁ to M-ARY ₄
The row-related address selection lines (word lines) include X address decoders (also word line drivers) XDCR ₁ , which receive the address signals a ₀ , ₀ to a ₉ , ₉ .
2 ¹⁰ =1024 word line selection signals formed by XDCR ₂ are applied. Among these, the 512 word line selection signals formed by XDCR ₁ are the 512 word line selection signals formed by XDCR ₁ ^,
The signal is applied to word lines W ₉ to _{W 511} of the book, respectively.
On the other hand, the remaining 512 word line selection signals formed by XDCR ₂ are sent to the right memory array M-ARY ₃ ,
512 word lines W ₅₁₂ to W ₁₀₂₃ in M-ARY ₄
are applied respectively.

Furthermore, when selecting the memory cells of the left memory arrays M-ARY ₁ and M-ARY ₂ based on the address signals a ₉ and ₉ of the most significant bits, the XDCR ₁ and XDCR ₂ select the dummy arrays on the right. Conversely, when selecting the memory cells of the right side memory arrays M-ARY ₃ and M-ARY ₄ , a dummy word line selection signal for selecting the leftmost dummy array is also generated.

The Y ₁ decoder Y ₁ DCR outputs 5-bit address signals a ₁₀ , ₁₀ to a ₁₄ , among the remaining address signals.
a ₁₄ to form 32 decoded output signals. As mentioned above, since each memory array M-ARY ₁ to M-ARY ₄ has 608 rows,
Column switches CW ₁ to CW ₄ are controlled so that 19 rows are simultaneously selected by one decode output signal. As a result, the column switches CW ₁ and CW ₂ switch the left memory array M-
Column switches CW ₃ and _{CW 4 transmit} signals from a total of 38 memory cells (or dummy cells) in ARY 1 and M-ARY _2.
-Transmits signals from a total of 38 dummy cells (or memory cells) in ARY ₃ and M-ARY ₄ .

The sense amplifier SA receiving signals from the column switches CW ₁ to CW ₄ is composed of a total of 38 dynamic differential amplifier circuits.

By selecting the word line, for example, when reading information from the left memory array, the differential amplifier circuit receives the read reference voltage from the dummy cell of the right memory array and the signal from the memory cell of the left memory array. It receives the signal and determines whether the signal is "1" or "0".

The address buffer is used to form clocks necessary for the operation of the dynamic ROM array and sense amplifier, such as timing signals for precharge and discharge.
An edge trigger that receives address signals from the ADB and a timing generation circuit are provided. The above edge trigger uses the above address signal a ₀ to a _14.
A trigger pulse is generated by detecting a level change in either of the chip selection signal and the chip selection signal. The timing generation circuit receives the trigger pulse and forms various timing signals necessary for read operations of the memory array and sense amplifier SA. In the figure, a timing signal _PC that controls precharge and discharge of the memory array and sense amplifier, a timing signal _φX that defines the word line selection timing, and a sense amplifier
Timing signal φ _PA1 that defines the activation timing of SA is shown as a representative.

The information read from the 38 memory cells determined by the one X decode output (word line selection) signal and one Y decoder output (column selection) signal is simultaneously error-corrected through the sense amplifier SA. The signal is input to a circuit (hereinafter referred to as an ECC circuit), where error correction is performed. Of these 38 bits of read information, 32 bits of information are used as data signals, and the remaining 6 bits of information are used as redundant (parity) signals.

The above-mentioned ROM is used as a kanji pattern generation circuit in which one character consists of 32×32 dots, although this is not particularly limited. Therefore, the ROM can store 1024 characters.

The ECC circuit described above is constituted by a static type circuit, although it is not particularly limited. Therefore, although not particularly limited, the sense amplifier SA is provided with a latch circuit that also serves as a main amplifier that receives the output signal of the dynamic differential circuit and forms a static output signal.

The 32-bit data signal whose error is corrected by the above ECC circuit is converted into 8 bits by the multiplexer.
Each bit is passed to the output buffer four times, and all bits are output. For such time allocation operations, the remaining two bits of address signals a ₁₅ and a ₁₆ are used. In other words, the above address signal
_Y2 decoder _{Y2 DCR receiving a15,15} and _a16,16
Accordingly, four types of control signals can be formed, and 8 bits each can be outputted in parallel from the multiplexer four times in accordance with changes in these address signals.

The output buffer is constructed of a static type circuit and has a three-state output function including, but not limited to, a high output impedance state.

Each of the above-mentioned main circuit blocks will be explained in detail below along with more specific examples.

FIG. 1B is a block diagram showing one embodiment of the edge trigger and timing generation circuit.

Address signals a ₀ to a ₁₄ from the address buffer ADB mentioned above are sent to delay circuits Delay ₀ to Delay _14.
, and delay circuits a ₀ ′ to a ₁₄ ′ are formed at its output. Input signals a ₀ to a ₁₄ of the delay circuits Delay ₀ to Delay ₁₄ and their delayed output signals a ₀ ′ to a ₁₄ ′ are input to exclusive OR circuits EX ₀ to EX ₁₄ , respectively. The outputs of the exclusive OR circuits EX ₀ to EX ₁₄ are transmitted to an OR circuit, where an edge trigger pulse φ _apd is formed.

As shown in FIG. 1C, in the exclusive OR circuit EX ₀ , when the address signal a ₀ changes, a level mismatch occurs between the input signals a ₀ and a ₀ ' in the delay time. A pulse with a pulse width commensurate with the delay time is formed in the output. Therefore, the edge trigger pulse φ _apd is output from the OR circuit when any one of the address signals a ₀ to a ₁₄ changes.

In other words, the address signals A ₀ to _{A 14} are changed asynchronously so that the edge trigger pulse φ _apd is generated whenever any of the address signals A ₀ to _{A 14} changes. However, in order to generate the edge trigger pulse φ _apd , the address buffer circuit ADB is constructed of a static type circuit. Although not particularly limited, in this embodiment, a p-channel type
The address buffer circuit is composed of a CMOS (complementary MOS) circuit composed of a MOSFET and an N-channel MOSFET. An embodiment of a static address buffer circuit constructed from a CMOS circuit is shown in FIG. 1E. The figure only shows the part that receives address signal A ₀ and forms complementary address signals a ₀ , ₀ , but similar circuits are provided for other address signals as well. .

In the following description, in order to simplify the drawings, circuit symbols will be used as shown in FIG. 2B. That is, in FIG. 2B, the circuit symbol with the suffix P indicates a P channel type MOSFET,
The circuit symbol with the subscript N is the N channel type.
The MOSFET and the circuit symbol with an X mark indicate an N-channel MOSFET that has a high threshold voltage and is always in an off state. for example,
In Figure 1E, Q ₁₀₀ is P channel type
It uses MOSFET, and _Q100 is N-channel type.
Shows MOSFET.

Therefore, the address buffer circuit for address signal A ₀ consists of P-channel MOSFETs Q ₁₀₀ to Q ₁₀₇ and N-channel MOSFETs Q ₁₀₃ to Q 107.
It is composed of Q ₁₁₅ .

Further, like the address buffer circuit, the exclusive OR circuit and the OR circuit are also comprised of stake type circuits.

Although not particularly limited, the above-mentioned OR circuit is constituted by a CMOS circuit as shown in FIG. 1F. i.e. MOSFETQ ₁₁₆ or
A static type OR circuit is constructed by _Q129 .

The timing generation circuit shown in FIG. 1B consists of two pulse width expansion circuits constructed of static type circuits and an internal timing signal generation _circuit . Forms various timing signals necessary to operate the ROM. In the figure, only the main timing signals for operating the ROM are shown to simplify the explanation. In addition, among the main timing signals mentioned above, timing signals φ _XS , φ _PCS , φ _X , φ _PC , φ _PA1 ,
The waveforms of φ _PA2 , φ _la , φ _S and φ _HZ are shown. In the figure, the precharge signal _PC and timing signal _S are omitted to simplify the drawing, but these timing signals _PC and _S are
The timing signals φ _PC and φ _S are signals whose phases are inverted, respectively.

Among the two pulse width expansion circuits mentioned above, one pulse expansion circuit has a precharge pulse _PC ,
The timing signal φ _PC whose phase is inverted with respect to it
A reference signal φ _PCS necessary for generating the various timing signals described above is generated from the internal timing signal generation circuit. This reference signal φ _PCS
is a signal in which the pulse width of the edge trigger pulse φ _apd is expanded by this pulse width expansion circuit, and is adjusted to a certain predetermined pulse width. In addition, the timing signal φ _PC is the reference signal φ _PCS .
This is a signal that falls in synchronization with the fall of . Therefore, the precharge signal _PC rises in synchronization with the fall of the reference signal φ _PCS . The precharging of the data lines of the memory array and the precharging of the sense amplifiers described above are performed when the precharge signal _PC is at a low level. Therefore, the precharge time is defined by the signal formed by extending the pulse width of the edge trigger pulse φ _apd . This pulse width expansion operation can be realized, for example, by a combination of a delay circuit and a logic gate circuit.

The other pulse width expansion circuit forms a word line selection timing signal _{φ X} and _a reference signal φ do. _{This reference} signal _φ
The pulse width is adjusted to the time required to raise the word line to the memory cell selection level.

The _internal timing signal generation _circuit receives _the two reference signals _{φ PCS and φ} These timing signals will be used in the following description, so the function of these timing signals will become clear later in the description.

In this way, by forming the timing signals important for operating the ROM in separate pulse width expansion circuits, it is possible to set the important timing signals separately, which simplifies the design and improves the following: There are advantages as described in .

In other words, the reference signal φ _PCS , which specifies the precharge period from separate pulse width expansion circuits, and the reference signal _φ Since the signal is supplied to the signal generation circuit, if the read timing is determined based on these two reference signals, accurate readout can always be performed without malfunction. In other words, the generation timing of the timing signal necessary for the read operation, for example, the timing signal φ _PA1 for activating the sense amplifier, is determined based on the reference signal that falls slowly between the two reference signals mentioned above. If you do that,
By the time the timing signal φ _PA1 is generated, precharging has finished and the word line is
This means that the voltage has risen to the memory cell selection level. Therefore, if the sense amplifier is operated at this point, accurate information can be read from the desired memory cell. Moreover, which reference signal falls later can be detected by a relatively simple logic circuit.

Although not particularly limited, in this example,
In order to reduce power consumption, the precharge signal _PC is activated by the timing signal φ _o synchronized with the timing signal φ _PA1 for activating the sense amplifier.
The fall of the current is now controlled. That is, precharging to the data line, sense amplifier, etc. is started at the point when the amplification of information from the memory cell is completed. For example, after amplifying information from a memory cell with a sense amplifier,
If precharging is not performed, the charges in the stray capacitance of the data line connected to unselected memory cells will leak over time. A relatively large amount of power is required to precharge the discharged stray capacitance of the data line again. Therefore, in this embodiment, after the sense amplifier amplifies the information in the memory cell as described above, the stray capacitance (parasitic capacitance) of the data line is immediately precharged.

In addition, as will be explained in detail later, in this embodiment, in order to reduce the power consumption of the ROM, after the information of the memory cell is transmitted to the data line, the level of the word line is set to the non-select level of the memory cell. It is meant to be. Specifically, as shown in FIG. 1B, the word line selection timing signal _φ
It is configured to be outputted via a gate circuit controlled by a signal _φPA1 for activating the sense amplifier. By doing so, when the sense amplifier starts operating, the levels of all word lines are set to the non-selection level of memory cells.

FIG. 2A shows a circuit diagram of a specific embodiment of the memory array and sense amplifier.

Although not particularly limited, in this embodiment, each circuit is constituted by a CMOS circuit, as shown in FIG. 2A.

FIG. 2A shows, for example, a memory array M-
A specific circuit diagram of a memory array arranged on the right side of the sense amplifier is shown as ARY ₃ and M-ARY ₄ . Therefore, vertically W ₅₁₂ or
512 word lines of W ₁₀₂₃ are formed and are commonly used for the above memory arrays M-ARY ₃ and M-ARY ₄ . On the other hand, for the left memory array indicated by the black box, W ₀ to
512 word lines of W ₅₁₁ are formed.

Further, in the figure, ground lines G and data lines DL are alternately arranged in the horizontal direction in the memory array. Although not particularly limited, the ground line G ₀ is formed in the first line, and the data line DL ₀ is formed in the second line. Below, similarly, the ground wire G ₁ and the data line
As in DL ₁ , the ground wire and data wire are arranged alternately.

Memory MOSFETM ₀ to _{M 6} and the like are formed at the intersections of the word lines and data lines, respectively.

That is, the storage MOSFET is of an n-channel type, and its gate is connected to a corresponding word line, its drain is connected to a corresponding data line, and its source is connected to a corresponding ground line. Therefore, except for the ground wire G ₀ at the end,
For example, for one data line DL ₀ and ground line G ₁ ,
The drains and sources of different storage MOFETM ₀ , M ₁ and M ₁ , M ₂ are commonly connected to the same word line W ₅₁₂ . Although not particularly limited, these ground wires and data wires may be used for storage purposes.
A highly integrated array is realized by using semiconductor regions that are integrally formed with the semiconductor regions that constitute the source and drain of the MOSFET.

The eight data lines DL ₀ to DL ₇ listed above form a p-channel that constitutes a column switch.
It is shared through MOSFETS ₀ to S ₁₁ and connected to one input terminal of sense amplifier SA ₀ . The column switch above selects four data lines.
It is composed of a series circuit of MOSFETS ₈ to _S11 and MOSFETS ₀ to _S7 that select two data lines for each. For example, when MOSFETS ₈ and _S0 are turned on, data line _DL0 is selected. In this way, the column switch has a column address decoding function.

In addition, each ground line and data line is connected to a p-channel MOSFETP ₀ , which is shown as a representative for receiving the precharge signal _PS described in FIGS. 1B and 1D.
_P8 is provided between the power supply voltage V CC and the power supply voltage V _CC . Discharge n-channel MOSFETDs ₀ to _D4 are provided between each of the representative ground lines _G0 to _G4 and the ground potential, respectively. 1/8 selection signals φ _SO to φ _S7 according to the column address are applied to the gates of these MOSFETDs ₀ to D ₄ in synchronization with the timing signal φ _S shown in FIG. 1D. That is, when the timing signal φ _S is at a high level, 1/8 selection signals S ₀ to S ₇ are applied to each discharge N-channel MOSFET. As a result, one discharge MOSFET is selected from among the discharge MOSFETs TDn in each pre-charge/discharge group PDSi and turned on, and the other discharge MOSFETs are turned on.
The MOSFET is left off.

Now, select data line DL ₀ , turn on MOSFETD ₀ and select ground ground G ₀ , then the memory
The row with MOSFETM ₀ is selected. Above MOSFETD ₀
When _D1 is turned on instead, the row of storage _MOSFETM1 is selected for data line _DL0 .

In addition, two MOSFETs constituting a dummy cell are connected between the data line DL and the corresponding ground line.
are arranged in series.

That is, looking at the data line DL ₀ , dummy MOSFETs _{DC 01 and} DC ₀₂ are provided for the ground line G 0, and dummy MOSFETs DC ₀₃ and DC ₀₄ are provided for the ground line G ₁ , respectively. Further, a high threshold voltage MOSFET is provided in parallel to each dummy MOSFET.

This allows the MOSFET connected to the word line to
and the number of MOSFETs connected to the dummy word line.
The total number of can be made equal. By doing so, the word line and the dummy word line have the same load capacitance, and the rise to the selection level is made equal.

The series form that constitutes the above dummy cell
MOSFETDC ₀₁ , DC ₀₂ , etc. are for memory respectively.
It is composed of a MOSFET of the same size as the MOSFET, and is formed to turn on when selected. Therefore, the combined conductance of the selected dummy MOSFET is approximately 1/2 of the conductance of the storage MOSFET that is turned on when selected.

On the other hand, when information that causes the selected storage MOSFET to turn off is written, the composite conductance of the dummy MOSFET becomes larger than that of the selected storage MOSFET.

Note that the discharge MOSFETDs ₀ to _D4 and the like prohibit discharge of unselected data lines to prevent wasteful current consumption. The sizes of these MOSFETDs ₀ to _D4 , etc. are set so that the conductance when they are in the on state is sufficiently larger than that of the storage MOSFET in the on state.

Therefore, the discharge time constant of the data line is determined approximately according to the conductance of the storage MOSFET and the dummy MOSFET.

In addition, the above MOSFET that constitutes the dummy cell is
Since it can be formed at the same time as the memory MOSFET, there is no additional manufacturing process. Moreover, by forming them at the same time, if the characteristics of the storage MOSFET, such as conductance, change due to, for example, variations in manufacturing conditions, a similar change in characteristics occurs in the dummy MOSFET. Therefore, the combined conductance of the dummy MOSFET can be made approximately half the conductance of the storage MOSFET that is selectively turned on, without being affected by variations in manufacturing conditions. Therefore, memories with high yield can be manufactured.

Next, a method for selecting dummy cells will be described.
To select a dummy cell, as described above, the most significant address signal _A9 of the row-related address signals and the lowest address signal of the column address signals used when forming the selection signals φ _S0 to φ _S7 are used.
A ₁₀ is used. That is, the highest address signal
_A9 is used to determine which dummy cell is selected from the left or right memory array. and,
The lowest address signal _A10 is for the data line.
It is used to decide whether to select the upper dummy cell or the lower dummy cell relative to the data line. Note that this lowest address signal
_A10 is used to turn on the discharge MOSFET connected to the upper ground line with respect to the data line, or to turn on the discharge MOSFET connected to the lower ground line with respect to the data line in the selection signals φ _S0 to φ _S7 . This is an address signal that determines whether to turn on the discharge MOSFET coupled to the

Actually, by decoding the above two address signals and the word line selection timing signal φ _X , four types of dummy word line drive signals φ _a0 ,
Form φ _a1 , _a0 , _a1 . For example, when extracting memory cell information from the right memory array to the sense amplifier, a corresponding dummy cell is selected from the left memory array using the drive signal, and a reference voltage is supplied to the sense amplifier. do.

Note that writing of information to the storage MOSFET is performed depending on whether or not ion implantation is performed into the region where the channel of the storage MOSFET is formed, although there is no particular restriction. For example, depending on whether or not impurity ions of the opposite conductivity type are implanted into the channel type of the memory MOSFET, a binary signal of "1" or "0" can be written to the memory MOSFET. . In this case, the memory MOSFET is
The state in which the threshold voltage of
The state in which the threshold voltage of the MOSFET is held at a low value corresponds to "0" of the binary signal.

In a read operation, when a storage MOSFET is selected, the voltage applied between its gate and source determines whether the storage MOSFET is turned on or not.
This is done by detecting whether it is turned off or off. In other words, for selected storage
A read operation is performed by detecting whether the conductance of the MOSFET is large or small. A reference for performing this magnitude detection is formed by the dummy cell.

The memory cell group MC ₀ , the dummy cell group DC ₀ , the column switch CW ₀ , and the precharge/discharge switch group PGS ₀ provided in connection with the eight data lines are considered to be one set. Compatible with sense amplifier SA ₀ and main amplifier MA ₀ . Therefore, each memory array M−ARY ₀
M-ARY ₄ is provided with the above-mentioned 19 sets of arrays, 19 sense amplifiers, and main amplifiers.

The sense amplifier _SA0 is constituted by a dynamic differential amplifier circuit that receives read signals from the corresponding data lines of the left and right memory arrays.

Two CMOS consisting of p-channel MOSFETQ ₁ (Q ₂ ) and n-channel MOSFET _{Q 3} (Q ₄ )
A latch circuit is constituted by the inverter, and by providing an n-channel MOSFET _Q6 as a power switch on the ground potential side, a dynamic type circuit is formed. Also, to help pre-charge from this sense amplifier side to the data line,
A p-channel MOSFET Q ₅ is provided between the common electrode of the MOSFETs _{Q 3} and Q ₄ that serves as a source in a normal operating state and the power supply voltage V _CC . the above
A timing signal φ _PA1 for activating the sense amplifier is commonly applied to the gates of MOSFETQ ₅ and Q ₆ .

A p-channel MOSFET _Q7 for equalizing the precharge level is provided between both input and output terminals of the sense amplifier _SA0 , and the precharge signal _PC is applied to its gate.

The amplified output signal of the sense amplifier SA ₀ is transmitted to the input/output terminal of the main amplifier MA ₀ through n-channel transmission gate MOSFETs _{Q 8} and Q ₉ controlled by the timing signal φ _PA2 . The pair of input and output terminals of this main amplifier MA ₀ has p
A pre-charge MOSFET consisting of channel MOSFETs Q ₁₀ and Q ₁₁ , and a p-channel similar to the above to equalize the pre-charge level of both.
MOSFETQ ₁₂ is provided. these
The above-mentioned timing signal _S is applied to the gates of _MOSFETQ10 to _Q12 .

This main amplifier MA ₀ is also the above sense amplifier
It is composed of MOSFETQ ₁₃ to Q ₁₃ similar to SA ₀ , and one output signal, that is, node NB ₀
The output signal is passed through an inverter composed of a p-channel MOSFETQ ₁₉ and an n-channel MOSFETQ ₂₀ to form an output signal _BL0 . n channel provided on the ground side of this inverter
The timing signal φ _la described above is applied to the gate of MOSFETQ ₂₁ and the gate of MOSFETQ ₁₈ that controls activation of the differential circuit. While the timing signal φ _la is at a high level, the differential circuit amplifies and latches the signal sent from the sense amplifier. That is, a static output signal _BL0 is output from the sense amplifier _MA0 .

Note that in the main amplifier, the p-channel MOSFETQ ₁₇ functions similarly to the MOSFETQ ₅ in the sense amplifier described above. That is, when precharging the sense amplifier etc., the timing signal _S is set to low level. Therefore, at this time, MOSFETQ ₁₇ is turned on, and precharging from this MOSFET to the main amplifier etc. is also performed, thereby increasing the speed of precharging.

Further, when precharging the main amplifier, the timing signal φ _la is set to a low level. Therefore, the MOSFETQ ₂₁ is turned off. Also, due to precharge, node NB ₀
MOSFETQ ₁₉ is also turned off because it becomes high level. For this reason, before the main amplifier is precharged, the level of the output signal BL ₀ output from the inverter is affected by the stray capacitance (parasitic capacitance) of this output signal line and the stray capacitance (parasitic capacitance) of MOSFETs Q ₁₉ and Q ₂₀ . will be held.
Therefore, even when the main amplifier is precharged, the inverter outputs the output signal before being precharged.

The read output signal BL _o outputted from each of the main amplifiers is supplied to an inverter IV as shown in FIG. 2C, and the output signal BL o is
_o ′ whose phase is inverted with respect to BL _o and a signal D _o ′ corresponding to the above output signal BL _o are output to the next stage.
Supplied to the ECC circuit. In addition, this inverter
As IV, for example, a static type inverter constructed from a CMOS circuit as shown in FIG. 1G is used.

FIG. 3 shows a specific circuit diagram of one embodiment of the X decoder.

In this embodiment, in order to select one word line, the selection signal is formed in three stages. The reason why we divided this into three stages is that the first
The second objective is to prevent unnecessary blank areas from occurring within the IC chip. That is, a large number of MOSFETs
The purpose is to match the horizontal pitch of the NAND gates, which have a relatively large area due to their structure, to the word line pitch of the memory array. The second objective is to reduce the load on one address signal line and improve its switching speed.

Therefore, the upper address signals a ₄ , ₄ and a ₉ ,
p-channel MOSFET receiving a ₉ Q ₃₀ to Q ₃₅
and n-channel MOSFETs _Q36 to _Q41 to form eight word line selection signals. Then, p-channel MOSFETs Q ₄₂ and Q receive 1/4 selection decode signals a ₀₀ to a ₁₁ formed by the middle 2-bit address signals a ₂ and a ₃ and a signal obtained by inverting the above decode output with an inverter IV ₁ . ₄₃ and n-channel MOSFETs Q ₄₄ and Q ₄₅ form four word line selection signals. These four word line selection signals are connected to an inverter-type p channel.
These signals are applied to the gate inputs of a word line drive circuit consisting of MOSFETQ ₄₆ and n-channel MOSFETQ ₄₇ , respectively.

In addition, the lower two bits of the address signals a ₀ , a ₁ and
Four word line selection timing signals φ _{W00 to} φ _W11 , which are generated in synchronization with the word line selection timing signal _φ

Therefore, when address signals _a0 to _a9 are all " ₀ ", in other words, when all address signals a0 to _a9 are "1", word line selection timing signal _φ
The word line _W0 can be raised to a high level in synchronization with the word line W0.

In addition, each word line may include, but is not particularly limited to,
N channel for setting the potential of unselected word lines on the opposite side to the driver to the circuit ground potential
A word line selection timing signal φ _wiJ (1=0, 1, j=0,
A signal whose phase is inverted with respect to 1) is supplied.
For example, the word line W ₀ to which the drive circuit DV ₀ is coupled
is coupled to MOSFETQ ₁₇₀ to which timing signal ₀₀ is applied to its gate. By doing this, the unselected word line, e.g.
Since the potential of W ₃ is set to the ground potential by MOSFETs _{Q 48} and Q ₁₇₃ , multiple selection of word lines can be prevented. Note that the signal whose phase is inverted with respect to the timing signal φ _wij can be easily obtained by, for example, inverting the phase of the timing signal φ _wij using an inverter.

FIG. 4 shows a circuit diagram of one embodiment of a _Y1 decoder for selecting column switches.

The decoder of this embodiment generates decode signals y ₀₀ to y ₁₁ that select MOSFETS ₈ to S ₁₁ of column switch CW ₀ shown in FIG. 2A.

P-channel MOSFETQ ₅₁ in parallel configuration,
Q ₅₂ and n-channel in series configuration
MOSFETs Q ₅₃ and Q ₅₄ constitute a two-input NAND gate, and address signals ₁₂ and ₁₃ are applied to its inputs, for example, when forming the decode signal y ₀₀ described above. The above parallel form
p channel in series with MOSFETQ ₅₁ , Q ₅₂
MOSFETQ ₅₀ is provided, and an n-channel MOSFETQ ₅₂ is provided in parallel to MOSFETQ ₅₃ and Q ₅₄ which are in series configuration.
A timing signal φ _PC shown in FIG. 1D is applied to the gates of MOSFETs Q ₅₀ and Q ₅₂ .

The output of the above logic gate is connected to the inverter IV ₂ ,
The decoded signal y ₀₀ is obtained through IV ₃ .

MOSFETS ₀ to above column switch CW ₀
Regarding the decoded signals y ₀ and y ₁ that select S ₇ , 1
It is formed by a decoder similar to the above using the bit Y address signal and the timing signal φ _PC .

Therefore, regardless of the Y address signal, during the precharge period, the timing signal φ _PC becomes high level, and all of its decoded outputs become low level. This allows the p-channel
All column switches composed of MOSFETs are turned on. Therefore, in FIG. 2A, the precharge to the data line DL is caused by the precharge caused by turning on the precharge MOSFETP ₀ to P3 _, etc., as well as by the n channel of the sense amplifier _SA0 which is turned on by this precharge operation.
With MOSFETQ ₃ and Q ₄ turned on, p channel
By turning on MOSFETQ ₅ , the sense amplifier side also precharges the data line DL, thereby shortening the precharge period.

FIG. 5 shows a schematic diagram of one embodiment of the ECC circuit in FIG. 1A.

The logic operation circuit receives the 38-bit read signals D ₀ ′, ₀ ′ to D ₃₇ ′, ₃₇ ′ from the ROM, and uses the exclusive OR of a predetermined combination to generate syndromes S ₀ to S that designate error bits. form ₅ .
For example, the above combination of exclusive ORs is determined based on a test matrix as shown in FIG. 6, and the parity bit of write data W is determined.
BP ₀ to BP ₅ are determined.

For example, the data bits of the write data W
B ₀ to B ₃₁ are “1” and “0” as shown in the same figure.
When writing the parity bit BP ₀ , focus on the syndrome S ₀ of the above inspection matrix,
Exclusive OR is performed between the above write data corresponding to the bit set to “1” in that line,
The value of parity bit _BP0 is determined so that this exclusive OR becomes "0". In the above data, exclusive OR is performed between data bits B ₀ to B ₄ , B ₁₄ to B ₂₁ and B ₂₈ to B ₂₉ .
In this case, since this exclusive OR is "1", the parity bit _BP0 is set to "1" so that the exclusive OR of the data bit and this parity bit becomes "0".

Below, in the same way, for the rows of syndromes S ₁ to S ₅ , so that the exclusive OR becomes "0",
Parity bits BP ₁ to BP ₁ are determined.

In this data example, the parity bits BP ₀ to BP ₅ determined as described above are all "1" as shown in the figure.

The logical formulas for determining the syndromes S ₀ to S ₅ are as shown in the following formulas (1) to (6).

S ₀ =B ₀ B ₁ B ₂ B ₃ B ₄ B ₁₄ B ₁₅ B ₁₆ B ₁₇
B ₁₈ B ₁₉ B ₂₀ B ₂₁ B ₂₈ B ₂₉ BP ₀ ……(1) S ₁ =B ₀ B ₅ B ₆ B ₇ B ₈ B ₁₄ B ₁₅ B ₁₆ B ₁₇
B ₂₂ B ₂₃ B ₂₄ B ₂₅ B ₃₀ BP ₁ ……(2) S ₂ =B ₁ B ₅ B ₉ B ₁₀ B ₁₁ B ₁₄ B ₁₈ B ₁₉
B ₂₂ B ₂₃ B ₂₆ B ₂₇ B ₂₈ B ₃₀ B ₃₁ BP ₂
...(3) S ₃ = B ₂ B ₆ B ₉ B ₁₂ B ₁₃ B ₁₅ B ₁₆ B ₂₀
B ₂₁ B ₂₂ B ₂₄ B ₂₆ B ₂₇ BP ₃ ……(4) S ₄ =B ₃ B ₇ B ₁₀ B ₁₂ B ₁₆ B ₁₉ B ₂₀ B ₂₃
B ₂₅ B ₂₆ B ₂₉ B ₃₁ BP ₄ ……(5) S ₅ =B ₄ B ₈ B ₁₁ B ₁₃ B ₁₇ B ₂₁ B ₂₄ B ₂₅
B ₂₇ B ₂₈ B ₂₉ B ₃₀ B ₃₁ BP ₅ ...(6) In these logical formulas, the mark indicates exclusive OR.

In the mask type ROM of the embodiment shown in FIG. 1A, 38 bits consisting of the data bits _B0 to _B31 and the parity bits _BP0 to _BP5 are as follows:
38 memories selected by a set of address signals A ₀ to A ₁₄
Written to MOSFET. That is, one Y
38 memory MOSFETs (memory cells) selected by the decode signal and two Y decode signals
The above 38 bits are written to each. For example, for each group that makes up the left memory array,
One bit of the above 38 bits is allocated and written. Although not particularly limited, data bits B ₀ to B ₁₈ of the above data are written to the memory array M-ARY ₁ .
- In ARY ₂ , data bits B ₁₉ to B ₃₁ and parity bits BP ₀ to BP ₅ are written.

In this way, after writing the write data W as shown in FIG. 6 into the memory array, when the write data W is read out to the ECC circuit, the data becomes, for example, the read data as shown in the same figure. If the data is incorrect as shown in R, that is, when data W is written and read, the 7th digit bit _B7 changes from “0” to “1”.
, the logical operation circuit in the ECC circuit calculates the above equation (1) or based on this data R.
Logical operations are performed on the syndromes S ₀ to S ₅ according to (6). In the calculation process for calculating syndromes S ₀ to S ₅ , the seventh digit bit B ₇ is taken in during the logical calculation for calculating syndromes S ₁ and S ₄ . As mentioned above, the 7th digit bit B ₇
changes from "0" to "1", the syndromes S ₁ and S ₄ each become "1". Regarding the other syndromes S ₀ , S ₂ , S ₃ and S ₅ , there are no errors in the bits taken in during the calculation process to obtain them, so this syndrome
S ₀ , S ₂ , S ₃ and S ₅ are each “0”.

Therefore, the bit pattern of syndromes _S5 to _S0 output from the logical operation circuit is “010010”.
becomes. This bit pattern corresponds to bit D ₇ in the 7th digit in the inspection matrix shown in FIG.
matches the bit pattern of syndrome S ₅ to S ₀ that indicates That is, looking at the bit _D7 column in the above inspection matrix, the pattern for syndromes _S5 to _S0 is "010010", and the bits for syndromes _S5 to _S0 output from the logic operation circuit are matches the pattern. However, in this case, blank columns in the inspection matrix are set to "0".

In other words, the bit patterns of syndromes _S5 to _S0 output from the logic operation circuit indicate the digits of the erroneous data bits included in the data supplied thereto.

The syndromes output from the logic operation circuit and syndromes ₀ to ₅ inverted by the inverter are input to a decoder DCR which converts them into the number of error digits.

The decoder DCR is composed of AND gates _G0 to _G31 , and when each output is "1", it indicates an erroneous digit. These AND gates G ₀ to G ₃₁ and the information bits B ₀ to B ₃₁ of the read data R are input to exclusive OR circuits EXOR ₀ to EXOR ₃₁ , respectively, and the output data D ₀ to B 31 are transmitted to the multiplexer. Form D ₃₁ . As mentioned above, if there is an error in the 7th digit,
Since the output of AND gate G ₇ becomes "1", the signal of the 7th digit which was incorrectly read as "1" is inverted from "1" to "0" by EXOR ₇ and becomes correct. The information will be corrected.

Note that the ECC circuit of this embodiment can correct a 1-bit error, but cannot correct an error of 2 or more bits. For example 2
such as being able to correct bit errors.
In the ECC circuit, its configuration is complicated,
The number of elements also increases. Also, in this case, the number of parity bits (redundant bits) must be significantly increased.

FIG. 7 shows a specific embodiment of the edge trigger or the logic operation circuit and the exclusive OR circuit used for error correction.

In this example, p-channel MOSFETQ _P1
or Q _P4 and n-channel MOSFETQ _o1 or
It consists of Q _o4 . Above MOSFETQ _P1 , Q _P2
and MOSFETQ _o1 and Q _o2 are in series form, and the above
Q _P3 , Q _P4 and MOSFETs Q _o3 and Q _o4 are connected in series.

The connection point of MOSFETQ _P2 and Q _o1 above and
The connection point of MOSFETQ _P4 and Q _o3 is commonly connected and output
Form OUT. Input signals a and b are applied to the gates of the MOSFETs _{Q o1} and Q _o2 , respectively, and input signals are applied to the gates of the MOSFETs Q _o3 and Q _o4 , respectively.

In addition, the gates of MOSFETQ _P1 and Q _P4 above are
The input signal, respectively, is applied and the above
Input signals b and a are applied to the gates of MOSFETs Q _P2 and Q _P3 , respectively.

Now, input signals a and b are both high level (“1”)
When , MOSFETs Q _o1 and Q _o2 are turned on and the output OUT is set to low level (“0”). Conversely, when both input signals are at high level,
MOSFETQ _o3 and Q _o4 are turned on and the output OUT is similarly set to low level.

Then, when input signal a (or) is low level and input signal b (or b) is low level,
MOSFETQ _P3 (or Q _P1 ) and MOSFETQ _P4 (or
Q _P2 ) turns on and makes the output OUT high level. In this way, when the levels of the input signals a and b match, the output OUT is set to the low level, and when they do not match, the output OUT is set to the high level, so that an exclusive OR operation is performed.

This embodiment has the advantage of extremely low power consumption because the number of elements is as small as eight, and no direct current flows between the power supply voltage V _CC and the ground potential.

In the logic operation circuit in the above ECC circuit,
In order to form the syndromes S ₀ to S ₅ , logical operations as shown in the above-mentioned logical formulas (1) to (6) are performed inside the syndromes. That is, a large number of exclusive OR operations are performed within the logical operation circuit.

Therefore, by using an exclusive OR circuit as shown in FIG. 7 as a logic circuit that performs this exclusive OR operation, it is possible to configure the above logic operation circuit with a relatively small number of elements. At the same time, the power consumption in this logic operation circuit can be made relatively small.

In addition, in FIG. 2A, when writing information to the right memory array, if inverted information is written to the left memory array, the read data from the sense amplifier and main amplifier will be changed to the left, In either reading on the right side, the positive phase output BL _o ( _o ') can always be obtained.

FIG. 8 shows how the potentials V _D and _D of the selected pair of data lines of the memory array change over time.

In the figure, a broken line indicates a change in potential of a data line connected to a dummy cell. In addition, the one-dot chain line shows the potential change of the data line when information "0" is written in the storage MOSFET, and the two-dot chain line shows the change in the potential of the data line when information "1" is written in the storage MOSFET. It shows the potential change of the data line at the time.

The sense amplifier amplifies the voltage difference between the pair of data lines and transmits it to the main amplifier.

In this case, as described above, since the above-mentioned discharge is not performed on the data line for which the ground line is not selected, the pre-charge level is maintained and the generation of invalid current consumption is prevented. be able to.

FIG. 9 shows a specific circuit of an embodiment of an output multiplexer and an output buffer.

The output signals D ₀ to D ₃₁ from the ECC circuit are transmitted 8 bits at a time to the output buffer by the following multiplexer.

To explain the data D ₀ shown as a representative, this data D ₀ is passed through the inverter IV ₄ ,
p-channel MOSFETQ ₅₅ and n-channel
Sent to the gate of MOSFETQ ₅₈ . the above
The drain outputs of MOSFETQ ₅₅ and Q ₅₈ are p-channel MOSFETQ ₅₆ and n-channel respectively.
Connected to the output line through MOSFETQ ₅₇ .

Timing signals φ ₀₀ to φ ₁₁ are formed by an address buffer and a Y ₂ decoder as shown in FIG. 10, although not particularly limited thereto. The address buffer consists of two unit buffers AD ₁ and AD ₂ , and each unit buffer has the same configuration, so the figure shows a specific circuit only for unit buffer AD ₁ . . The unit buffer AD ₁ is composed of a static type circuit.
That is, MOSFETQ ₁₃₆ to Q ₁₆₃ constitute unit buffer AD ₁ . The _Y2 decoder also consists of four unit decoders _YU1 to _YU4 , each of which has the same configuration. Therefore, only the single decoder _YU1 is shown in the figure. The unit decoder YU ₁ is composed of MOSFETs _{Q 164} to Q ₁₆₉ , and unlike the X decoder shown in FIG. 3, it has a circuit configuration that does not require a special timing signal. For this reason, the above Y ₂
The decoder can form the timing signals φ ₀₀ to φ ₁₁ using only the address signals supplied from the address buffer.

The above _Y2 decoder uses address signals _a15 , ₁₅ ,
A ₁₆ and ₁₆ are received to form a 1/4 selection signal.

Now, if the Y address signals a ₁₅ and a ₁₆ are both "0", the timing signal φ ₀₀ becomes high level. This signal φ ₀₀ is the n channel in FIG.
It is inverted through MOSFETQ ₅₇ and inverter IV ₅ and applied to the gate of p-channel MOSFETQ ₅₆ .

Therefore, when the timing signal φ ₀₀ is at high level, these MOSFETs Q ₅₆ and Q ₅₇ are both turned on, so the data D ₀ is transmitted to the output line,
When the above timing signal φ ₀₀ is low level, the above
Since MOSFETQ ₅₅ and Q ₅₇ are both turned off, they become high impedance regardless of the data D ₀ mentioned above.

A set of eight circuits similar to those described above which receive 8-bit signals from data _D0 to _D7 is controlled by the timing signal _φ00 .

Then, for the remaining data signals, the data
Each of 8 bits, such as D ₈ to _{D 15} , D ₁₆ to D ₂₃ and D ₂₄ to D ₃₁ , is constructed by a circuit similar to the above, and is controlled by the remaining timing signals φ ₀₁ to φ ₁₁ .
The above four sets of output lines are connected to the corresponding bits.
Data of every 8 bits such as D ₀ , D ₈ , D ₁₆ , and D ₂₄ are shared. Therefore, the total number of output lines is eight.

The output buffer consists of eight output circuits provided according to the output lines, one of which is shown as a representative.

This output buffer is MOSFET Q ₅₉ to Q ₆₆
Two sets of 2-input NAND gates consisting of 4
one inverter IV ₆ to IV ₉ and n-channel
It consists of a push-pull output circuit consisting of MOSFETQ ₆₇ and Q ₆₈ .

That is, the output signal of inverter IV ₆ receiving the signal from the output line of the multiplexer is:
Applied to one input of a NAND gate consisting of _MOSFETQ59 to _Q62 . In addition, the output signal of inverter IV ₇ , which receives the output signal of inverter IV ₆ , is composed of MOSFETs Q ₆₃ to Q ₆₆ .
Applied to one input of the NAND gate. The timing signal φ _HZ is applied to the other input of these two sets of NAND gates.
The output signals of the above two NAND gates are passed through inverters IV ₈ and IV ₉ to the output MOSFETs Q _{67 and 67} , respectively.
Reported to the gate of Q ₆₈ .

_The above-mentioned timing signal φ _HZ is formed by, for example, the reference signals _{φ PCS} and _φ When the output signal of the ECC circuit becomes undefined due to the output of new data from the main amplifier to the ECC circuit, the timing signal φ _HZ is set to a low level. By setting this timing signal _φHZ to low level, the output MOSFETQ ₆₇ ,
Q ₆₈ is turned off. Therefore, the external output terminal D _o (n=0 to 7) becomes high impedance. This allows the semiconductor memory device of this embodiment to be connected to a common data bus type system, and also prevents output of undefined data.

Next, the operation of this embodiment will be briefly explained with reference to the waveform diagram shown in FIG. 1D.

First, address signals A ₀ to A ₁₄ are changed to read information from the desired memory cell. Then, an edge trigger pulse φ _apd is generated from the edge trigger.

One pulse width expansion circuit receives this edge trigger pulse φ _aPd and forms a reference signal φ _pcs that defines the precharge time of the data line, etc. In addition, in response to the falling edge trigger pulse φ _apd , the other pulse width expansion circuit generates a word line selection timing signal _φ A reference signal _φXS having a pulse width is formed. When the word line selection timing signal _φX rises,
The potentials of the word line connected to the desired memory cell and the corresponding dummy word line begin to rise.

When a predetermined time has elapsed since the address signal changed, that is, when the time required for precharging the data lines, sense amplifiers, etc. has elapsed, the reference signal φ _PCS falls. In response, the internal timing signal generation circuit raises the timing signal φ _S and lowers the timing signal φ _PC . When the timing signal φ _PC falls, precharging of the data line, sense amplifier, etc. is completed. On the other hand, the main amplifier starts to be precharged because the timing signal φ _S rises.

Further, the timing signal generation circuit lowers the timing signal φ _la to a low level following the rise of the timing signal φ _S to a high level. As a result, the main amplifier and the subsequent inverter, which had been activated until now, become inactive.
The main amplifier is unlatched.

Therefore, the node NB _o of the main amplifier changes from its previous output state to precharge.

In addition, since this timing signal φ _S rises, the discharge MOSFET of the ground line connected to the desired memory cell and the discharge MOSFET of the ground line connected to the dummy cell corresponding to this desired memory cell are turned on. Become. Furthermore, at this time, since the timing signal φ _PC falls, the column switch, which had connected all the data lines to the sense amplifier for precharging, connects the data line to which the desired memory cell is connected.
The corresponding dummy cell operates to couple only the coupled data line to the sense amplifier. Therefore, the information stored in the desired memory cell is transmitted to one input/output terminal of the sense amplifier as a change in the potential of the data line, and the reference voltage from the dummy cell is transmitted to the other input/output terminal of this sense amplifier. It becomes like this. That is, as shown in the figure, the potential of the data line DL _o connected to a desired memory cell changes according to the information stored in that memory cell.

Next, the reference signal _φXS falls. At this time, the potential of the word line connected to the desired memory cell is at the memory cell selection level.

In response to the falling of the reference signal φ _XS , the internal timing signal generation circuit generates the timing signal _φ
bring down. This completes precharging to the main amplifier.

The internal timing signal generation circuit raises a timing signal φ _PA1 for activating the sense amplifier in synchronization with the fall of this timing signal φ _S. As a result, the sense amplifier begins to amplify the potential difference between the data line to which the memory cell is coupled and the data line to which the dummy cell is coupled.

Further, the internal timing signal generation circuit lowers the word line selection signal _φX in synchronization with the rise of the timing signal _φPA1 . That is, the word line is set to a non-select level to reduce power consumption.

As mentioned above, when the sense amplifier starts operating, the potential of the data line DL _o connected to the desired memory cell changes greatly according to the information stored therein, as shown in the figure. .

When the potential difference between the pair of data lines is amplified to some extent by the sense amplifier, the internal timing signal generation circuit raises the timing signal φ _PA2 . Thereby, the output signal of the sense amplifier is transmitted to the main amplifier.

Following the rise of the timing signal φ _PA2 , the internal timing signal generation circuit raises the timing signal φ _la to high level again. The rise of this timing signal φ _la activates the main amplifier and inverter, amplifies and latches the output signal sent from the sense amplifier, and transmits it to the ECC circuit. Therefore, the level of the node NB _o of the main amplifier changes from the precharge level to the level according to the information of the desired memory cell. The inverter changes from the data held in the parasitic capacitance of its output node to output new data.

In addition, the ECC circuit outputs undefined data for a certain period of time, which is mainly determined by the time required for the inverter to output new data from old data, and the delay time of the ECC circuit itself.
New data that has been accurately corrected by the ECC circuit will be output.

While this ECC circuit is outputting undefined data, the timing signal φ _HZ is kept at a low level. As a result, the external output terminal is in a floating state during this time. After that, new data will be output from the external output terminal.

Furthermore, after the internal timing signal generation circuit lowers the timing signal _φPA1 to a low level,
Raise the timing signal φ _PC to high level again to start precharging the data line, sense amplifier, etc. again.

Note that the previous data is held by the inverter in the latter stage of the main amplifier after the main amplifier is deactivated until it is activated again by the timing signal φ _la . ,
The output signal D _o of the ECC circuit and the output signal DO _o from the external output terminal are the previous data.

Further, the fall of the timing signal φ _S to the low level is defined by either the reference signal φ _PCS or the reference signal φ _XS , whichever falls later. This is to ensure that the read operation is performed as described above.

Next, the relationship between the address signal and the output data DO _o (n=0 to 7) from the external output terminal will be described. In FIG. 11, address signals A ₀ to A ₁₆ and
The relationship with the output data line DO _o is shown.

When any one of the address signals _A0 to _A14 changes, 32-bit data is output from the ECC circuit, as described above.
Although not particularly limited, in this embodiment, the 32-bit data can be divided into four groups and taken out from the external output terminals in a time-division manner. i.e. address signals A ₁₅ and A ₁₆
Depending on the combination of , it is possible to decide which of the four sets to take out.

As shown in Figure 11, the address signal
When the combination of A ₁₅ and A ₁₆ is set to the state, 8-bit data indicated by DO() can be extracted from the external output terminal. Following this, if the combination of address signals A ₁₅ and A ₁₆ is set to the state, it follows this state for a short time.
The 8-bit data indicated by DO() can be extracted. Thereafter, the 8-bit data indicated by DO() and the 8-bit data indicated by DO() can be retrieved in a short time in the same manner.

In this way, in a short time, the data in DO(), DO
The reason why data in () and data in DO() can be retrieved is that when retrieving data DO(〇1), DO() or DO()
This is because the data reaches the output node of the ECC circuit.

According to this embodiment, the number of data bits is increased and the ratio occupied by the required number of validity bits is reduced, so that the actual capacity of the memory array can be increased. Since the output data of the ECC circuit is divided into several times and output in a time-sharing manner by the multiplexer, the number of output terminals does not increase. As a result, in a one-chip semiconductor memory device, the storage capacity of the memory array can be substantially increased, and defective bits can be repaired and read out efficiently.

and for storage to be read simultaneously from the memory array.
Since the MOSFETs are divided into blocks corresponding to sense amplifiers as described above, these storage MOSFETs are distributed on the semiconductor substrate. Therefore, even if there are defective memory cells that occur intensively over multiple bits on the semiconductor substrate, these are dispersed and read out during readout, so that the ECC of the 1-bit correction function is
Even if a circuit is used, these problems can be reliably relieved.

Furthermore, when the memory array and sense amplifier are configured as dynamic circuits, static read data and parity signals are supplied to the ECC circuit by providing a main amplifier. It can be simplified.

Furthermore, when a storage device is configured by combining a static type circuit and a dynamic circuit as in the above embodiment, it is possible to reduce power consumption and simplify external handling. Furthermore, by configuring the CMOS circuit, the power consumption of the static type circuit can be reduced, so that even higher power consumption can be achieved.

The invention is not limited to the above embodiments.

When incorporating an ECC circuit into a semiconductor memory device, the above-mentioned problems arise. Therefore, this invention solves the above problem.
It can be widely used in semiconductor memory devices with built-in ECC circuits, such as various semiconductor ROMs and semiconductor RAMs.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing one embodiment of the present invention, FIG. 1B is a block diagram showing one embodiment of the edge trigger and timing generation circuit, and FIG.
Figure C is a timing diagram for explaining the operation of the edge trigger, Figure 1D is a waveform diagram for explaining the operation of the edge trigger and timing generation circuit,
FIG. 1E is a circuit diagram showing one embodiment of the address buffer circuit, FIG. 1F is a circuit diagram showing one embodiment of the OR circuit, and FIG. 1G is a circuit diagram showing one embodiment of the inverter circuit. , FIG. 2A is a circuit diagram showing a specific example of a memory array and sense amplifier, FIG. 2B is a diagram showing circuit symbols of MOSFETs, and FIG. 2C is a logic diagram showing an example of an inverter circuit. Symbol diagram, FIG. 3 is a circuit diagram showing one embodiment of the X decoder, FIG. 4 is a circuit diagram showing one embodiment of the _Y1 decoder, and FIG. 5 is a schematic diagram showing one embodiment of the ECC circuit. 6 is a diagram of a check matrix and a bit pattern of write/read data showing one embodiment of the test matrix, FIG. 7 is a circuit diagram showing an embodiment of an exclusive OR circuit, and FIG. A timing diagram for explaining a read operation; FIG. 9 is a circuit diagram showing an embodiment of a multiplexer and an output buffer;
FIG. 10 is a circuit diagram showing one embodiment of the _Y2 decoder and address buffer circuit, and FIG. 11 is a timing diagram for explaining time-divisionally extracting output data.

Claims (1)

[Claims] 1. An address terminal that receives an address signal from the outside, D data output terminals (D is an integer, D>1) for outputting data to the outside, a ROM memory array, and an ECC circuit. In a semiconductor memory device including a sense amplifier and a decoder, the ECC circuit receives an m-bit data signal (m is an integer and a multiple of D, where the multiple is 2 or more) from the memory array and the m-bit data signal. corresponding n
The circuit is configured to receive a parity signal of bits (n is an integer, n>1) and perform error correction of at least more data than the number of data output terminals, and the error-corrected m A multiplexer that sequentially outputs bit data multiple times for each D bit based on an address signal that does not select a memory cell, and an output buffer that receives the output signal of the multiplexer and outputs the data. A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1, wherein the memory array is a dynamic memory array. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is constituted by a CMOS circuit.