JPH0793036B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a read-only semiconductor memory device, and more particularly to a large-capacity semiconductor memory device having a function of correcting error data.

[Technical background of the invention and its problems] As a rescue method for a small number of bits in a large-capacity read-only semiconductor memory device (hereinafter referred to as a ROM), an error detection / correction method using a code and a defective bit address have hitherto been used. Has been proposed and a method of correcting the output when this address is supplied, a method of providing a detection circuit in the row decoder and the column decoder to correct the output, and the like. However, in the error detection / correction method using the code, the number of memory cells for storing the code is required to be about 20% of the main cell, so that the chip size becomes large and the arithmetic circuit is operated every time data is output. Therefore, there is a drawback that the data access time is delayed. Further, in the method of detecting the defective bit address and correcting the output, it is necessary to program the same number of fuses as the address input terminals in order to save the defect of 1 bit, and it is completely effective for one row or column defect. It has the drawback of not having it. Furthermore, the method of providing a detection circuit in the row decoder and the column decoder to correct the output can save the defect in the same row or in the column, but can completely eliminate the defect in the random two bits or more. has no effect.

Recently, a ROM with a storage capacity of 1 Mbit has been developed,
In such an extremely large-capacity ROM, the yield reduction due to the crystal lattice defects of the semiconductor substrate and the like cannot be ignored, so it is considered that a rescue agent for a small number of bits is indispensable.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to repair a plurality of randomly generated defective bits without delaying the access time, and An object of the present invention is to provide a semiconductor memory device which can relatively reduce the increase in chip size when integrated into a circuit by adding a bit defect correction function.

[Summary of the Invention] A semiconductor memory device of the present invention includes a memory cell array including a plurality of memory cells arranged in rows and columns, a row decoder and a column decoder for selecting memory cells in the memory cell array, and the row decoder. A plurality of first defects connected to the output terminals of the decoder, programmable so that the corresponding rows of the memory cell array are defective, divided into a plurality of groups, and having the output terminals commonly connected within each group. The address detection circuit is connected to the output terminal of the column decoder, and it is programmable that the corresponding column of the memory cell array is defective, divided into a plurality of groups, and the output terminals are commonly connected in each group. A plurality of second defective address detection circuits, an output of a common output terminal of each group of the plurality of first defective address detection circuits, and a plurality of the second defective address detection circuits.
The output of the common output terminal of each group of the defective address detection circuit is supplied, and it is programmable that the memory cell corresponding to a specific row and column of the memory cell array is defective,
A detection circuit that detects that a defective memory cell corresponding to the particular row and column is selected, and read data from the memory cell selected by the row decoder and the column decoder according to the detection output of the detection circuit. A correction circuit for correction is provided.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit diagram showing the structure of the semiconductor memory device according to the present invention. Reference numeral 10 is a memory cell array in which a plurality of memory cells 11 composed of MOS transistors are arranged in a row direction and a column direction. The gate of each memory cell 11 in the memory cell array 10 has a plurality of row lines 12i (i = 1, 2
...), the drain is connected to the corresponding one of the plurality of column lines 13j (j = 1, 2, ...), and all the sources are connected to the reference potential Vss (ground). Has been done. The plurality of row lines 12 are adapted to be supplied with respective outputs of a plurality of decoding NOR gates 14 constituting a row decoder. And these noah gates
14 are divided into, for example, four groups, whereby the row decoder is divided into first to fourth row decoders 15 ₁ to 15 ₄ .

Column line selection MOS transistors 16 are inserted in the middle of the plurality of column lines 13, and one ends of these transistors 16 are commonly connected. Further, the gate of the MOS transistor 16 for selecting the column line is connected to the output terminals of the respective NOR gates 17 for decoding which form a column decoder, and a plurality of column line selecting lines 18k (k = 1, 2 ...) Are connected. The signal of the corresponding one is supplied. The NOR gate 17 is divided into, for example, four groups, whereby the column decoder is divided into first to fourth column decoders 19 ₁ to 19 ₄ . The common connection point 20 at one end of the transistor 16 is connected to the input terminal of the sense amplifier 21, and the output of the sense amplifier 21 is one input terminal of an exclusive OR circuit (exclusive OR) 22. Is supplied to. Further, the output of the exclusive OR circuit 22 is output as read data from the memory cell 11 via the output buffer 23.

A plurality of row-side defective address detection circuits 24 are connected to the tip ends of the row lines 12, respectively. Each of these defective address detection circuits 24 has an AND gate 25 whose one input terminal is connected to the corresponding row line 12, and this AND gate 25.
The load resistor 26 is inserted between the other input terminal of the other and the power supply potential Vcc, and the fuse 27 is inserted between the other input terminal and the ground. Further, these defective address detection circuits 24 are divided into _four defective address detection circuit groups 28 ₁ to 28 ₄ corresponding to the _{first to} fourth row decoders 15 ₁ to 15 ₄ and each defective address detection circuit The output terminals of the AND gates 25 in the group 28 are commonly connected.

A plurality of column-side defective address detection circuits 29 are connected to the ends of the column line selection lines 18, respectively. Each of these defective address detecting circuits 29 is constructed similarly to the row-side defective address detecting circuit 24, while the input terminal is connected to the corresponding column line selecting line 18 instead of the row line 12. These defective address detection circuits 29 are divided into _four defective address detection circuit groups 30 ₁ to 30 ₄ corresponding to the _{first to} fourth column decoders 19 ₁ to 19 ₄ , and each defective address detection circuit group 30 The output terminals of the AND gates 25 therein are commonly connected.

Group of four defective address detection circuits 28 ₁ to 2 on the row side
8 ₄ and the output of the four defective address detection circuit groups 30 ₁ to 30 ₄ on the column side are the four column group selection circuits 31 ₁ to 31 ₄
Is supplied to. These column group selection circuits 31 ₁ to 31 ₄
4 three-input AND gates 32 to 35, four fuses 36 to 39 and 4 as illustrated in one circuit 31 _1.
It consists of individual load resistors 40 to 43. The first input terminals of the AND gates 32 to 35 are connected to the respective other ends of the load resistors 40 to 43 whose one ends are connected to the power source potential Vcc, and at the same time, the one ends thereof are connected to the ground. The other ends of the fuses 37 to 39 are connected. The second defective input detection circuit 28 ₁ on the row side is connected to the second input terminals of the AND gates 32 to 35.
Outputs are fed in parallel. Further, the outputs of the first to fourth defective address detection circuits 30 ₁ to 30 ₄ on the column side are supplied to the third input terminals of the AND gates 32 to 35. The column group selection circuit 31 ₂ in the row side 1
The second output of the defective address detection circuit 28 _2, column group selection circuit 31 ₃ in the third defective address detection circuit 28 of the low-side ₃ instead of the row side of the output of the defective address detection circuit 28 ₁
Of the row-side fourth defective address detection circuit 28 _{4 in} the column group selection circuit 31 ₄ , respectively.
2 to 35 are supplied in parallel to the second input terminals. These four columns group selecting circuit 31 ₁ to output terminals of all the AND gates 32 to 35 in the 31 ₄ are connected to a common signal of the common connection point 44 and the other input terminal of the exclusive OR circuit 22 Is supplied to.

For example, one row line in such a structure 12 ₁ and one memory cell and the column line 13 ₁ is arranged at the intersection 1
If a bit defect occurs in ₁ , the fuse 27 in the defective address detection circuit 24 of the defective address detection circuit group 28 ₁ on the row side to which this row line 12 ₁ is connected and the column side to which this column line 13 ₁ is connected The fuse 27 in the defective address detection circuit 29 of the defective address detection circuit group 30 ₁ is disconnected. Further, in the column group selection circuit 31 ₁ , the defective address detection circuit group 28 ₁
The fuse 36 connected to the AND gate 32 to which the respective outputs of the defective address detection circuit group 30 ₁ are supplied is cut.

As a result, the defective cell is selected by the first row decoder 15 ₁ and the first column decoder 19 ₁ , and the memory cell 1
When data is read from 1, the outputs of the row-side defective address detection circuit group 28 ₁ and the column-side defective address detection circuit group 30 ₁ both become “1” level. In the AND gate 32 in the column group selection circuit 31 ₁ to which the outputs of the defective address detection circuit groups 28 ₁ and 30 ₁ are supplied, the fuse 36 connected thereto is cut beforehand, and the first input terminal is a load. The output of the AND gate 32 is set to the "1" level because it is set to the "1" level by the resistor 40. At this time, the data read from the memory cell 11 and detected by the sense amplifier 21 is erroneous, that is, inverted, and this inverted data is supplied to the exclusive OR circuit 22. At this time, "1" level signal is outputted from the column group selection circuit 31 ₁ is supplied to the other input terminal of the exclusive OR circuit 22. As a result, the erroneous data detected by the sense amplifier 21 is inverted by the exclusive OR circuit 22 to be corrected to correct data and supplied to the output buffer 23. When correct data is read from the memory cell 11, the output of the column group selection circuits 31 ₁ to 31 ₄ is "0".
The level is set, and the detection data of the sense amplifier 21 is output from this exclusive OR circuit 22 at the same level.

With such a configuration, when a defective cell occurs in the memory cell array 10, the same number of defective cell data as the number of the defective address detection circuit group 28 or 30 can be corrected. In addition, it is possible to relieve a defective cell which is connected to different row lines 12 and different column lines 13 and which occurs randomly. Moreover, since it is not a conventional error detection and correction method using a code, a memory cell for storing a code is unnecessary,
The increase in chip size due to the addition of the correction function can be sufficiently suppressed as compared with the conventional method. Further, since it is not necessary to operate the arithmetic circuit every time data is output, the delay in data access time can be minimized. Further, a total of three fuses may be cut for a defective cell of 1 bit, and the time required for programming the fuses can be greatly shortened as compared with that of a conventional circuit of this type.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above embodiment, when four row-side defective address detection circuit groups 28 and four column-side defective address detection circuit groups 30 are provided, the present invention is applied to a storage device capable of saving a 4-bit defective cell. However, it is also possible to provide a required number of defective address detection circuit groups 28 and column-side defective address detection circuit groups 30, respectively.

[Effects of the Invention] As described above, according to the present invention, a plurality of randomly generated defective bits can be relieved without delaying the access time, and an integrated circuit can be realized by adding a bit defect correction function. It is possible to provide a semiconductor memory device that can relatively reduce the increase in chip size.

[Brief description of drawings]

FIG. 6 is a circuit diagram showing the configuration of an embodiment of the present invention. 10 ... Memory cell array, 11 ... Memory cell, 12 ... Row line, 13 ... Column line, 14,17 ... NOR gate, 15 ... Row decoder, 16 ... Column line selection MOS transistor, 18 ... …
Column line selection line, 19 ... Column decoder, 21 ... Sense amplifier, 22 ... Exclusive OR circuit, 23 ... Output buffer,
24,29 …… Defective address detection circuit, 28,30 …… Defective address detection circuit group, 31 …… Column group selection circuit.

Claims (1)

[Claims] 1. A memory cell array composed of a plurality of memory cells arranged in rows and columns, a row decoder and a column decoder for selecting memory cells in the memory cell array, and connected to output terminals of the row decoder, respectively. A plurality of first defective address detection circuits, in which the corresponding row of the memory cell array is programmable to be defective, divided into a plurality of groups, and output terminals are commonly connected in each group; A plurality of second defective addresses connected to the output terminals of the respective memory cells, programmable so that the corresponding columns of the memory cell array are defective, divided into a plurality of groups, and having the output terminals commonly connected within each group. A detection circuit, an output of a common output end of each group of the plurality of first defective address detection circuits, and a group of each group of the plurality of second defective address detection circuits. The output of the common output terminal is supplied, the memory cell corresponding to a specific row and column of the memory cell array is made programmable, and the defective memory cell corresponding to the specific row and column is selected. A semiconductor memory device, comprising: a detection circuit for detecting the above, and a correction circuit for correcting the read data from the memory cell selected by the row decoder and the column decoder according to the detection output of the detection circuit.