JP3306920B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant circuit for relieving a defective cell and improving the production yield.

[0002]

2. Description of the Related Art In recent years, the size of semiconductor memory devices has been increasing with the increase in their capacity. However, as the size of the chips increases, the probability that dust adheres to the chip surface during the manufacturing process increases. However, there is a problem that the manufacturing yield is reduced.

Therefore, in such a semiconductor memory device, a redundant circuit is provided in order to improve the manufacturing yield.
2. Description of the Related Art A cell that has become defective due to attachment of dust or the like is relieved by a redundant cell.

Here, the redundant circuit is provided with a redundant address storage circuit for storing a redundant address. The redundant address stored in the redundant address storage circuit is externally known for failure analysis and the like. Of a redundant address determination circuit for the purpose.

Conventionally, as this kind of semiconductor memory device, a device whose main part is shown in FIG. 3 is known. In the figure,
1 chip body, 2 _0, 2 _1, 2 ₂ row address input terminal row address is input, 3 _0, 3 _1, 3 ₂ is a column address input terminal the column addresses are inputted.

4 is an input buffer / decoder circuit,
Reference numeral 5 denotes a redundant row address storage circuit for storing redundant row addresses, and reference numeral 6 denotes a memory cell array unit in which memory cells are arranged.

Reference numeral 7 denotes an output buffer circuit for outputting data read from the memory cell array unit 6 to the outside, 8 denotes a data output terminal, and 9 denotes a redundant row address stored in the redundant row address storage circuit 5. From the redundant row address determination circuit.

A redundant column address storage circuit for storing a redundant column address and a redundant column address determination circuit for determining a redundant column address are not shown.

Here, the redundant row address determination circuit 9
By taking the logic of the redundancy determination instruction signal and the level of the word line for redundancy when a row address is input to the row address input terminals 2 ₀ to _{2 2} , the input row address is a redundant row address. Judge whether or not
The determination result, and is configured to output a column address input terminal 3 _2.

Accordingly, in this semiconductor memory device, when determining the redundancy row address, the row address to the row address input terminal 2 _{0-2 2} it is necessary to enter by incrementing sequentially from address 0.

[0011]

As described above, in the conventional semiconductor memory device shown in FIG.
If you do not increment and enter in order from the address,
There is a problem that the redundant row address cannot be determined, and the procedure for determining the redundant row address is complicated.

Although not shown, the redundant column address determination circuit is also configured so that the redundant column address cannot be determined unless the column address is sequentially incremented from address 0 and input. Therefore, there is a problem that the procedure for determining the redundant column address is complicated.

In view of the foregoing, the present invention provides a semiconductor memory having a built-in redundant address determination circuit which can determine a redundant address by a very simple method and can shorten the time used for failure analysis and the like. It is intended to provide a device.

[0014]

According to the semiconductor memory device of the present invention, each bit of an output of a redundant address storage circuit for storing an n-bit (n = 2 or more integer) address is turned on.
In the redundant address determination, n switch elements are connected in series between the first external terminal and the second external terminal, and the n switch elements are connected in parallel to each of the n switch elements. When the redundant address is determined, the resistance between the first external terminal and the second external terminal is set to 2 depending on how the n switch elements are turned on and off.
^The redundant address determination circuit includes n resistors having ⁿ different resistance values.

[0015] Here, for example, in the case where the magnitude of the resistance values of the n resistors 2 ^n-1 to 2 ^n-2 to 2 ^n-3 to-... 2 ^1: 2 ^0, n pieces By setting the ON and OFF states of the switch element described above, 2 ⁿ kinds of resistance values can be obtained as the resistance value between the first external terminal and the second external terminal.

[0016]

In the present invention, each of the n switch elements takes an ON state or an OFF state depending on the value of each bit of the output of the redundant address storage circuit. In this case, the first
The resistance value between the external terminal and the second external terminal is OFF.
It is a value obtained by adding the resistance values of the resistors connected in parallel to the switch element in the state.

Here, since the resistance values of the n resistors are set to take 2 ⁿ types of values depending on the ON / OFF state of the n switch elements, the first external The resistance value between the terminal and the second external terminal indicates a unique value depending on the address stored in the redundant address storage circuit.

Therefore, in the present invention, the address stored in the redundant address storage circuit is known by measuring the resistance value of the redundant address determination circuit using the first external terminal and the second external terminal. be able to.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, portions corresponding to those in FIG. 3 are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention. In this embodiment, a redundant row address determining circuit 9 and a redundant column address determining circuit incorporated in the conventional semiconductor memory device shown in FIG. A redundant row address determination circuit 10 and a redundant column address determination circuit (not shown) having circuit configurations different from those of the circuit (not shown) are provided, and the rest is configured similarly to the conventional semiconductor memory device shown in FIG. It is.

Here, the redundant row address storage circuit 5 and the redundant row address determination circuit 10 are configured as shown in FIG.
11, 12, and 13 are fuse circuits.

In the fuse circuits 11, 12, 13, 14, 15, and 16 are ground lines set to the ground voltage, 17, 18, and 19 are resistors, 20, 21, and 22 are fuses, 23, 24, and 25. Is the power supply voltage VEE, for example,-
VEE power supply line that supplies 5.2 [V].

Here, for example, the fuse circuits 11, 1
If “0” is stored in each of the fuses 2 and 13, the fuses 20, 21 and 22 are not cut, and “1” is stored.
Are stored, the fuses 20, 21, and 22 are blown.

That is, the redundant row address storage circuit 5 stores addresses [0, 0, 0] to [1,
[1,1] Any row address up to the address can be stored.

In the redundant row address judging circuit 10, reference numerals 26, 27 and 28 denote resistors, and reference numerals 29, 30 and 31 denote ON and OFF outputs of the fuse circuits 11, 12, and 13 constituting the redundant row address storage circuit 5, respectively. Is an nMOS transistor as a switch element, and an nMOS transistor as a switch element whose ON / OFF is controlled by a redundant row address determination instruction signal.

Here, the resistance value of the resistor 26 is 4 KΩ, the resistance value of the resistor 27 is 2 KΩ, and the resistance value of the resistor 28 is 1 KΩ. That is, the magnitude of the resistance value of the resistor 26, 27, 28 is a 2 ^2: 2 ^1: 2 ^0.

The nMOS transistor 29 has an nM
In the case where the OS transistor 32 is in the ON state and the fuse 20 is not blown, the node 34 =
When the fuse 20 is cut off at "L" and the fuse 20 is blown, the node 34 is set at "H" and at the ON state.

The nMOS transistor 30 has an nM
When the OS transistor 32 is in the ON state and the fuse 21 is not blown, the node 35 =
When the fuse 21 is cut off at "L" and the fuse 21 is blown, the node 35 is set at "H" and at the ON state.

The nMOS transistor 31 has nM
When the OS transistor 32 is in the ON state and the fuse 22 is not blown, the node 36 =
When "L" is set to the OFF state and the fuse 22 is cut, the node 36 is set to "H" and the ON state.

The nMOS transistor 32 is turned off when the redundant row address determination instruction signal is "L".
When the state and the redundant row address determination instruction signal are “H”, the state is turned on.

As a result, in this embodiment, when the redundant row address determination instructing signal = “H”, n
ON of the MOS transistors 29, 30 and 31, by way of taking in the OFF state, the resistance value between the column address input terminal 3 ₂ and the ground point 37, i.e., the external terminal for grounding a column address input terminal 3 ₂ The resistance values between them are as shown in Table 1.

[0032]

[Table 1]

[0033] Therefore, in this embodiment, by using the external terminal for grounding a column address input terminal 3 _2, by measuring the resistance between the column address input terminal 3 ₂ and the ground point 37 , NMOS transistors 29, 3
0, 31 ON / OFF state, that is, fuses 20, 2
The status of disconnection and non-disconnection of Nos. 1 and 22, that is, the redundant row address stored in the redundant row address storage circuit 5 can be known.

[0034] Thus, according to this embodiment, by using the external terminal for grounding a column address input terminal 3 _2,
It is possible to determine the redundant row address in a very simple way of measuring the resistance value between the column address input terminal 3 ₂ and the ground point 37, it is possible to shorten the time used for failure analysis, etc. it can.

Although not shown, the redundant column address determination circuit can also determine the redundant column address by having the same configuration as the redundant row address determination circuit 10.

In the above embodiment, the resistance 2
Although the case where the resistance values of 6, 27, 28 are set to 2 ² : 2 ¹ : 2 ⁰ has been described, the resistance values of these resistors 26, 27, 28 are not limited to this case, and the nMOS transistor 29,
Depending on how the ON and OFF states of 30, 31 are taken, 2 ³
= Any value that can take eight different resistance values.

In the above embodiment, the case where the row address is 3 bits has been described.
The present invention can be widely applied when the row address is n bits (n = positive integer). In this case, the redundant row address storage circuit has n bits and the redundant row address determination circuit has the magnitude of the resistance values of the resistors, for example, 2 ^n-1 pairs 2 ^n-2 versus 2 ^n-3 to-... 2 ¹
It may be set to 2 ^0.

In the above-described embodiment, the case where the redundant row address storage circuit is constituted by the fuse circuit has been described. The present invention can be applied to a case where the present invention is configured.

[0039]

As described above, according to the present invention, the redundant address stored in the redundant address storage circuit is stored in a very simple method of measuring the resistance value of the redundant address determination circuit using an external terminal. Since the determination can be made, the time used for failure analysis and the like can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a redundant row address storage circuit and a redundant row address determination circuit which constitute one embodiment of the present invention.

FIG. 3 is a block diagram showing a main part of a conventional semiconductor memory device.

[Explanation of symbols]

1 Chip body 2 ₀ to _{2 2} Row address input terminal 3 _{0 to} 3 ₂ Column address input terminal 4 Input buffer / decoder circuit 5 Redundant row address storage circuit 6 Memory cell array unit 7 Output buffer circuit 8 Data output terminal 10 Redundant row address judgment circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 603

Claims (2)

(57) [Claims] An on / off state of each bit of an output of a redundant address storage circuit for storing an address of n bits (n is an integer of 2 or more) depends on a first external terminal and a second external terminal when determining a redundant address. N switching elements connected in series with the external terminals of the switching elements, and each of the n switching elements is connected in parallel to each of the n switching elements. A redundant address including n resistors having a value that takes 2 ⁿ kinds of resistance values as the resistance value between the first external terminal and the second external terminal depending on how to take the address. A semiconductor memory device comprising a decision circuit built therein. Wherein said n resistance, a feature that it is the magnitude of the resistance value 2 ^n-1 to 2 ^n-2 to 2 ^n-3 to-... 2 ^1: 2 ⁰ The semiconductor memory device according to claim 1.