JPH06103796A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten time used for analyzing defective parts and the like by discriminating a redundant address with an extremely simple method, in a semiconductor memory providing a redundant circuit which improves a manufacturing yield by relieving defective cells. CONSTITUTION:ON, OFF operation of nMOS transistors 29, 30 and 31 are made to depend on an output of a redundant row address memory circuit 5. And a resistance value between an input terminal 32 of a column address and a ground point 37 is made a peculiar value corresponding to the redundant row address, and the redundant row address is discriminated by measuring the resistance value between the column address input terminal 32 and the ground point 37 using the column address input terminal 32 and an external terminal for ground.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant circuit for repairing defective cells to improve the manufacturing yield.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been made larger in size with the increase in capacity thereof. However, as the size of a chip increases, the probability of dust adhering to the chip surface increases during the manufacturing process. However, there is a problem that the manufacturing yield is reduced.

Therefore, in such a semiconductor memory device, a redundant circuit is provided in order to improve the manufacturing yield.
It has been practiced to repair cells that have become defective due to adhesion of dust and the like with redundant cells.

Here, the redundant circuit is provided with a redundant address storage circuit for storing a redundant address, and the redundant address stored in this redundant address storage circuit is known from the outside for failure analysis and the like. It has been practiced to incorporate a redundant address determination circuit for this purpose.

Conventionally, as this type of semiconductor memory device, there has been known a semiconductor memory device whose essential portion is shown in FIG. In the figure,
Reference numeral 1 is a chip body, 2 ₀ , 2 ₁ , 2 ₂ are row address input terminals to which a row address is input, 3 ₀ , 3 ₁ and 3 ₂ are column address input terminals to which a column address is input.

Reference numeral 4 denotes an input buffer / decoder circuit,
Reference numeral 5 is a redundant row address storage circuit for storing redundant row addresses, and 6 is a memory cell array portion in which memory cells are arranged.

Reference numeral 7 is an output buffer circuit for outputting the data read from the memory cell array section 6 to the outside, 8 is a data output terminal, and 9 is a redundant row address stored in the redundant row address storage circuit 5. This is a redundant row address determination circuit to be known from.

A redundant column address storage circuit for storing a redundant column address and a redundant column address determination circuit for determining a redundant column address are not shown.

Here, the redundant row address determination circuit 9 is
A redundancy judgment instruction signal, by taking the logic level of the word line for redundancy when inputting a row address to the row address input terminal 2 _{0-2 2,} row address input row address is redundant Is determined,
The determination result, and is configured to output a column address input terminal 3 _2.

Therefore, in this semiconductor memory device, when determining a redundant row address, it is necessary to sequentially increment the row address from address ₀ to the row address input terminals 2 ₀ to _{2 2} .

[0011]

As described above, in the conventional semiconductor memory device shown in FIG. 3, the row address is 0.
If you do not increment by entering from the address,
There is a problem in that the redundant row address cannot be determined and the procedure for determining the redundant row address is complicated.

Although not shown in the figure, the redundant column address determination circuit is also configured so that the redundant column address cannot be determined unless the column address is incremented from 0 and input. However, there is a problem that the procedure for determining the redundant column address is complicated.

In view of the above point, the present invention is a semiconductor memory having a built-in redundant address judging circuit which can judge a redundant address by an extremely simple method and can shorten the time used for defect analysis and the like. The purpose is to provide a device.

[0014]

A semiconductor memory device according to the present invention is turned on for each bit of an output of a redundant address memory circuit for storing an n-bit (n = integer of 2 or more) address,
When the redundant address is determined to be dependent on OFF, n switch elements connected in series between the first external terminal and the second external terminal, and these n switch elements are connected in parallel. At the time of determining a redundant address, the resistance value between the first external terminal and the second external terminal is set to 2 depending on how the n switch elements are turned on and off.
^A redundant address determination circuit is built in, which is provided with n resistors having values that take ⁿ types of resistance values.

[0015] Here, for example, in the case where the magnitude of the resistance values of the n resistors 2 ^n-1 to 2 ^n-2 to 2 ^n-3 to-... 2 ^1: 2 ^0, n pieces It is possible to take 2 ⁿ kinds of resistance values as the resistance value between the first external terminal and the second external terminal depending on how the switch element is turned on or off.

[0016]

In the present invention, each of the n switch elements is turned on or off depending on the value of each bit of the output of the redundant address storage circuit. In this case, the first
The resistance value between the external terminal and the second external terminal is OFF
It is a value obtained by adding the resistance values of the resistors connected in parallel to the switch element in the state.

Here, the resistance values of the n resistors are set to values of 2 ⁿ types depending on how the n switch elements are turned on and off, and therefore, the first external The resistance value between the terminal and the second external terminal shows a unique value depending on the address stored in the redundant address storage circuit.

Therefore, in the present invention, the address stored in the redundant address storage circuit is known by measuring the resistance value of the redundant address determination circuit using the first external terminal and the second external terminal. be able to.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 1 is a block diagram showing an essential part of an embodiment of the present invention. In this embodiment, a redundant row address judging circuit 9 and a redundant column address judging circuit built in the conventional semiconductor memory device shown in FIG. 3 are incorporated. A redundant row address determination circuit 10 and a redundant column address determination circuit (not shown) having a circuit configuration different from that of the circuit (not shown) are provided, and others are configured similarly to the conventional semiconductor memory device shown in FIG. Is.

Here, the redundant row address storage circuit 5 and the redundant row address determination circuit 10 are configured as shown in FIG. 2, and in the redundant row address storage circuit 5,
Reference numerals 11, 12, and 13 are fuse circuits.

In the fuse circuits 11, 12, and 13, reference numerals 14, 15, and 16 are ground lines set to the ground voltage, 17, 18 and 19 are resistors, 20, 21 and 22 are fuses, and 23, 24 and 25. Is a power supply voltage VEE, for example, −
This is a VEE power supply line for supplying 5.2 [V].

Here, for example, the fuse circuits 11 and 1
When “0” is stored in each of the Nos. 2 and 13, the fuses 20, 21, 22 are not cut, and the “1” is stored.
Is stored, the fuses 20, 21, 22 are blown.

That is, the redundant row address storage circuit 5 stores redundant row addresses from addresses [0, 0, 0] to [1,
Any row address up to addresses 1 and 1] can be stored.

In the redundant row address determination circuit 10, 26, 27 and 28 are resistors, and 29, 30 and 31 are ON and OFF to the outputs of the fuse circuits 11, 12 and 13 constituting the redundant row address storage circuit 5, respectively. Is an nMOS transistor that forms a switch element that depends on, and 32 is an nMOS transistor that forms a switch element whose ON / OFF is controlled by a redundant row address determination instruction signal.

The resistance value of the resistor 26 is 4 KΩ, the resistance value of the resistor 27 is 2 KΩ, and the resistance value of the resistor 28 is 1 KΩ. That is, the magnitude of the resistance value of the resistor 26, 27, 28 is a 2 ^2: 2 ^1: 2 ^0.

Further, the nMOS transistor 29 has an nM
In the case where the OS transistor 32 = ON state and the fuse 20 is not cut, the node 34 =
When it is "L", it is turned off, and when the fuse 20 is blown, it is turned on when the node 34 = "H".

Further, the nMOS transistor 30 has an nM
When the OS transistor 32 = ON state and the fuse 21 is not cut, the node 35 =
When it is "L", it is turned off, and when the fuse 21 is blown, it is turned on when the node 35 is "H".

Further, the nMOS transistor 31 has an nM
In the case where the OS transistor 32 = ON state and the fuse 22 is not cut, the node 36 =
When it is "L", it is turned off, and when the fuse 22 is blown, it is turned on when the node 36 = "H".

The nMOS transistor 32 is turned off when the redundant row address determination instruction signal = “L”.
In the state, if the redundant row address determination instruction signal = “H”, it is turned on.

As a result, in the present embodiment, when the redundant row address determination instruction signal = “H”, n
Depending on how the MOS transistors 29, 30, 31 are turned on and off, the resistance value between the column address input terminal 3 ₂ and the ground point 37, that is, the column address input terminal 3 ₂ and the external terminal for grounding, The resistance value between them is as shown in Table 1.

[0032]

[Table 1]

Therefore, in the present embodiment, the column address input terminal 3 ₂ and the external terminal for grounding are used to measure the resistance value between the column address input terminal 3 ₂ and the ground point 37. , NMOS transistors 29, 3
ON and OFF states of 0 and 31, that is, fuses 20 and 2
It is possible to know the state of disconnection and non-disconnection of Nos. 1 and 22, that is, the redundant row address stored in the redundant row address storage circuit 5.

As described above, according to this embodiment, the column address input terminal 3 ₂ and the external terminal for grounding are used,
Since the redundant row address can be determined by an extremely simple method of measuring the resistance value between the column address input terminal 3 ₂ and the ground point 37, the time used for defect analysis can be shortened. it can.

Although not shown, the redundant column address determination circuit can also determine the redundant column address by configuring the redundant column address determination circuit in the same manner as the redundant row address determination circuit 10.

Further, in the above embodiment, the resistor 2
Has been described in which the resistance value of 6,27,28 2 ² to 2 ¹ to 2 ^0, the resistance value of the resistors 26, 27 and 28 is not limited to this case, nMOS transistors 29,
2 ³ depending on how to turn on and off 30 and 31
= Any value that can take eight types of resistance values may be used.

In the above embodiment, the case where the row address is 3 bits has been described, but the present invention is
It can be widely applied to the case where the row address is n bits (n = a positive integer). In this case, the fuse circuit forming the redundant row address storage circuit is set to n bits and the redundant row address determination circuit is formed. the magnitude of the resistance values of the resistors, for example, 2 ^n-1 pairs 2 ^n-2 versus 2 ^n-3 to-... 2 ¹
It may be set to 2 ^0.

Further, in the above-mentioned embodiments, the case where the redundant row address storage circuit is composed of the fuse circuit has been described, but instead of this, the redundant row address storage circuit is constituted by a non-volatile cell or a flip-flop circuit. The present invention can be applied to the case of configuration.

[0039]

As described above, according to the present invention, the redundant address stored in the redundant address storage circuit can be determined by the extremely simple method of measuring the resistance value of the redundant address determination circuit using the external terminal. Since the determination can be made, the time used for failure analysis and the like can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a redundant row address storage circuit and a redundant row address determination circuit which constitute an embodiment of the present invention.

FIG. 3 is a block diagram showing a main part of a conventional semiconductor memory device.

[Explanation of symbols]

1 chip body 2 ₀ to _{2 2} row address input terminal 3 _{0 to} 3 ₂ column address input terminal 4 input buffer / decoder circuit 5 redundant row address storage circuit 6 memory cell array section 7 output buffer circuit 8 data output terminal 10 redundant row address determination circuit

Claims (2)

[Claims] 1. A first external terminal and a second external terminal are made to depend on ON and OFF for each bit of an output of a redundant address storage circuit which stores an n-bit (n = integer of 2 or more) address, when a redundant address is determined. Switch elements connected in series with the external terminals of the switch and the switch elements connected in parallel to each of the n switch elements, and when the redundant address is determined, the n switch elements are turned on and off. A redundant address comprising n resistances whose values are set to take 2 ⁿ kinds of resistance values between the first external terminal and the second external terminal depending on how to take them. A semiconductor memory device comprising a judgment circuit built therein. Wherein said n resistance, a feature that it is the magnitude of the resistance value 2 ^n-1 to 2 ^n-2 to 2 ^n-3 to-... 2 ^1: 2 ⁰ The semiconductor memory device according to claim 1.