KR0185612B1 - Row decoder for protecting stand by fail - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs; A low decoder of a semiconductor memory device.

2. The technical problem to be solved by the invention; It provides a row decoder that can eliminate current failing in the standby state.

3. Summary of the Solution of the Invention; At least two of the word line driver circuits in a row decoder having string driver circuits for driving string select lines in accordance with a string select signal and word line driver circuits for driving word lines in accordance with a first word line select signal The at least one word line driver circuit is driven according to the second word line selection signal.

4. Significant use of the invention; It is suitably used for low decoders of semiconductor memory devices.

Description

Low Decoder Prevents Fail in Standby

1 is an overall functional block diagram of a mask ROM.

2 is a circuit diagram showing a row decoder and a memory cell array connected to a row decoder according to the prior art.

3 is a concrete circuit diagram of an X-predecoder for driving a low decoder according to the prior art.

4 is a circuit diagram illustrating a low decoder and a memory cell array connected to the low decoder according to the present invention.

5 is a detailed circuit diagram of an X-predecoder for driving a low decoder according to the present invention.

The present invention relates to a semiconductor memory device, and more particularly to a row decoder.

Representative types of memory cells in a semiconductor memory device using a row decoder have a contact mask type and a NAND type. Among these, the NAND type memory cell can minimize the area of the memory cell by connecting transistors in series. It is used in most ROMs. When a memory cell of a semiconductor memory device composed of such NAND type memory cells is damaged by a stressor (during manufacturing process: white ribbon, pin-hole, etc. / after manufacturing process: burn-in, etc.) during or after the manufacturing process Remedy can be performed by a bad remedy (extra memory cell, error correction code: ECC), but when the current consumption increases in the stand-by state due to the bad memory cell, the bad remedy of data becomes meaningless. It is essential to suppress the current increase. Therefore, the problem of the current increase in the standby state in this regard will be described with reference to FIGS.

1 is a general functional block diagram of a mask ROM.

Referring to FIG. 1, the mask ROM includes a chip enable buffer 10 driven by a chip enable signal CEx, an address driven by the chip enable signal CEx, a row address signal AXi, and a column address signal AYi. Driven by the buffer 20, the X-predecoder 40 driven by the output signals P, Q, SS, and X of the address buffer 20, and the output signals of the address buffer 20. Y-predecoder 50, output signals of the X-predecoder 40, low decoder 60 driven by Pi, Qi, SSi, Xi, and output signal of the Y-predecoder 50 Y-pass 80 driven by the memory cell array 70 and Y-pass 80 driven by the output signal of the low decoder 60 and the output signal of the Y-pass 80. A sense amplifier (90) for sensing and amplifying a signal output through the, and temporarily storing the output of the sense amplifier (90) Emitter an output buffer 100 and an output terminal and the input-output pads (110) connected to the data output buffer 100.

The well-known components of the above components are omitted from the detailed description so as not to obscure the features of the present invention.

FIG. 2 is a circuit diagram showing the memory cell array 70 connected to the conventional row decoder 60 shown in FIG.

Referring to FIG. 2, a memory cell string connected to a strain line BL of one of a plurality of bit lines arranged in a column direction will be described as an example. Memory cell strings S1 and S2 are connected in parallel between the bit line BL and ground power supply VSS, and the memory cell string S1 selects transistors for selecting the memory cell string S1 between the bit line BL and ground power supply. The channels of ST1 and ST2 and the channels of the memory cells M1 to M8 (en-channel Morse transistor) for storing and reading data are connected in series, and the memory cell strings S1 to Sn having the same structure as the memory cell string S1 are Arranged in a matrix form of rows and columns, the control gates of the memory cells M1 to M8 are connected to the corresponding word lines WL1 to WL8, respectively, and the selection transistors ST1 and ST2 are corresponding string selection lines SL1 and SL2. Are respectively connected to the string selection lines SL1 and SL2 and are respectively connected to the corresponding string selection lines SL1 and SL2 and are respectively connected to the string selection lines SL1 and SL2. Since the word lines WL1 to WL8 are connected to the row decoder 60, the row decoder 60 will be described in detail to clarify the present invention to be described later. A channel is connected in series between the inverters INV1 and INV2 connected to SL1 and SL2 and the connection nodes N2 and N3, which are input terminals of the inverters INV1 and INV2, respectively, and the gate is connected to N2, Precharge transistors (depletion) en-channel MOS transistors connected to N3, respectively, and a channel is serially connected between PCT1 and PCT2 and the connection nodes N2 and N3 corresponding to the string selection signals SS1 and SS2. Fast transistors (en-channel mode transistors) PT1 and PT2 connected to each other, delay circuits (circuit consisting of two inverters G2 and G3) D1 to D8 respectively connected to the word lines WL1 to WL8, and the delay. Of circuits D1-D8 Precharge transistors (depletion en-channel MOS transistors) WPCT1 to WPCT8 are respectively connected in series between the input nodes N4 to N11 and the power supply voltage in series, and the gates are respectively connected to the connection nodes N4 to N11. And fast transistors (en-channel MOS transistors) WPT1 to WPT8 having channels connected in series between the connection nodes N cells to N1 corresponding to the word line selection signals X1 to X8, and the fast transistors PT1. , PT2, and a gate node G1 connected to the connection node N1 to which the gates of WPT1 to WPT8 are connected and operated by a combination of the output signals Pi and Qi of the X-predecoder 40.

The operation of the row decoder 60 will be presented after the detailed description with respect to FIG.

3 shows a word line control circuit for generating a word line selection signal for controlling a word line in accordance with the present invention.

Since the word line control circuit is a circuit included in the X-predecoder 40, it will be referred to as an X-predecoder 40 hereinafter. The word line control circuit comprises the X-predecoder 40 showing a circuit for generating only word line selection signals X1 to X8 by combining the address signals Ai, Aj, Ak and its complementary signals Ai, Aj, Ak. ) Is composed of a NAND gate 41 and two inverters 42 and 43.

Referring to the operation of the row decoder 60 through FIGS. 2 and 3, the operation of the string select lines SL1 and SL2 is performed at the low level of both the output signals Pi and Qi from the X-predecoder 40. When the two input terminals of the noble gate G1 are input, the output terminal of the noble gate G1 becomes high level. At this time, an address signal SS, which is an external input signal, is input to the X-predecoder 40, and the string selection signal SS1 selected by the X-predecoder 40 has a low level (SS2 is selected as a string selection signal. And SSn are all charged to a high level voltage value) to discharge through the fast transistor PT1. Subsequently, a voltage value of a high level (all unselected string selection lines SL2 to SLn are applied with a low level voltage) passing through the inverter INV1 is applied to the selection transistor ST3 (the selection transistor ST4 has a low level). The string S2 is selected by turning on a voltage value applied and being turned on). In the operations of the word lines WL1 to WL8 connected to the gates of the memory cells M9 to M16 in the selected string S2, an address signal S, which is an external input signal, is input to the X-free decoder 40, and the X-free decoder ( One word line selection signal X1 selected by 40) becomes low level and is discharged through the fast transistor WPT1. Subsequently, after being delayed by the delay circuit D1, a low level (high level is applied to unselected word lines WL2 to WL8) is applied to the word line WL1 to select the memory cell M9 connected to the string S2. At this time, if the memory cell M9 is turned on (Inhencement) is turned off, if the depletion (Depletion) is turned on, current is already turned on in the memory cell M10 through the memory cell M16 to the bit line BL A path between the connected sense amplifier 90 and a ground voltage (ground level voltage) is formed. Therefore, the sense amplifier 90 reads the logical data 1 or the logical data 0 by the two modes when the current path between the sense amplifier 90 and the ground voltage is formed or not. On the other hand, the operation of the row decoder 60 in the standby state of the semiconductor memory device will be described. Since the signals Pi and Qi, which are signals for selecting the row decoder 60, are at a high level in the standby state, the output of the NOA gate G1 is output. The connection node N1, which is a terminal, becomes low level and is charged by the precharge transistors PCT1, PCT2, and WPCT1 to WPCT8 by turning off the fast transistors PCT1, PCT2, and WPCT1 to WPCT8. . The charges charged by the precharge transistors PCT1 and PCT2 apply a low level voltage value to the string select lines SL1 and SL2 by the inverters INV1 and INV2, and the word lines WL1 to WL8. The charges precharged by the precharge transistors WPCT1 to WPCT8 connected to the high voltage are applied to all of the word lines WL1 to WL8 by the delay circuits D1 to D8. Therefore, if an oxide layer, which is a gate protection layer of one or more memory cells, is destroyed in the memory cells M1 to M8 during the standby state of the chip, a DC current path is formed between the voltage applied to the gate of the destroyed memory cell and the ground to form a standby current. There is a problem that causes a failure (Fail).

Accordingly, an object of the present invention is to provide a row decoder capable of eliminating current fail generated in the standby state of a chip.

In the present invention for achieving the above object, a nonvolatile semiconductor memory device having a plurality of memory strings consisting of a plurality of memory string transistors connected in series between a string select transistor connected to a bit line and a ground voltage. A first circuit section for controlling driving of a first memory V transistor group connected to the string transistor side of the memory V transistors of a memory V string; And a fast transistor, a precharge transistor, and an inverter. The semiconductor memory device is in a standby state by controlling driving of a second memory transistor group connected to the ground voltage side of the memory transistor of the memory string. And a second circuit section for selectively controlling the electrical connection between the memory string and the ground voltage.

Hereinafter, the detailed description of the preferred embodiments of the present invention will be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

4 is a circuit diagram showing a memory cell array 70 connected to the row decoder 160 according to the present invention.

Referring to FIG. 4, the configuration of the row decoder 160 is the same as the circuit configuration described with reference to FIG. 2 except for the circuit shown in FIG. 2 in the circuit for driving the word lines WL7 and WL8. The circuit was constructed by removing one of the inverters G2 and G3 in the delay circuits D7 and D8. The number of inverters connected by removing one of the inverters G2 and G3 will be named as G10 and G20, respectively, for the convenience of the following description. The description of the operation will be presented after the description of FIG.

5 is a word line control circuit for generating a word line selection signal for controlling a word line in accordance with the present invention.

Referring to the circuit arrangement of FIG. 5, the circuit arrangement for generating word line selection signals X1 to X6 for controlling the word lines WL1 to WL6 is the same as that described in FIG. The circuit configuration for generating word line selection signals X7 and X8 for controlling WL7 and WL8 was designed by adding an inverter 44 to the output terminal of the one described in FIG.

4 and 5, the operation for selecting the string selection lines SL1 and SL2 and the word lines WL1 to WL6 is the same as that described with reference to FIG. 2, and thus, the word lines are omitted. The operation to select WL7 and WL8 and the operation of the chip in the standby state will be described in detail. First, in the standby state of the chip, since the output terminal of the noble gate G1 is a state indicating a low voltage value, the fast transistors WPL7 and WPL8 are turned off and the connection node is disconnected by the precharge transistors WPCT7 and WPCT8. N10 and N11 are charged. The charges charged by the precharge transistors WPCT7 and WPCT8 apply a low level voltage value to the word lines WL7 and WL8 by the inverters G10 and G20. Therefore, even when an oxide film, which is a gate protection film of one or more memory cells, of the memory cells M1 to M16 in the string is destroyed, the voltages applied to the gates of the two memory cells M7, M8, M15, and M16 connected to the ends of the strings remain. In this case, the difference in usage in the method of bringing one or more word lines connected to the end of the string S2 into the low level in the standby state is limited to the end of the string S2. When only one word line is at a low level, when the memory cell M8 selected by the word line is a depletion transistor, the current path cannot be blocked, and thus the current flowing in the standby state cannot be saved. If memory cell M8 is an enhancement transistor, shut off current in standby It is good. Therefore, in order to reduce the probability of such a case, two or more word lines are brought to a low level in the standby state to save the fail in the more accurate standby state. Further, the word lines WL1 to WL6 are operated in the same manner as described in FIG. Meanwhile, referring to operations other than the standby state of the semiconductor memory device, operations of the string selection lines SL1 and SL2 and the word lines WL1 to WL6 are the same as those described with reference to FIG. 2 and the word lines WL7 and WL8. The word line selection signal X8 in which the address signal X, which is the external input signal, is selected by the X-predecoder 40 when the word line WL8 is selected among the word lines WL7 and WL8, The word line select signal X7 has a low level voltage with a high level voltage. Thus, by bringing the connection node N10 to ground level through the turned-on fast transistor WPT7 connected to the unselected word line WL7, the inverter G10 is brought into a high level state, thereby operating the original low decoder. Will be done.

As described above, the present invention has the effect of eliminating the standby current fail that may occur when the gate protection layer of the memory cell is destroyed.

Although the present invention has been described with a string having eight memory cells as an example, it is also applicable to the case where the memory cells have 16 or more memory cells. In addition, the present invention has been described in the case of having two strings on both sides of the bit line, but it will be apparent to those skilled in the art that the present invention is applicable to the case of having a string on one side.

Claims (2)

1. A nonvolatile semiconductor memory device having a plurality of memory V strings comprising a plurality of memory V transistors connected in series between a string selection transistor connected to a bit line and a ground voltage, wherein: a memory V transistor of the memory V string A first circuit section for controlling driving of a first memory-V transistor group connected to the string transistor side; And a fast transistor, a precharge transistor, and an inverter. The semiconductor memory device is in a standby state by controlling driving of a second memory transistor group connected to the ground voltage side of the memory transistor of the memory string. A second circuit portion for selectively controlling the electrical connection between the string and the ground voltage; (Correction) The semiconductor memory device according to claim 1, wherein the output of said second circuit portion is at a low level in a standby state.