JP2534308B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory such as a mask ROM in which information is written at a manufacturing stage and a decoder for improving the yield is built in. .

[Problems to be Solved by Conventional Techniques and Inventions] Recently, in a mask ROM, various techniques have been used to improve the yield along with the miniaturization of dimensions and the increase in storage capacity. As the first method, a mask ROM incorporating an error correction circuit has been partially put into practical use.
However, this method has a drawback that the chip area is increased by 20% or more because the inspection bit is incorporated.

As a second method, a spare array used in RAM or the like is provided, and if there is a defective array, it is replaced with the spare array. However, in the case of a mask ROM, it is difficult to apply because information is written at the manufacturing stage.

On the other hand, with the increase in capacity, the entire area of the memory space is not used, and there is a high possibility that an unused area will occur. When a defective bit occurs in an unused area, the area that is not actually accessed is Therefore, although there is no problem in practical use, in the shipping test, there is a problem in that it cannot be distinguished from the used area and the unused area, so that the product must be treated as a defective product.

Therefore, a main object of the present invention is to incorporate a decoder circuit composed of an information writable storage element at the time of manufacturing, so that when an unused area occurs, the address information of this area is stored in the decoder circuit at the time of manufacturing. It is an object of the present invention to provide a semiconductor memory capable of controlling data by detecting an address pattern corresponding to a written or unused area.

[Means for Solving the Problems] In the present invention, in a semiconductor memory having a used area in which information is written and an unused area in which information is not written in a manufacturing stage, address data indicating the unused area is A decoder which is written in advance and which always outputs a constant value in response to the input of an address signal corresponding to the address data, and the output of the decoder controls the data from the used area or the unused area. And a gate circuit for outputting the output.

[Operation] In the semiconductor memory according to the present invention, when the address signal indicating the unused area is input, the output is always set to a constant value. Therefore, even if the unused area includes a defective bit, Since the defective bit does not determine the semiconductor memory device as a defective product, the yield can be improved without increasing the chip area.

[Embodiment of the Invention] FIG. 1 is an electric circuit diagram showing a decoder included in an embodiment of the present invention, and FIG. 2 is a diagram showing a storage area of a mask ROM.

As shown in FIG. 2, it is assumed that addresses 1000 to 1FFF are unused areas 11 and addresses 32000 to 32FFF are unused areas 12 in the memory space of the mask ROM 1. When memory cells are defective in such unused areas 11 and 12, even if the unused areas 11 and 12 are addressed, erroneous data is not output. 2, 4 are provided in the mask ROM. The decoder 2 designates the unused area 11, and the decoder 4
Indicates an unused area 12.

In the decoder 2, high V _TH transistors 21 to 26 that switch at a relatively high input voltage are connected in series, and the drain of the transistor 21 is connected to the power source + V via the P-channel MOS transistor 6 and the transistor 26
Is grounded through an enhancement transistor 37 that switches at a relatively low input voltage. An address signal is applied to each gate of each transistor 21-26 and 37.
A18 to A12 are given.

Also, enhancement transistors 31-36 are each connected in series, the drain of transistor 31 is connected to the source of transistor 6, and the source of transistor 36 is grounded via high V _TH transistor 27. An address signal is applied to each gate of the transistors 31 to 36 and 27.
▼ to ▲ ▼ are given. The transistor
22 drain, transistor 31 source, transistor
Drain of 23, source of transistor 32, transistor
24 drain, source of transistor 33, transistor
25 drain, transistor 34 source, transistor
The drain of 26 and the source of the transistor 35 are connected to each other, and the drain of the transistor 37 and the source of the transistor 36 are connected to each other.

On the other hand, in the decoder 4, a high V _TH transistor 41, enhancement transistors 52 and 53, high V _TH transistors 44 and 45, enhancement transistor 56 and high V _TH transistor 47 are connected in series, and the drain of the transistor 41 is connected to the source of the transistor 6. Connected and transistor
The source of 47 is grounded. And each transistor 41,5
Address signal A18 is applied to each gate of 2,53,44,45,56 and 47.
~ A12 is given. Further, an enhancement transistor 51, high V _TH transistors 42 and 43, enhancement transistors 54 and 55, high V _TH transistor 46 and enhancement transistor 57 are connected in series, and the drain of transistor 51 is connected to the source of transistor 6 and transistor 57 is connected. Source is grounded. And
Address signals ▲ ▼ to ▲ ▼ are applied to the gates of the transistors 51, 42, 43, 54, 55, 46 and 57.

In addition, the drain of transistor 52 and transistor 51
Source, drain of transistor 53 and transistor 42
Source, transistor 44 drain and transistor 43
Source, transistor 45 drain and transistor 54
Source, drain of transistor 56 and transistor 55
Source and the drain of the transistor 47 are connected to the source of the transistor 46, respectively. Further, the source of the transistor 6 is connected to one input end of the AND gate 7, and the output data of the sense amplifier is given to the other input end of the AND gate 7. The output of the AND gate 7 is output as output data via the output buffer 8.

Although not shown, the mask ROM 1 is addressed by address signals A0 to A18, and A12 to A18, ▲ ▼ to ▲ ▼ of the address signals are given to the decoders 2 and 4 described above.

Next, the operation will be described. Now address signal A12
To "H", ▲ ▼ to "L", A13 to A18 to "L", ▲ ▼
Setting ~ to ▼ to "H" sets transistors 31 to 37
Is turned on, the transistors 21 to 27 are turned off, one input end of the AND gate 7 becomes "L", and the gate is closed.
The output data of the sense amplifier is no longer output. That is, the output of the AND gate 7 becomes, for example, "H", similarly to the data when it is not used. Therefore, the address signal A0
Even if the unused area 11 of the mask ROM 1 is addressed by ˜A18 and erroneous data is read out, it is prevented from being output by the AND gate 7.

Similarly, set the address signals A17, 16, 13 to "H", ▲
▼, ▲ ▼, ▲ ▼ for "L", A18,15,14,12 for "L", ▲
When ▼, ▲ ▼, ▲ ▼, and ▲ ▼ are set to "H", the transistors 51 to 57 become conductive, and one input terminal of the AND gate 7 becomes "L" level in the same manner as described above. AND gate 7 is closed. Therefore, the mask R
Even if the unused area 12 of OM1 is addressed, incorrect data will not be output.

[Effects of the Invention] As described above, according to the present invention, the decoder in which the data indicating the area where the information is not written is previously written is provided, and the address signal indicating the unused area is input. Accordingly, since the output is always set to a constant value, even if a defective bit is included in the unused area, the semiconductor memory element is not judged as a defective product by the defective bit, so that the yield is improved. it can. Further, not only the application of the unused area only, but also when the same data occupies a certain area, the same effect can be obtained. The decoder can be arranged in an empty space of the input / output circuit around the memory array, and the yield can be improved without increasing the chip area.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing an unused area of the mask ROM. In the figure, 1 is a mask ROM, 2 and 4 are decoders, 6 is a P-channel MOS transistor, 7 is an AND gate, 8 is an output buffer, 11 and 12 are unused areas, 21 to 27 and 41 to 47 are enhancement transistors, 31-37, 51-57 represent high V _TH transistors.

Claims (1)

(57) [Claims] 1. In a semiconductor memory having a used area in which information is written and an unused area in which information is not written in a manufacturing stage, address data indicating the unused area is written in advance and the address data is written in the address data. A decoder that always outputs a constant value in response to the input of the corresponding address signal, and a gate circuit that controls and outputs the data from the used area or the unused area by the output of the decoder. A semiconductor memory characterized by being provided.