JPH0685244A - Semiconductor element having electrostatic induction buffer structure - Google Patents

Abstract

PURPOSE:To make it possible to improve the injection efficiency of hole from an anode and apply a high electric field between a cathode and the anode while forming a buffer layer in a low resistance by depleting a low impurity density region. CONSTITUTION:In a turn-on state, holes mainly flow in a low impurity density region 12 of an electrostatic induction (SI) buffer layer and electrons injected from a cathode are stored in a high impurity density region 11 of the SI buffer layer. The high impurity density region 11 is short-circuited to an anode region 2 at a pitch two times the diffusion length Ln of electron, that is, 2Ln or shorter, and has an effect, of absorbing the electrons into an anode electrode 1 in accordance with the life of electron in the SI buffer layer determined by the life time of electron. A metal layer or a metal silicide layer may be used instead of the high impurity region 11 of the SI buffer layer. In short, the low impurity density layer of the SI buffer layer may be depleted by a diffusion potential occurring between the low impurity density layer and the high impurity density layer, metal or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and in particular, in a semiconductor device having a buffer structure, the resistance of a buffer layer is reduced, the injection rate of holes from the anode is increased, and the cathode-anode The present invention relates to a semiconductor device having a new buffer structure capable of applying a strong electric field (hereinafter, referred to as an electrostatic induction buffer structure).

[0002]

2. Description of the Related Art Conventionally, various semiconductor devices having a buffer layer have been proposed. For example, it is as proposed in a high breakdown voltage GTO, an electrostatic induction thyristor, an IGBT (insulated gate bipolar transistor), an insulated gate electrostatic induction thyristor and the like. The feature of this structure is that the n buffer layer is positively interposed between the high resistance layer of the n base layer and the gate (base) on the front surface of the anode (collector) region.
The electric field distribution between the anodes (collectors) is changed from a substantially triangular shape to a trapezoidal shape so that a strong electric field is uniformly applied to the vicinity of the anode region. As a result, the thickness of the high resistance layer can be reduced, the breakdown voltage can be easily increased, and the carriers drift in the high resistance layer due to the strong electric field, so that particularly the turn-on characteristics are improved.

An example of the structure of the electrostatic induction thyristor having the n-buffer structure is as already disclosed in Japanese Patent Publication No. 59-31869. Or 2500V-300A
Prototype example of a prototype embedded gate SI thyristor
E 16TH ANNUAL IEEE POWER ELECTRONICS SPECIALISTS C
"LOW-LOSS HIGH SPEED" in ONFERENCE (PESC '85)
SWITCHING DEVICE, 2500V-300A STATIC INDUCTION THY
It is reported as "RISTOR".

FIG. 13 is a sectional structural view schematically showing an example of the prototype structure in the above paper. In FIG. 13, 1 is an anode electrode, 2 is an anode region, 3 is an n buffer layer, 4 is an n buffer shorting layer, 5 is a high resistance layer, 6 is a gate region, 7
Is an epitaxial layer, 8 is a cathode region, 9 is a cathode electrode, and 10 is a gate electrode. The n layer 3 serves as an n buffer layer, and the n ⁺ region 4 allows the P anode region 2
Is electrically short-circuited with. The n ⁺ region 4 is formed substantially on the lower side of the gate electrode 10 projected onto the anode surface.

Here, the amount of holes injected from the anode side is determined by the thickness of the n buffer layer and the value of the impurity density. If the impurity density of the n buffer layer is set too high,
The injection amount decreases, which affects the turn-on characteristics and on-voltage. When the impurity density of the n buffer layer is lowered, the hole injection amount is increased, but a strong electric field may enter the n buffer layer to cause punching through, resulting in a contradiction that the breakdown voltage cannot be increased so much. Therefore, n
Although it is possible to set the thickness of the buffer layer to a certain degree, in an n buffer layer set to a certain thickness with a predetermined impurity density, the on-voltage rises, the amount of holes injected decreases, and latching occurs. Problems such as a sluggish reaction to move up (that is, a decrease in turn-on response) are likely to occur. Therefore, in the current semiconductor device having an n-buffer layer, although it is desirable to set the thickness to a certain degree thick to form a high impurity density to prevent high breakdown voltage, it is desirable to set the thickness to a certain level, but the amount of injected holes is increased. Is formed to have a moderate impurity density in order to secure a certain degree of

Furthermore, since the n buffer layer is interposed between the anode region and the high resistance layer as a layered region having a predetermined impurity density, the n buffer layer remains in an electrically floating state with respect to the anode region. The electrons as carriers accumulated therein will continue to exist in the n buffer layer for a period determined by their lifetime. In this case, it causes the injection of holes from the anode region,
When the lifetime of electrons is long, hole injection occurs during that time, which also causes injection of extra holes.
Therefore, it is desirable that the n buffer layer be electrically shorted to the anode region. However, if the short-circuit rate is increased, the effect of the n-buffer is weakened, latching-up does not occur, or the injection amount of holes is reduced, and even if the off characteristic and the tail characteristic are improved, the on characteristic is deteriorated. It also causes Since the n buffer layer is formed in layers, it is necessary to reduce the lateral resistance. Furthermore, the conventional buffer structure having a base structure has a drawback that the on-voltage tends to increase due to its structure.

[0007]

The object of the present invention is to increase the hole injection rate from the anode region, to reduce the resistivity distribution, and to apply a strong electric field between the cathode and the anode to achieve a high breakdown voltage. An object of the present invention is to provide a suitable semiconductor device having a static induction buffer structure.

Another object of the present invention is to provide a semiconductor device having an improved on-voltage as compared with the conventional base layer structure by adopting the electrostatic induction buffer structure.

[0009]

The electrostatic induction (SI) buffer structure disclosed by the present invention is a buffer structure utilizing the electrostatic induction effect. That is, in the turned-on state, holes mainly flow in the low impurity density region of the SI buffer layer, and the electrons injected from the cathode are accumulated in the high impurity density region of the SI buffer layer. This high impurity density region is twice the diffusion length L _n of electrons, that is, 2L _n
It is short-circuited with the anode region at the following pitches, and has the effect of absorbing electrons in the anode electrode in accordance with the life of electrons in the SI buffer layer determined by the electron lifetime τ _n . Instead of the high impurity density region of the SI buffer layer,
A metal layer of W, Mo, Co, Pt or the like or a metal silicide layer may be used.

The point is that the low impurity density layer of the SI buffer layer should be depleted by the diffusion potential generated between it and the high impurity density layer or the metal layer. The potential in the depleted low impurity density layer of the SI buffer layer is SI
The thickness and the impurity density may be selected so as to be capacitively controlled by the potential of the high impurity density layer or the metal layer of the buffer layer. In the ON state, a channel region is formed which also serves as a passage for holes, but this channel region is a depleted channel and its height is variable by capacitive coupling by controlling the potential barrier by the electrostatic induction effect. is there. A shorter channel length is more effective because the hole injection amount increases, but on the other hand, the depletion layer spreading from the cathode side has a potential potential structure high enough to sufficiently block a high voltage even if it reaches. Need to be. The region that mainly blocks the strong electric field is the high impurity density region or the metal layer region of the SI buffer layer, but the depletion layer penetrates to a part of the low impurity density region, and the height of the potential barrier of the channel in the low impurity density region is increased. The effect of lowering also occurs. When this effect becomes strong, hole injection from the anode is caused and the effect of the buffer layer is reduced.
Therefore, in the SI buffer structure, the potential barrier height of the channel portion in the low impurity density region is set sufficiently high,
It is necessary that the strong electric field between the cathode and the anode can be sufficiently blocked, and that the potential barrier height can be changed by capacitive coupling depending on the potential of the high impurity density region or the metal layer.

The buffer structure defined and described above will be referred to as a static induction (SI) buffer structure.

Therefore, the structure of the present invention is as follows. That is, the present invention includes an anode region, a cathode region,
In a semiconductor device having a gate region, a buffer layer is provided in contact with or in the vicinity of the anode region, the buffer layer has a high impurity density region and a low impurity density region, and the low impurity density region is the high impurity density region. The buffer layer in the high impurity density region is substantially depleted by a diffusion potential between the impurity concentration region and the high impurity concentration region, and the buffer layer is short-circuited with the anode region at a pitch of 2L _n or less (L _n is an electron diffusion length). The semiconductor device has a structure as a semiconductor device having an electrostatic induction buffer structure characterized by the above.

Alternatively, the buffer layer has a structure as a semiconductor device having an electrostatic induction buffer structure, which is of a conductivity type opposite to that of the anode region.

Alternatively, in the buffer layer, the high impurity density region has a conductivity type opposite to that of the anode region, and the low impurity density region has the same conductivity type as the anode region or an intrinsic semiconductor region. And a structure as a semiconductor device having an electrostatic induction buffer structure.

Alternatively, in a semiconductor device having an anode region, a cathode region, and a gate region, a buffer layer is provided in contact with or near the anode region, and the buffer layer includes a metal layer region and a low impurity density region. And the low impurity density region is substantially depleted by a diffusion potential between the low impurity concentration region and the metal layer,
The buffer layer in the metal layer region is short-circuited with the anode region at a pitch of 2L _n or less (L _n is a diffusion length of electrons), which is a semiconductor device having a static induction buffer structure. I have.

Alternatively, a structure as a semiconductor device having an electrostatic induction buffer structure is characterized in that a thin semiconductor layer having a conductivity type opposite to that of the anode region is interposed between the buffer layer and the anode region. Is to have.

[0017]

1 is a schematic cross-sectional structure diagram of an electrostatic induction (SI) buffer structure applicable to an embodiment of the present invention. Figure 2
FIG. 3 is an explanatory diagram of a potential distribution of the SI buffer structure. 1 and 2, the n buffer structure is formed in layers by a buffer layer 11 having a high impurity density and a buffer layer 12 having a low impurity density. n ⁺ layer 11 are each meshed, stripes or the like, or n ^- has a plane pattern shape of the plate-like shape with a hole in the layer 12, n ^- layer 12
Together with this, an electrostatic induction (SI) buffer layer is formed.
Reference numeral 1 is an anode electrode, 2 is an anode region, and 5 is a high resistance layer (substrate). 4 is an n-buffer short-circuit layer, and 2L _n
The anode region 2 is formed at a pitch equal to or less than (L _n is the diffusion length of electrons)
And the buffer layer 11 having a high impurity density is short-circuited. In FIGS. 1 and 2, the dotted line schematically shows the state of the depletion layer spreading in the n ⁻ layer (5, 12) by the n ⁺ (11) n ⁻ (12) junction. The width of the n ⁺ layer 11 is W _{n +} ,
The width of the n ⁻ layer 12 is W _B , the n ⁺ layer 11 or the n ⁻ layer 12 is
Is the thickness of L _B , the factors that determine the shape of the potential barrier in the n ⁻ layer 12 are the dimensions of W _B and L _B , and the n ⁺ layer 11
And the impurity density of the n ⁻ layer 12 and the impurity density of the anode region 2. By setting these parameters in the SI buffer structure, the n ⁻ layer 12 is substantially depleted. The low impurity density region 12 is shown in FIG. 1 as being of the same conductivity type as the high impurity density region 11, but may be of the opposite conductivity type of p ⁻ if it is substantially depleted, or It may be formed from the layer of the intrinsic region (i).

The dimension of L _B corresponds to the channel length, and W _B corresponds to the channel width. The holes injected from the anode region 2 mainly flow in the low impurity density region 12 determined by W _B and L _B , while the electrons injected from the cathode are accumulated in the high impurity density region 11 and 2L.
_It is electrically short-circuited with the anode region 2 through the buffer short-circuit regions 4 arranged at a pitch of _n (L _n is the diffusion length of electrons) or less.

[0019] With reference to FIG. 2, a potential change due to the electrons stored in the n ⁺ layer 11 and [Delta] V _n, n due to [Delta] V _n ^- When a change in the potential barrier layer in the ItaderutaV _n, from the anode region 2 The hole injection amount Δp of is relative to the amount Δn of the electrons accumulated in the n ⁺ layer 11 injected into the anode region 2.

[0020]

[Equation 1] It will be about.

Here, P _A is the impurity density of the anode region 2, n _B is the impurity density of the n ⁺ layer 11, v _P is the hole injection speed (diffusion or drift), and v _n is the electron injection speed (diffusion or diffusion). Drift), k is the Boltzen constant, T is the absolute temperature, and η is a value close to 1.

With respect to the value of ΔV _n , the diffusion potential between the n ⁺ layer 11 and the P anode layer 2 is V _GA, and the potential barrier height in the n ⁻ layer 12 seen by the holes in the anode region 2 is V _{G. * A}

[0023]

[Equation 2] You can also think of it.

Therefore, assuming that the current gain of hole injection for stored electrons in the SI buffer layer is η = 1,

[0025]

[Equation 3] Is.

Comparing this value with the conventional buffer structure, since V _GA = V _{G * A} in the conventional structure,

[0027]

[Equation 4] Therefore, the injection ratio is almost determined by diffusion.

[0028]

[Equation 5] Therefore, G _SI > G _C , and it can be said that the SI buffer structure has a much higher injection amount, and the on-voltage decreases correspondingly.

It is apparent that the hole injection rate is higher than that of the conventional buffer structure having the same size L _B , but in the SI buffer structure, the n ⁺ layer 11 has a mesh shape, a stripe shape, a plate shape, or the like. The layered resistance is substantially determined by the resistivity of the n ⁺ layer because it is formed in the. Therefore, the lateral resistance of the SI buffer layer is extremely small. This is because the electrons in the n ⁻ layer 12 easily reach the surrounding n ⁺ layer 11 by drifting and the resistance in the n ⁺ layer 11 is low. Comparing this with the conventional buffer structure, the n buffer layer has a base structure having a predetermined resistivity and does not have a region corresponding to a channel. Therefore, the electrons flow by diffusion in a predetermined resistivity in the n buffer layer.
Therefore, the resistance of the entire buffer layer is much lower in the SI buffer structure.

On the other hand, when the lifetime of the electron is long, the electron stays long in the n buffer layer, particularly in the n ⁺ layer 11. However, if it stays for too long, extra holes are injected by that amount, which causes a delay in the accumulation time and the tail time at turn-off. Therefore, it is necessary to devise to extract the electrons accumulated in the n ⁺ layer 11 while securing a certain amount of hole injection. As a structure therefor, the SI buffer structure adopts a structure in which the SI buffer is electrically short-circuited with the anode region 2 at a constant pitch. The pitch of the short-circuit, considering the diffusion length L _n that is determined by the electron lifetime, twice the L _n
The following may be done. As a result, the amount of holes injected from the anode region 2 can be secured, and the electrons accumulated with an appropriate time constant can be absorbed by the anode electrode 1.

A SI anode short structure has been conventionally proposed as an anode short structure utilizing the electrostatic induction effect. For example, Japanese Patent Application No. 62-250254 (Japanese Unexamined Patent Publication No.
No. 93169). The present invention is a structure in which the electrostatic induction effect is used for the n-buffer structure. In the present invention, since the buffer layer utilizing the electrostatic induction effect is provided, p ⁺ in is provided between the gate and the anode.
It is a combined structure of a ⁺ p ⁺ structure and a p ⁺ in ^- p ⁺ structure. the n ^- when a layer (12) is sufficiently depleted by the n ⁺ layer (11) is a depletion layer spreading from the gate region n ⁺ layer (11) n ^- comprises a layer (12) SI
The structure is such that it is blocked by the buffer layer and a sufficient strong electric field can be blocked. Of course, it is desirable that the dimensions of W _{n +} and L _B are as small as possible. n
^As described below, a metal layer may be used instead of the ⁺ layer 11. In this case, the Schottky junction will be used. However, a structure combined with a PN junction may be considered for high breakdown voltage.

Although it has been described that the SI buffer structure employs a structure that short-circuits with the anode region 2 at a pitch of 2L _n or less, the buffer short-circuit layer 4 can be omitted by performing lifetime control. . That is, the lifetime control of electrons is performed and the n ⁺ layer (11)
This is because the effect of the short-circuit layer 4 is weakened when the life of electrons near the n ⁻ layer (12) is set to a predetermined value and the life time is short. In this case, the buffer short-circuit layer 4 does not need to be positively formed, and a means for lifetime control may be provided. For example, irradiation of radiation such as irradiation of protons and irradiation of electron beams or diffusion of heavy metals is performed.

Although the principle, structure, and operation of the SI buffer structure have been clarified above, the SI buffer structure can be applied to various semiconductor devices. For example, SI thyristor, GTO, buried gate GTO, SCR, AS
CR, IGBT, MOS control thyristor, MOS control S
When a buffer structure is set in an I thyristor or the like and high speed operation due to high breakdown voltage and high electric field is required, high injection, high breakdown voltage, high speed turn-on, or high speed due to low resistivity, which cannot be obtained with the conventional buffer structure. Turn-off can be realized.

FIG. 3 is a schematic sectional structural view when the SI buffer structure according to the present invention is applied to a buried gate SI thyristor. The n-buffer short-circuit layer 4 is provided at a pitch of 2L _n or less. The SI buffer layer is an n ⁺ layer (1
1) and n ^- layer (12). n ⁺ layer (11) and n ⁻
The pitch of the layer (12) may correspond to the pitch of the buried gate region 6, and a structure in which the n ⁺ layer (11) is arranged immediately below the gate channel may be adopted. In FIG. 3, reference numerals are the same as those used in FIG. 13 of the conventional example and FIGS. 1 and 2 for explaining the principle of the SI buffer structure. The same applies to the following examples.

FIG. 4 shows a structure of the buried gate SI thyristor in which the n-buffer short-circuit layer 4 is provided in the anode side projection region below the gate electrode 10 in the structure in which the distance between the gate electrodes 10 is narrowed. Although the number of channels per unit segment is smaller than that of the structure shown in FIG. 3, it is miniaturized accordingly. The n-buffer short-circuit layer 4 is set to 2L _n or less.

FIG. 5 shows the n buffer shorting layer 4 and the n ⁺ layer 11
3 is an example of a plane pattern shape of the SI buffer layer including the n ⁻ layer 12. The n ⁺ layer 11 is short-circuited with the anode electrode 1 at the n-buffer shorting layer 4. The width and the impurity density of the n ⁻ layer 12 are set so as to be sufficiently depleted by the diffusion potential with the n ⁺ layer 11.

FIG. 5 shows an example in which the n buffer short-circuit layers 4 are arranged in a mesh shape, but FIG. 6 shows an example in which the n ⁺ short-circuit portions 4 are arranged at a constant pitch l _P. ing. An n ⁺ short-circuit region 4 is provided corresponding to the vertex of a regular hexagon or a regular triangle. The dimensions of l _P may be arranged so as to satisfy the about l _P <2L _n.

FIG. 7 shows the SI buffer structure according to the present invention as G
This is an example applied to a TO (gate turn-off thyristor). 13 is a P base layer, and 14 is a high-concentration base layer.
The n-buffer short-circuit layers 4 are arranged at a pitch of 2L _n or less.

FIG. 8 shows another example in which the SI buffer structure according to the present invention is applied to a buried gate SI thyristor. As a structural feature, the SI buffer structure is a P ⁺ gate 6
This is a point that is set to be wider by L _{n in the} projection portion on the anode side of. In consideration of the spread of electrons injected from the cathode side due to the transit time, the SI buffer structure is provided to be wide by about L _n .

FIG. 9 shows another example of the SI buffer structure. As compared with the configuration example of FIG. 1, a thin intervening layer n (15) is provided between the anode region 2 and the buffer layer (n ⁺ n ⁻ ). The role of the thin intervening layer 15 in the structure of FIG. 9 is to control the injection amount of holes from the anode region 2 by its impurity density and thickness. n ⁺ layer 11 and n ⁻ / p
^- a buffer layer comprising a layer 12 prevents the depletion layer mainly extending from the gate side, responsible for blocking a strong electric field, by setting the thickness and impurity concentration of the thin intermediate layer 15 to a predetermined value, hole injection The amount is controlled. The dimension corresponding to L _B in the structure of FIG. 1 substantially corresponds to the thickness of the thin intervening layer 15 in the structure of FIG. 16 is an insulating layer. 15
Is a thin intervening layer.

In the structure of FIG. 9, after the n ⁺ layer 11 is formed by diffusion,
This is realized by forming the thin intervening layer 15 by forming the n epitaxial layer and further forming the anode region 2 by forming the p epitaxial layer. The diffusion depth and diffusion pitch of the n ⁺ layer 11 may be formed relatively deep in order to prevent high breakdown voltage. The amount of holes injected is controlled by the thickness of the thin intervening layer, and it is desirable that the holes injected into the n ⁻ / p ⁻ layer 12 have a structure that drifts. Also in the structure of FIG. 9, the n-buffer short-circuit layer 4 is provided at a pitch of 2L _n or less to short-circuit the anode region 2.

FIG. 10 is a schematic sectional structural view of a planar gate SI thyristor to which the SI buffer structure shown in FIG. 9 is applied. The reference numbers for each component are the same as in the previous example.

FIG. 11 and FIG. 12 are structural examples in which the metal layer 17 is used instead of the n ⁺ layer 11 in the description of the above-mentioned embodiment. As the metal layer, a metal such as W, Mo, Co, Pt or the like, or a silicide thereof or the like can be applied. In FIG. 11, the short-circuit layer 4 is also made of these metals. The pitch of the short circuit is 2L _n or less. In FIG. 12, the anode region 2 and the SI buffer layer (17, 12)
An example in which a thin intervening layer 15 is provided between and is shown.
The short-circuit layer 4 is provided at a pitch of 2L _n or less.

[0044] SI buffer structure according to the present invention is not limited to the structure described above, for example n ^- structure with an n ⁺ layer that is embedded in the layer, or, p ^- n ⁺ layer plate in a layer It is also possible to have a structure provided in a shape.

It is also possible to further increase the pitch of the short circuit and arrange the short circuit layer 4 for each n ⁺ buried layer.

[0046]

Since the SI buffer structure according to the present invention can reduce the resistivity spreading in the lateral direction of the buffer layer, the accumulated electrons in the buffer layer are quickly discharged to the anode electrode, which results in a turn-off performance. improves.

By adopting the SI buffer structure,
Since holes are injected through the low impurity density layer,
The injection amount of holes is increased, the turn-on performance is improved,
Fast turn-on and on-voltage are reduced.

Since the high impurity density layer and the low impurity density layer are connected to each other by the depletion layer, a strong electric field can be blocked.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram of an SI buffer structure.

FIG. 2 is an explanatory diagram of a potential distribution of an SI buffer structure.

FIG. 3 is an example in which the SI buffer structure according to the present invention is applied to a buried gate SI thyristor.

FIG. 4 is an example in which the SI buffer structure according to the present invention is applied to a miniaturized embedded gate SI thyristor.

FIG. 5 is an example of a plane pattern of the SI buffer structure (11, 12) and the n buffer shorting layer (4).

FIG. 6 is a pattern arrangement example of an n buffer short-circuit region (4).

FIG. 7 is an example in which the SI buffer structure according to the present invention is applied to GTO.

FIG. 8 is another example in which the SI buffer structure according to the present invention is applied to a buried gate SI thyristor.

FIG. 9 is another configuration example of the SI buffer structure according to the present invention.

10 is a schematic cross-sectional structure diagram of a planar gate SI thyristor to which the SI buffer structure of FIG. 9 is applied.

FIG. 11 is an example of an SI buffer structure using a metal layer 17.

FIG. 12 is an example of the structure of FIG. 11 with a thin intervening layer 15.

FIG. 13: Buried gate S having a conventional n buffer layer
It is a structural example of an I thyristor.

[Explanation of symbols]

 1 Anode Electrode 2 Anode Region 3 Buffer Layer 4 n Buffer Short Layer 5 High Resistance Layer (Substrate) 6 Gate Region 7 Epitaxial Layer 8 Cathode Region 9 Cathode Electrode 10 Gate Electrode 11 High Impurity Density Buffer Layer 12 Low Impurity Density Buffer Layer 13 base layer 14 high concentration base layer 15 thin intervening layer 16 insulating layer 17 metal layer

Claims (5)

[Claims] 1. A semiconductor device having an anode region, a cathode region and a gate region, comprising a buffer layer in contact with or in the vicinity of the anode region, wherein the buffer layer comprises a high impurity density region and a low impurity density region. The low impurity density region is substantially depleted by a diffusion potential between the low impurity density region and the high impurity density region, and the buffer layer of the high impurity density region has a pitch of 2L _n or less with the anode region. A semiconductor device having an electrostatic induction buffer structure, wherein the semiconductor device is short-circuited by (L _n is an electron diffusion length). 2. The semiconductor device having the electrostatic induction buffer structure according to claim 1, wherein the buffer layer has a conductivity type opposite to that of the anode region. 3. The high impurity density region of the buffer layer has a conductivity type opposite to that of the anode region, and the low impurity density region has the same conductivity type as the anode region or an intrinsic semiconductor region. A semiconductor device having the electrostatic induction buffer structure according to claim 1. 4. A semiconductor device having an anode region, a cathode region and a gate region, comprising a buffer layer in contact with or in the vicinity of the anode region, the buffer layer having a metal layer region and a low impurity density region. However, the low impurity density region is substantially depleted by a diffusion potential between the low impurity concentration region and the metal layer, and the buffer layer in the metal layer region and the anode region have a pitch of 2L _n or less (L _n is an electron). A semiconductor element having an electrostatic induction buffer structure characterized by being short-circuited by the diffusion length of the. 5. A thin semiconductor layer having a conductivity type opposite to that of the anode region is interposed between the buffer layer and the anode region. A semiconductor device having the electrostatic induction buffer structure according to the paragraph.