JP3528393B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar normally-off vertical power device.

[0002]

2. Description of the Related Art As a conventional technique, a semiconductor device devised by the present inventor and disclosed in Japanese Patent Publication No. 6-252408 will be introduced. 9 is a perspective view for explaining the basic structure of the device, FIG. 10 is a sectional view showing the same part as the front surface of FIG. 9, FIG. 11 is a surface view of the device, and FIG. 12 is a same sectional view as the side surface of FIG.
For the sake of explanation, FIGS. 9 and 11 show a state in which the metal film as an electrode on the surface and the interlayer insulating film are removed.

First, the device structure will be described. Note that the names of each part are appropriately changed from those described in the above publication. In the above figure, the number 1 is an n ⁺ type substrate region, and the number 2 is n.
Type drain region, 3 is n ⁺ type source region, 4 is MO
S-type electrodes 5 are insulating films. The MOS type electrode 4 is made of high concentration p ⁺ type polysilicon. A drain electrode 11 is in ohmic contact with the substrate region 1. Thirteen
Is a source electrode, which is in ohmic contact with both the source region 3 and the MOS type electrode 4. That is, the MOS electrode 4 is fixed at the source potential. Therefore this MOS
Formed electrode 4 and insulating film 5 are combined to form "fixed potential insulating electrode" 6
Call. As shown in FIG. 10, the sectional structure of this fixed potential insulated electrode is formed in a groove whose side wall is substantially vertical like a letter "U".

Further, in FIG. 10, a fixed potential insulating electrode 6 is provided.
The drain region 2 sandwiched between the two is called a channel region 7. In the drain region 2 around the fixed potential insulating electrode 6,
In this state, a depletion region is formed from the MOS type electrode 4 by the electric field resulting from the work function difference. In the channel region 7 sandwiched by the fixed potential insulating electrodes 6, the depletion region forms a main current. A potential barrier is formed for the conduction electrons, and the source region 3 is left as it is.
And the drain region 2 are cut off. Since the structure of the channel region forms this potential barrier, the channel thickness H is made as small as possible, for example, H is 2 μm or less. Further, the channel length L shown in FIG. 10 is set to 2 to 3 times or more the channel thickness H so that the drain electric field does not affect the potential distribution near the source region. Furthermore, as shown in FIGS. 9 and 12, a p-type gate region 8 is present in contact with the insulating film 5 and away from the source region 3. In FIG. 12, reference numeral 18 denotes an electrode which makes ohmic contact with the gate region 8 and is called a “gate electrode”. Reference numeral 10 is an interlayer insulating film. Further, as can be seen from the relationship with FIG. 11, the “dashed line” in the figure shows the existence of the fixed potential insulated electrode in the depth direction of the paper surface.

Next, the operation will be described. In this element, for example, the source electrode 13 is grounded (at 0 V) and the drain electrode 1
3 is used by applying an appropriate positive potential via the load. First, when the gate electrode 18 is grounded, the device is in a cutoff state. In this state, the drain region 2
Has a depletion layer extending due to the positive drain potential, and a small amount of carriers are generated in the depletion layer. Among them, conduction electrons flow away to the drain electrode through the n ⁺ type substrate region 1, and holes reach the interface of the insulating film 6 on the surface.
However, if the potential of the insulating film interface rises as a result,
As it is, the potential barrier for electrons in the channel region lowers, but holes are in contact with this insulating film interface,
The gate electrode 1 is moved to the grounded p-type gate region 8.
Run off through 8. Therefore, holes do not stagnate in the channel region, and the element keeps the cutoff state.

Next, in the conductive state, the potential of the gate electrode 18, that is, the potential of the p-type gate region 8 is, for example, +0.5.
On the contrary to the above, when V is applied, holes flow from the p-type gate region 8 into the interface of the insulating film 6 in contact therewith to form an inversion layer, and raise the potential of the interface. Then, the holes block the lines of electric force from the MOS electrode 4 to the channel region 7, and lower the potential barrier height for conduction electrons in the channel region 7. That is, this brings the drain region 2 and the source region 3 into conduction. further,
When the potential of the gate electrode is raised, the pn junction composed of the p-type gate region 8 and the surrounding n-type region is forward biased, and holes are directly injected into the drain region 2 and the channel region 7. Then, in order to maintain the breakdown voltage, reduce the impurity concentration,
The conductivity of these n-type regions, which have been made to have a high resistance, is increased, and the current flows with a low resistance. Since the channel region 7 is used as a hole conduction path in this manner, the fixed potential insulating electrode 6 is formed in a stripe shape as shown in FIGS.

Next, in order to turn off this element, the positive potential applied to the gate electrode may be released and the grounded state or a negative potential may be applied. Then, the excess carriers in the drain region flow into the p-type gate region in reverse, and finally the excess carriers in the drain region and the channel region are exhausted, the potential barrier is restored in the channel region, and the main current is cut off. To be done.

However, the above structure has the following problems. That is, in order to efficiently reduce the on-resistance of the device, it is necessary to set a certain distance between the gate region and the source region. In the conductive state where the drain potential is extremely low, the holes injected from the p-type gate region 8 spread to the n ⁻ -type drain region 2 and evenly increase the conductivity thereof. If the distance between the two is too small, most of the holes injected into the n-type region will immediately flow into the n ⁺ -type source region 3 without reaching the drain region. On the contrary, if this distance is increased, the distance of the inversion layer formed at the interface of the insulating film becomes long at the time of turn-off, and the time for holes to flow through the inversion layer to the gate region becomes long.

[0009]

As described above, in the conventional structure, when the distance between the source region and the gate region is increased in order to efficiently reduce the on-resistance, the turn-off time tends to increase. there were. The present invention pays attention to such a problem, and an object thereof is to provide a current control element having a short turn-off time while maintaining good on-resistance characteristics of the element.

[0010]

In order to achieve the above object, the present invention has a structure as set forth in the claims. That is, in the invention according to claim 1, the drain region of one conductivity type (for example, n
Type) semiconductor substrate in contact with one main surface of the same conductivity type (n type)
A source region, and has a first groove arranged in contact with the main surface so as to sandwich the source region, the side wall of the groove is formed substantially perpendicular to the main surface, Inside, there is a first insulating electrode insulated from the drain region by a first insulating film, and the first insulating electrode has a depletion region in the drain region adjacent to the drain region through the first insulating film. A conductive material with a work function such as forming (eg p
⁺ Type polysilicon) and is kept at the same potential as the source region. In addition, a part of the drain region in contact with the source region has a channel region sandwiched by the first insulating electrode, and the channel region is formed around the first insulating electrode. A potential barrier that blocks the movement of majority carriers (conduction electrons here) is formed by the depletion region, and the electric field from the drain region side in the cutoff state does not affect the vicinity of the source region. The distance from the bottom of the first groove to the source region in the channel region, that is, the channel length, is at least 2 of the distance between the sidewalls of the first groove facing each other in the channel region, that is, the channel thickness. To 3 times or more. Further, minority carriers (here, holes) are supplied to the interface of the first insulating film surrounding the first insulating electrode to form an inversion layer, and an electric field from the first insulating electrode to the drain region is formed. Of the opposite conductivity type, which is in contact with the first insulating film and the drain region but not the source region, in order to reduce or eliminate the potential barrier formed in the channel region to open the channel by shielding and a gate electrode electrically connected to the gate region. Further, the channel region in contact with the main surface has an off-gate region of an opposite conductivity type (p-type) that is not in contact with at least the gate region, and the off-gate region has an opposite conductivity type by a metal electrode. A structure in which the anode region is connected to a (p-type) anode region, the anode region is connected to a cathode region of the same conductivity type (n-type) to form rectifying matching, and the cathode region is electrically connected to the gate electrode. And

Further, in the invention of the second aspect, as one means for embodying the invention of the first aspect, a second groove is provided in contact with the main surface, and a second insulation is provided inside thereof. The anode region and the cathode region are provided through a film. By the way, this corresponds to the semiconductor device shown in FIGS.

Further, in the invention described in claim 3, as another means for embodying the invention of claim 1,
A second semiconductor region is provided on the main surface via a third insulating film, and the anode region and the cathode region are provided therein. Incidentally, this corresponds to the semiconductor device shown in FIG. 7, which will be described later.

Further, in the invention according to claim 4, in addition to the structure according to claim 1, the gate region is in contact with both ends of the first groove, and the two first regions are in contact with the main surface. The off-gate region is located in a region sandwiched by the sidewalls of one groove and surrounded by two junctions formed by the gate region and the channel region, and at a substantially equal distance from the two junctions. And has the source region between the off-gate region and the gate region. Incidentally, this corresponds to the semiconductor device shown in FIG. 8 described later.

[0014]

First, when the configuration described in claim 1 is adopted,
When a positive potential is applied to the gate electrode to make the device conductive, minority carriers (holes) are injected from the gate region (here, p-type) into the drain region and the channel region, the channel region is opened, and the source region is opened. Majority carriers (conduction electrons) flow from the drain to the drain region. At this time, the pn junction formed by the anode region and the cathode region is reverse-biased, so that no current flows back and forth through the off-gate region connected to the anode region.

When the potential of the gate electrode is made negative in order to turn the element to the cutoff state, the minority carriers (holes) accumulated in the drain region flow into the gate region of opposite conductivity type (p type). At this time, the pn junction formed by the cathode region and the anode region is forward-biased, and excess minority carriers existing in the vicinity of the source region are quickly removed from the vicinity of the source region through the off-gate region. Is shortened.

Next, according to the second aspect of the present invention, since the cathode region and the anode region are formed in the groove having the same shape as the fixed potential insulating electrode, the chip region can be saved.

According to the third aspect of the present invention, the cathode region and the anode region are formed on the second semiconductor region on the chip surface, which is insulated, for example, a film-like polysilicon region. The present invention can be easily realized.

Next, according to the invention described in claim 4, by providing the source region avoiding a point equidistant from the two p-type gate regions in contact with the channel region, particularly when driving an inductive load, The main current that tends to concentrate in the center of the channel region during the turn-off is quickly cut off,
Moreover, by providing the off-gate region in the central portion, holes which are concentrated current components can be removed quickly, turn-off time can be shortened, and the current value at which the element can be turned off can be increased.

[0019]

The present invention will be described in detail with reference to the drawings.

[First Embodiment] First, a first embodiment of the present invention will be described with reference to FIGS. It should be noted that this embodies claims 1 and 2. 1 is a bird's-eye view of a semiconductor device according to a first embodiment of the present invention,
2 is the same sectional view as the front surface of FIG. 1, FIG. 3 is the same surface view as the upper surface of FIG. 1, and the sectional view taken along line AA in FIG. 2 is FIG. Figure 4
3 is the same sectional view as the side surface of FIG. 1, and FIG. 5 is a sectional view taken along line BB in FIG. Note that, in FIGS. 1 and 3, for the sake of explanation, a state in which the metal film as the surface electrode, the interlayer insulating film, and the like are removed is drawn.

The structure will be described. 1 to 4, reference numeral 1 is an n ⁺ type substrate region, 2 is an n type drain region, 3 is an n ⁺ type source region, 4 is a MOS type electrode, and 5 is an insulating film. The MOS type electrode 4 is made of high concentration p ⁺ type polysilicon. A drain electrode 11 is in ohmic contact with the substrate region 1. 13 is a source electrode,
The source region 3 and the MOS electrode 4 are in ohmic contact. That is, the MOS electrode 4 is fixed at the source potential. Therefore, the MOS type electrode 4 and the insulating film 5 are collectively referred to as "fixed potential insulating electrode" 6.

As shown in FIGS. 1 and 2, the sectional structure of this fixed potential insulated electrode is formed in a groove whose side wall is substantially vertical like a letter "U". Further, the drain region 2 sandwiched between the fixed potential insulating electrodes 6 is called a channel region 7. In this state, a depletion region is formed in the drain region 2 around the fixed potential insulating electrode 6 from the MOS type electrode 4 due to the electric field due to the work function difference. Channel region 7
At this point, a potential barrier is formed by the depletion region for conduction electrons that form the main current, and the source region 3 and the drain region 2 are in a cutoff state as they are.

Since the structure of the channel region forms this potential barrier, the channel thickness H in FIG. 2 is made as small as possible, for example, H is 2 μm or less.
Further, the channel length L shown in FIG. 2 is set to 2 to 3 times or more the channel thickness H so that the drain electric field does not affect the potential distribution near the source region. further,
As shown in FIGS. 1 and 4, a p-type gate region 8 exists in a position in contact with the insulating film 5 and away from the source region 3. In FIG. 4, reference numeral 18 denotes an electrode which makes ohmic contact with the gate region 8 and is called a “gate electrode”. Reference numeral 10 is an interlayer insulating film. Further, as can be seen from the relationship with FIG. 3, the “dashed line” in the figure shows the existence of the fixed potential insulated electrode in the depth direction of the paper surface.

Up to this point, the configuration is the same as that of the conventional example.
Further, in the present embodiment, as shown in FIGS. 1 and 4, a p ⁺ type off-gate region 40 is provided, and a p-type anode region 44 is further provided in the second groove via an insulating film 55.
Then, it has an n-type cathode region 48 therein, and the cathode region 48 is in ohmic contact with the gate electrode 18. 4 and 5, the number 9 is off.
It is a bypass electrode that connects the gate region 40 and the p-type anode region 44.

In this embodiment, the anode region 44 is used.
Although the groove in which is present is formed in the same shape as the fixed potential insulating electrode 6, the source region 3 is not formed between the fixed potential insulating electrode 6 and the second groove. Further, FIG. 5 shows the anode region 4
4 is a cross-sectional view showing the configurations of 4 and a cathode region 48. FIG. In the figure, the bypass electrode 9 is in ohmic contact with the cathode region 44. Further, the p-type gate region indicated by number 8 is in contact with the gate electrode 18 in another region as shown in FIG.

The operation will be described. In this device, for example, the source electrode 13 is grounded (at 0 V), and the drain electrode 13 is used by giving an appropriate positive potential via a load. First,
When the gate electrode 18 is grounded, the device is in the cutoff state. In this state, a depletion layer extends in the drain region 2 due to this drain potential, and a small amount of carriers are generated in the depletion layer. Among them, conduction electrons are n ⁺
After passing through the mold substrate region 1 to the drain electrode, the holes reach the interface of the insulating film 6 on the surface. However, if the potential at the interface of the insulating film rises as a result, the potential barrier for electrons in the channel region lowers as it is, but holes move to the grounded p-type gate region 8 where the interface of the insulating film contacts. It flows away through the gate electrode 18. Therefore, holes do not stagnate in the channel region, and the element keeps the cutoff state.

Next, in the conductive state, first, the gate electrode 1
8 to the potential of the p-type gate region 8, for example, +
On the contrary to the above, when 0.5 V is applied, holes flow from the p-type gate region 8 to the interface of the insulating film 6 in contact therewith to form an inversion layer, and from the MOS-type electrode 4 to the channel region 7. The lines of electric force are shielded, and as a result, the potential at the interface of the insulating film is raised, and the potential barrier height for conduction electrons in the channel region 7 is lowered. That is, this brings the drain region 2 and the source region 3 into conduction.

When the potential of the gate electrode is further raised, the pn junction composed of the p-type gate region 8 and the peripheral n-type region is forward biased, and holes are directly injected into the drain region 2 and the channel region 7. It Then, in order to maintain the breakdown voltage, the impurity concentration is made thin and these n
The conductivity of the mold region is increased, and the current flows with low resistance. Since the channel region 7 is used as a hole conduction path in this manner, the fixed potential insulating electrode 6 is formed in a stripe shape as shown in FIG. 1 or 2. In this state, the pn junction between the p-type anode region 44 and the n-type cathode region 48 is in a reverse bias state, so no holes are injected from the p-type off-gate region. Since the positive potential applied to the gate region is at most 1 V inside and outside, even if the p-type anode region 44 and the n-type cathode region 48 are made of polysilicon, they sufficiently function.

In order to allow the main current to flow efficiently, that is, with a low gate current and a low resistance, the injected holes must be evenly distributed to the drain region for conductivity modulation. For that purpose, the distance between the gate region and the source region must be separated to some extent. As an example, this distance is about the distance from the source region to the substrate region. If this distance is too short, most of the injected holes immediately flow into the source region having a low potential, and the so-called current amplification factor decreases.

Next, in order to turn off this element, the positive potential applied to the gate electrode may be released and the grounded state or a negative potential may be applied. Then, the excess carriers in the drain region flow into the p-type gate region in reverse, and finally the excess carriers in the drain region and the channel region are depleted, the potential barrier in the channel region is restored, and the main current is restored again. Be cut off.

Now, the behavior of excess holes in the drain region and the channel region at the time of turn-off will be described. In the conductive state immediately before the turn-off, excess holes are injected from the p-type gate region 8 into the drain region and the channel region, and are generally in a high injection level state. Once the potential of the gate electrode changes from positive to negative,
On the contrary, the excess holes are sucked into the p-type gate region 8,
The concentration gradually decreases from its vicinity. When the supply of holes is stopped in the channel region and the hole density is reduced, the holes form an inversion layer at the interface of the insulating film, and then flow through the inversion layer into the p-type gate region. .

FIG. 6 is a three-dimensional graph in which the potential distribution in the vicinity of the junction between the channel region and the p-type gate region 8 is calculated. The position shown is the channel region, and the line segment C in FIG.
Is a plane sliced in parallel with the element surface along the vertical axis, and the vertical axis is the potential for electrons in the channel region, and the negative potential increases upward. The side in the front of the figure corresponds to the channel region immediately below the source region, but the potential for conduction electrons has already become high and depleted over the entire region, that is, the channel is in the cutoff state. A negative potential of -10V is applied to the gate region. If it is a normal one-dimensional pn junction, p
Although the electric field of the type gate region 8 reaches a few 10 μm on the side of the n ⁻ region, in the case of the present invention, the n ⁻ region of the channel region is affected by the grounded p ⁺ type MOS type electrodes so that the n ⁻ region is separated from the junction. At most, the channel thickness (for example, 2 μm) is reached. That is, in the semiconductor device of the present invention,
Even if the gate electrode has a negative potential, the effect is normal JFET
As described above, the holes do not reach the source region in a straightforward manner, and the movement of holes in the channel region depends on the concentration gradient of carriers in the inversion layer. Therefore, the movement of carriers in the channel region is not in the bulk region having high resistance, but in the inversion layer having relatively low resistance. However, if the distance is long, it takes a relatively long time to reduce the hole concentration in the vicinity of the source region.

Therefore, in this embodiment, the p-type off-gate electrode 40 is provided at a distance closer to the source region than the distance between the source region and the gate region. When a negative potential is applied to the gate electrode, the pn junction between the p-type anode region 44 and the n-type cathode region 48 is forward biased.
Excess holes in the channel region 7 also flow through the path of the p-type off-gate region 40 → the bypass electrode 9 → the p-type anode region 44 → the n-type cathode region 48 → the gate electrode 18, so that the source region can be more quickly formed. An effect that holes in the vicinity can be eliminated is obtained. Further, since the off-gate region 40 does not function at all during conduction, it may be in contact with the source region 3.

Further, as in the present embodiment, the p-type anode region 44 and the n-type cathode region 48 are formed in the groove having the same shape as the fixed potential insulating electrode 6. Such a structure has an advantage that it can be realized without increasing the number of manufacturing steps of the device. For example, the off-gate region 40 forms a high concentration region (not shown) for making ohmic contact between the p-type gate region 8 and the gate electrode 18, and n
The formation of the type cathode region can be performed simultaneously with the formation of the n ⁺ type source region 3.

[Second Embodiment] Next, FIG. 7 is a bird's-eye view for explaining a second embodiment of the present invention. This corresponds to claim 3. This is p-type anode region 44 and n
The cathode region 48 and the interlayer insulating film 10 on the surface of the device.
It is realized by a polysilicon film newly formed on the above. The polysilicon film can be formed by the CVD method, but needless to say, it may be a single crystal silicon film formed by another method. In this way, the same effect can be easily realized by simply adding to the structure of FIG. 1 of the conventional example. Also,
Impurity conditions for the p-type anode region 44 and the n-type cathode region 48 can be set independently of the parameters of other semiconductor regions.

[Third Embodiment] FIG. 8 shows a third embodiment of the present invention. This corresponds to claim 4. FIG. 8 is a side view corresponding to FIG. This embodiment is characterized by the positions of the source region and the off gate region. Off gate area is just 2
It is located at the midpoint of the two gate regions and the source region is located away from that location. This is mainly for driving an inductive load. When the semiconductor device cuts off the current in the circuit driving the resistive load, the drain potential rises symmetrically with the decrease in the main current, but if the circuit driving the inductive load tries to cut off the current, the inductive load Since it has the property of holding the current value, the drain potential first rises to near the power supply voltage, and then the current drops. During this period, first, in the semiconductor, excess carriers disappear from the vicinity of the p-type gate region 8 and the resistance gradually increases, so that the current concentrates in a region equidistant from the gate region. However, since the total current value does not decrease, a very high current density is locally concentrated in this area.

The current value drops only when the depletion layer is formed in the drain region to collect the electric charge which constitutes the main current and the electric current cannot be collected. Therefore, by arranging the off-gate region in the region where this current is finally concentrated and quickly lowering the conductivity around this region, it is possible to turn off the main current even earlier. Further, when the current value and the drain voltage at the time of cutoff become high to some extent, a high-density current travels in a region having a steep potential gradient at the moment of turn-off, carrier pair generation occurs, and holes opening the channel are generated. It is supplied and it is difficult to turn off. However, in the present embodiment, since the off-gate region is arranged in a portion where the hole current reaches the channel region and is excluded, the reached hole does not pass through the channel region in front of the source region,
The channel is shut off quickly. That is, it is possible to widen the so-called reverse bias safe operation area (RBSOA) of the device. The distance between the source region and the off-gate region may be equal to or longer than the channel length L.

[0038]

As described above, according to the present invention, excess minority carriers eliminated at turn-off can be quickly removed without impairing other characteristics of the device, and the turn-off time of the device can be shortened. Can be done.

Further, according to the first embodiment, in addition to the above basic effects, the anode region and the cathode region are formed in the groove formed in the same step as the fixed potential insulated electrode, It saves the chip area and can be manufactured without adding a new manufacturing process.

Further, according to the second embodiment, in addition to the basic effects described above, the anode region and the cathode region can be easily realized by forming them in the film-shaped semiconductor region formed on the surface. it can. Furthermore, these formation parameters can be set independently of the manufacturing parameters of other structures.

Further, according to the third embodiment, in addition to the above basic effects, it is possible to widen at least the reverse bias safe operation area (RBSOA) when driving an inductive load.

[Brief description of drawings]

FIG. 1 is a bird's-eye view illustrating a first embodiment of the present invention.

FIG. 2 is the same sectional view as the front surface of FIG.

FIG. 3 is the same surface view as the top surface of FIG.

4 is the same cross-sectional view as the side surface of FIG.

5 is a cross-sectional view taken along the line BB in FIG.

FIG. 6 is a graph illustrating a potential distribution in a channel region.

FIG. 7 is a side view illustrating a second embodiment of the present invention.

FIG. 8 is a side view explaining a third embodiment of the present invention.

FIG. 9 is a bird's-eye view illustrating a conventional example.

10 is the same cross-sectional view as the front surface of FIG.

FIG. 11 is the same cross-sectional view as the top surface of FIG.

FIG. 12 is the same cross-sectional view as the side surface of FIG.

[Explanation of symbols]

1 ...... n ⁺ -type substrate region 11 · · drain electrode 2 ...... n ^- -type drain region 3 ...... n ⁺ -type source region 4 ... ..P.sup. ⁺ Type MOS electrode 44..p type anode region 48..n type cathode region 5, 55..insulating film 6..fixed potential insulating electrode 7 .. Channel region 8 P-type gate region 18 Gate electrode 9 Bypass electrode 10 Interlayer insulating film L ... Channel length H ... Channel thickness

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 301G 658H

Claims (4)

(57) [Claims] 1. A source region of the same conductivity type is in contact with one main surface of a semiconductor substrate of one conductivity type which is a drain region, and a first region is arranged in contact with the main surface so as to sandwich the source region. And a sidewall of the first groove is formed substantially at a right angle to the main surface, and the inside of the first groove is insulated from the drain region by a first insulating film. A first insulating electrode, the first insulating electrode is made of a conductive material having a work function such that a depletion region is formed in the drain region adjacent to the first insulating film, The first insulated electrode is kept at the same potential as the source region, is a part of the drain region in contact with the source region, and has a channel region sandwiched by the first insulated electrode, In the channel region of the first insulated electrode A potential barrier that blocks the movement of majority carriers is formed by the depletion region formed in the enclosure, and the channel region is formed so that the electric field from the drain region side in the cutoff state does not affect the vicinity of the source region. And the distance from the bottom of the first groove to the source region, that is, the channel length, is at least 2 to 3 times the distance between the sidewalls of the first groove facing each other in the channel region, that is, the channel thickness. Further, minority carriers are supplied to the interface of the first insulating film surrounding the first insulating electrode to form an inversion layer, and an electric field from the first insulating electrode to the drain region is formed. To open the channel by blocking or blocking the potential barrier formed in the channel region and opening the channel. A semiconductor device having a gate region of an opposite conductivity type that is in contact with the drain region and not in contact with the source region, and has at least a gate electrode electrically connected to the gate region, wherein the semiconductor device is in contact with the main surface. In the channel region, between the gate region and the source region, there is at least an off-gate region of opposite conductivity type that is not in contact with the gate region, and the off-gate region is of opposite conductivity type due to a metal electrode. A semiconductor device, which is connected to an anode region, the anode region is connected to a cathode region of the same conductivity type to form a rectifying junction, and the cathode region is electrically connected to the gate electrode. . 2. A second groove is provided in contact with the main surface, and the inside of the second groove has the anode region and the cathode region with a second insulating film interposed therebetween. The semiconductor device according to claim 1, wherein 3. A third insulating film is provided in contact with the main surface, and in a second semiconductor region formed on the third insulating film,
The semiconductor device according to claim 1, comprising the anode region and the cathode region. 4. The gate region is in contact with both ends of the first groove, is in contact with the main surface, and is sandwiched between two sidewalls of the first groove, and the gate region and the channel region. The off-gate region is located in a region surrounded by two junctions formed by the two junctions, and the region is substantially equidistant from the two junctions, and the off-gate region is provided between the off-gate region and the gate region. The semiconductor device according to claim 1, further comprising a source region.