JP2007173675A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor device for improving resistance to short-circuiting and also inhibiting occurrence of an avalanche phenomenon. <P>SOLUTION: The semiconductor device 10 includes an electric field retention region 38 in which a depletion layer is formed when the device is turned OFF between a pair of main electrodes. The electric field retention region 38 includes, in a plane perpendicular to the direction between the pair of main electrodes, a first partial region 34 with a relatively high carrier concentration and a second partial region 32 with a relatively low carrier concentration. Thus, the occurrence of the avalanche phenomenon can be inhibited while improving the resistance to short-circuiting. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes. The present invention also relates to a method for manufacturing such a semiconductor device.

  Generally, a semiconductor device includes an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes. For example, a vertical IGBT (Insulated Gate Bipolar Transistor) includes a base region (an example of an electric field holding region) containing an n-type impurity between a collector electrode on the back surface and an emitter electrode on the front surface. A vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) includes a drift region (an example of an electric field holding region) containing n-type impurities between a drain electrode on the back surface and a source electrode on the front surface.

  Non-Patent Document 1 proposes an IGBT in which the base region is made i-type by reducing the impurity concentration of the base region. By making the base region i-type, the strength of the electric field extending in the thickness direction of the base region is made uniform over the entire base region. For this reason, even if the thickness of the base region is reduced, the base region can hold a large number of electric fields, and a necessary breakdown voltage can be ensured. In other words, the IGBT of Non-Patent Document 1 can shorten the current path by reducing the thickness of the base region while ensuring the necessary breakdown voltage. The IGBT of Non-Patent Document 1 can improve the trade-off relationship between breakdown voltage and on-voltage. Furthermore, even when an external load connected to the semiconductor device is short-circuited and a high voltage / high current is applied to the semiconductor device, the intensity of the electric field extending in the thickness direction of the base region is uniform, so It can be distributed throughout the base region. Thereby, as for IGBT of nonpatent literature 1, destruction at the time of a short circuit is controlled, and short circuit tolerance is improving.

H.Ruething, F.Umbach, O.Hellmund, P.Kanschat, G.Schmidt, "600V-IGBT3: Trench Field Stop Technology in 70μm Ultra Thin Wafer Technology", Proceedings of the 15th ISPSD, pp.63-66, 2003

  If the entire base region is i-type, as in the IGBT of Non-Patent Document 1, most of the base region is depleted in the off state. The base region of the IGBT is sandwiched between a p-type collector region formed on the back surface and a p-type body region formed on the front surface. For this reason, the IGBT of Non-Patent Document 1 has a problem that in the off state, the parasitic bipolar due to the p-type collector region / i-type base region / p-type body region easily operates. In particular, if the entire base region is i-type, the entire base region is in a high electric field state, so that the parasitic bipolar is easily operated. As a result, the current amplified by the parasitic bipolar promotes the occurrence of the avalanche phenomenon and causes the semiconductor device to be destroyed.

The structure in which the electric field holding region is i-type can also be applied to a vertical MISFET. In this case, the entire drift region is i-type. However, if the entire drift region is i-type, when high voltage and high current are applied, the electric field strength in the vicinity of the drain region increases, which promotes the occurrence of the avalanche phenomenon and causes the breakdown of the semiconductor device. End up.
The phenomenon that the breakdown phenomenon of the semiconductor device increases when the entire electric field holding region is i-type is not limited to the vertical IGBT and the vertical MISFET. This type of problem exists in common in semiconductor devices such as lateral IGBTs, MISFETs, and PIN diodes. Further, this kind of problem exists in either the trench type gate electrode or the planar type gate electrode regardless of the structure of the gate electrode.
An object of this invention is to implement | achieve the technique which improves a short circuit tolerance and also suppresses generation | occurrence | production of an avalanche phenomenon.

The present invention provides a technique for realizing both improvement of short-circuit resistance and suppression of occurrence of an avalanche phenomenon by making a part of the electric field holding region i-type. In the semiconductor device of Non-Patent Document 1, the short-circuit resistance is improved by making the entire electric field holding region i-type. However, if the entire electric field holding region is i-type, the occurrence of the avalanche phenomenon is promoted. In the semiconductor device of the present invention, part of the electric field holding region is i-type. Thereby, the semiconductor device of this invention can improve short circuit tolerance, suppressing generation | occurrence | production of an avalanche phenomenon.
Here, terms used in this specification will be described. As used herein, “i-type” refers to “a low carrier concentration” and is interpreted in a broad sense. The “state where the carrier concentration is low” means “a state where the concentration of impurities contributing to carriers is low”. In this specification, “i-type”, “a state where the carrier concentration is low”, and “a state where the energy level concentration of the impurity is low” are interpreted in the same meaning. In this specification, the term “carrier concentration” is mainly used. The semiconductor region that realizes the “state of low carrier concentration” can be in many states. For example, even if the concentration of the introduced impurity is high, a low carrier concentration state can be realized if the activated impurity is small. Alternatively, even if the concentration of the introduced impurity is high, if the concentration of the energy level of the impurity is reduced due to the defect level, a state where the carrier concentration is low can be realized. Of course, a low carrier concentration state can be realized by the low concentration of the introduced impurity. Therefore, the “state with a low carrier concentration” referred to in this specification means (1) a state in which there are few activated impurities, (2) a state in which the concentration of energy levels of impurities is low due to defect levels, (3) In the first place, there are those that can be realized in a state where the concentration of impurities is low, or by using other methods easily conceived by those skilled in the art.

The present invention can be embodied in a semiconductor device including an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes. The electric field holding region includes a first partial region having a high carrier concentration and a second partial region having a low carrier concentration in a plane perpendicular to the direction between the pair of main electrodes. The electric field holding region includes a first partial region extending in the direction between the pair of main electrodes and a second partial region extending in the direction between the pair of main electrodes. For example, the first partial region is a region having a high donor level concentration. The second partial region is a region having a low donor level concentration.
The first partial region is adjusted to have a high carrier concentration. For this reason, when the semiconductor device is turned off, the first partial region can suppress the extension of the depletion layer. When the extension of the depletion layer is suppressed, for example, the parasitic bipolar or diode is suppressed from being turned on. Therefore, the occurrence of the avalanche phenomenon is also suppressed.
In the second partial region, the carrier concentration is adjusted to be thin. Therefore, the intensity of the electric field extending in the thickness direction of the second partial region is made uniform. For this reason, in the semiconductor device of the present invention, even if an external load connected to the semiconductor device is short-circuited and a high voltage / high current is applied to the semiconductor device, the second partial region, and thus the entire electric field holding region is covered. The heat generating area can be dispersed. Thereby, the semiconductor device of the present invention is prevented from being destroyed at the time of short circuit, and the short circuit tolerance is improved.
The semiconductor device of the present invention can suppress the occurrence of the avalanche phenomenon while improving the short-circuit tolerance.

In the semiconductor device of the present invention, the combination of the first partial region and the second partial region is preferably repeatedly formed in at least one direction within a plane orthogonal to the direction between the pair of main electrodes. If the first partial region and the second partial region are formed in a thin plate shape, the combination of the first partial region and the second partial region is repeated in one direction. If the first partial region and the second partial region are formed in a quadrangular prism shape, a hexagonal column shape, or other shapes, the combination of the first partial region and the second partial region is repeated in a plurality of directions.
According to the above aspect, the first partial region and the second partial region are formed in a distributed manner in the electric field holding region. Thereby, the semiconductor device of the said form can acquire effectively the effect which improves a short circuit tolerance, and the effect which suppresses generation | occurrence | production of an avalanche phenomenon.

  The present invention can be embodied in a vertical IGBT. The semiconductor device of the present invention includes an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes. The semiconductor device of the present invention is formed on a first main electrode, a collector region formed on the first main electrode, a semiconductor region formed on the collector region, and the semiconductor region. A body region, an emitter region separated from the semiconductor region by the body region, and a second main electrode electrically connected to the emitter region are provided. The collector region contains a first conductivity type impurity. The body region contains a first conductivity type impurity. The emitter region contains a second conductivity type impurity. The semiconductor device of the present invention further includes a trench gate electrode. The trench gate electrode penetrates the body region and faces the body region that separates the semiconductor region and the emitter region via a gate insulating film. The semiconductor region of the present invention has an electric field holding region. In the present invention, the electric field holding region includes a first partial region having a high second conductivity type carrier concentration and a second partial region having a low second conductivity type carrier concentration in a plane orthogonal to the direction between the pair of main electrodes. It is characterized by having.

  In the vertical IGBT of the present invention, the semiconductor region preferably further includes a buffer region having a high carrier concentration of the second conductivity type. The buffer region is formed between the collector region and the electric field holding region. This form of semiconductor device is referred to as a punch-through type. The vertical IGBT of the present invention can be embodied in either a punch-through type or a non-punch-through type.

In the vertical IGBT of the present invention, it is preferable that the collector region is formed in a distributed manner on the first main electrode. Furthermore, it is preferable that the semiconductor region is in contact with the first main electrode through the dispersed collector regions.
According to the semiconductor device of the above aspect, the carriers accumulated in the semiconductor region when being turned off are quickly discharged to the first main electrode. Therefore, the semiconductor device of the above embodiment can improve the switching speed.

  The present invention can be embodied in a vertical MISFET. The semiconductor device of the present invention includes an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes. A semiconductor device of the present invention is formed on a first main electrode, a drain region formed on the first main electrode, a semiconductor region formed on the drain region, and the semiconductor region. A body region, a source region separated from the semiconductor region by the body region, and a second main electrode electrically connected to the source region are provided. The drain region contains a second conductivity type impurity. The body region contains a first conductivity type impurity. The source region contains a second conductivity type impurity. The semiconductor device of the present invention further includes a trench gate electrode. The trench gate electrode penetrates the body region and faces the body region that separates the semiconductor region and the source region via a gate insulating film. The semiconductor region of the present invention has an electric field holding region. In the present invention, the electric field holding region includes a first partial region having a high second conductivity type carrier concentration and a second partial region having a low second conductivity type carrier concentration in a plane perpendicular to the direction between the pair of main electrodes. It is characterized by having.

In the vertical IGBT and MISFET of the present invention, the concentration of the second conductivity type impurity introduced into the first partial region and the concentration of the second conductivity type impurity introduced into the second partial region are substantially equal. Also good.
In this case, the difference in carrier concentration between the first partial region and the second partial region is formed due to the defect level. A structure in which a difference in carrier concentration between the first partial region and the second partial region is formed due to the defect level is a novel and novel structure.

In the vertical IGBT and MISFET of the present invention, the first partial region preferably extends from the front surface to the back surface of the electric field holding region. It is preferable that the second partial region also extends from the front surface to the back surface of the electric field holding region.
According to this aspect, a structure including the first partial region and the second partial region can be obtained in the plane orthogonal to the direction between the pair of main electrodes over the entire electric field holding region. According to this aspect, it is possible to effectively obtain the effects of improving the short-circuit resistance and suppressing the avalanche phenomenon.

In the vertical IGBT and MISFET of the present invention, the second partial region is preferably in contact with the junction interface between the electric field holding region and the body region. More preferably, the second partial region is in contact with the entire surface of the junction interface between the electric field holding region and the body region.
According to this embodiment, when the external load connected to the semiconductor device is short-circuited, a high current can be passed through the second partial region. Since the carrier concentration of the second partial region is adjusted to be thin, the strength of the electric field extending in the thickness direction of the second partial region is made uniform. Therefore, even if a high voltage and a high current are applied to the semiconductor device, the heat generating region can be dispersed over the entire second partial region.

In the vertical IGBT and MISFET of the present invention, the electric field holding region preferably further includes a third partial region having a low carrier concentration of the second conductivity type. The third partial region is formed over the entire back surface portion of the electric field holding region.
According to this embodiment, the breakdown voltage of the semiconductor device can be improved.

In the vertical IGBT and MISFET of the present invention, the first partial region is preferably in contact with the bottom surface and the side surface of the trench gate electrode.
According to the semiconductor device of this embodiment, the side surface of the trench gate electrode and the first partial region can be made continuous. Therefore, when the semiconductor device is turned on, carriers that move along the side surface of the trench gate electrode can move between the first main electrode and the second main electrode via the first partial region. The semiconductor device of this mode can obtain a low on-voltage or on-resistance.

The present invention can be embodied in a method for manufacturing a semiconductor device having an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes. The manufacturing method of the present invention includes a step of providing a mask in which a plurality of openings are formed facing the surface of a semiconductor substrate containing impurities, and a step of implanting charged particles toward the semiconductor substrate through the openings of the mask (hereinafter referred to as the following steps). Abbreviated as a driving step). In the manufacturing method of the present invention, the first partial region having a high carrier concentration and the second carrier concentration having a low carrier concentration in the semiconductor substrate are deactivated by inactivating part of the impurities introduced into the region through which the charged particles have passed. An electric field holding region having a partial region is formed.
When this manufacturing method is used, the first partial region and the second partial region extending from the front surface to the back surface of the electric field holding region can be formed.

In the implantation process, protons can be used for the charged particles. In this case, in the implantation step, by performing a heat treatment after implanting the charged particles, a part of the impurities introduced into the region through which the charged particles have passed is inactivated, the carrier concentration is lowered, and the semiconductor substrate The carrier concentration is increased by charged particles accumulated in the deep part of the substrate.
When this manufacturing method is used, a region in which the carrier concentration is adjusted to be deep can be formed under the electric field holding region at the same time as the electric field holding region is formed. For example, when the above manufacturing method is used for a punch-through vertical IGBT, the electric field holding region and the buffer region can be formed simultaneously.

In the implantation step, when protons are used for the charged particles, it is preferable to implant protons at 1 × 10 ¹³ cm ⁻² or more.
When protons are implanted under the above conditions, a part of impurities introduced into the region through which protons have passed can be inactivated and the carrier concentration can be lowered.

  The semiconductor device of the present invention includes an electric field holding region having a first partial region having a high carrier concentration and a second partial region having a low carrier concentration in a plane orthogonal to the direction between the pair of main electrodes. Thereby, the semiconductor device of this invention can implement | achieve both improvement of a short circuit tolerance, and suppression of an avalanche phenomenon.

The main features of the present invention are listed.
(First Form) Charged particles include protons, helium, electron beams, double hydrogen, tritium, and the like. Of these, protons are preferably used. Proton can reduce the carrier concentration in the region where the proton has passed and increase the carrier concentration in the region where the proton is accumulated by a predetermined heat treatment.
(2nd form) When using a proton for a charged particle, the temperature of the heat processing after irradiation has the preferable range of 300 to 600 degreeC. By the heat treatment exceeding 300 ° C., the carrier concentration in the region where protons are accumulated can be increased. By the heat treatment at less than 600 ° C., it is possible to maintain a state in which the carrier concentration in the region where protons have passed is reduced. Further, the heat treatment in the range of 300 ° C. to 600 ° C. does not melt the emitter electrode made of aluminum.
(3rd form) In form 2, the time of the heat processing after irradiation has the preferable range of 20 second-300 second. More preferably, the range of 20 seconds to 60 seconds is good. By the heat treatment time exceeding 20 seconds, the carrier concentration in the region where protons are accumulated can be increased. With the heat treatment time of less than 300 seconds, it is possible to maintain a state in which the carrier concentration in the region where protons have passed is reduced. With the heat treatment time of less than 60 seconds, it is possible to maintain a state in which the carrier concentration in the region where protons have passed is significantly reduced.

  Embodiments will be described below with reference to the drawings. The semiconductor devices of the following examples use silicon as the semiconductor material. However, the technical idea of the present invention is also useful for semiconductor devices using other semiconductor materials.

(First embodiment)
FIG. 1 schematically shows a cross-sectional view of the main part of the semiconductor device 10. The semiconductor device 10 is a punch-through vertical IGBT (Insulated Gate Bipolar Transistor).
The semiconductor device 10 includes a collector electrode 22 (an example of a main electrode), a collector region 24 formed on the collector electrode 22, a semiconductor region 37 formed on the collector region 24, and the semiconductor region 37. The body region 42 formed above, the emitter region 46 and the body contact region 44 selectively formed on the surface of the body region 42, and the emitter region 46 and the body contact region 44 are electrically connected The emitter electrode 55 (an example of a main electrode) is provided. Aluminum is used for the collector electrode 22. The collector region 24 contains a p-type impurity (typically boron). The impurity concentration of the collector region 24 is generally adjusted to 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . The body region 42 contains p-type impurities (typically boron). The impurity concentration of the body region 42 is generally adjusted to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . The emitter region 46 is separated from the semiconductor region 37 by the body region 42. The emitter region 46 includes an n-type impurity (typically phosphorus or arsenic). The impurity concentration of the emitter region 46 is generally adjusted to 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . Body contact region 44 includes p-type impurities (typically boron). The impurity concentration of the body contact region 44 is generally adjusted to 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . Aluminum is used for the emitter electrode 55.

  The semiconductor device 10 further includes a trench gate electrode 54. The trench gate electrode 54 penetrates through the body region 42 and reaches the semiconductor region 37. The trench gate electrode 54 is opposed to the body region 42 that separates the semiconductor region 37 and the emitter region 46 via the gate insulating film 52. The trench gate electrode 54 and the trench gate electrode 54 adjacent thereto are separated from each other by a predetermined distance. The group of trench gate electrodes 54 are arranged in a stripe shape when viewed in plan. The trench gate electrode 54 and the emitter electrode 55 are electrically separated by an insulating separation film 53. Polysilicon is used for the trench gate electrode 54.

The semiconductor region 37 includes an electric field holding region 38 and a buffer region 36. The electric field holding region 38 is formed in the upper part of the semiconductor region 37. The buffer region 36 is formed in the lower part of the semiconductor region 37. The buffer region 36 is formed between the collector region 24 and the electric field holding region 38.
The electric field holding region 38 includes a first partial region 34 and a second partial region 32. The thickness of the electric field holding region 38 is generally adjusted to 50 to 200 μm. The first partial region 34 extends from the front surface to the back surface of the electric field holding region 38. The second partial region 32 also extends from the front surface to the back surface of the electric field holding region 38. The first partial region 34 has a thin plate shape, and the second partial region 32 also has a thin plate shape. The first partial region 34 and the second partial region 32 are arranged in a stripe shape in a plane orthogonal to the direction between the pair of main electrodes (the vertical direction on the paper surface). Therefore, the combination of the first partial region 34 and the second partial region 32 is repeatedly formed in one direction (left and right direction on the paper surface) within a plane orthogonal to the direction between the pair of main electrodes (up and down direction on the paper surface). The first partial region 34 is in contact with the bottom surface 52 b and the side surface 52 a of the gate insulating film 52 covering the trench gate electrode 54.

As will be described later in the manufacturing process, the buffer region 36, the first partial region 34, and the second partial region 32 are formed separately by implanting protons into the semiconductor region 37 containing n-type impurities. Therefore, the concentration of the n-type impurity introduced into the buffer region 36, the concentration of the n-type impurity introduced into the first partial region 34, and the concentration of the n-type impurity introduced into the second partial region 32 are reduced. Concentration is almost equal. The implanted protons change part of the semiconductor region 37 to n ⁺ type or change part of the semiconductor region 37 to i type, so that the buffer region 36, the first partial region 34, and the second partial region 32 are created separately.

The buffer region 36 is produced by the accumulated protons forming a donor. The buffer region 36 is a region where the donor level concentration is high due to the donor caused by protons. The concentration of the donor level can be evaluated by the carrier concentration. The carrier concentration of the buffer region 36 is generally adjusted to 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ .
The first partial region 34 is a region through which protons do not pass, and the state of the original semiconductor region 37 is maintained. Therefore, the first partial region 34 has the same impurity concentration and carrier concentration. The carrier concentration of the first partial region 34 is generally adjusted to 5 × 10 ¹³ to 2 × 10 ¹⁴ cm ⁻³ .
The second partial region 32 is a region in which a part of the n-type impurity introduced into a part of the semiconductor region 37 is inactivated due to the passage of protons, and the donor level concentration is reduced. The carrier concentration of the second partial region 32 is generally adjusted to 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻³ .
Here, the impurity concentration contained in the electric field holding region 38 and the thickness of the electric field holding region 38 are adjusted based on the base region of a so-called punch-through type IGBT. Therefore, it can be evaluated that the electric field holding region 38 has the second partial region 32 formed in a part of the base region of a so-called punch-through type IGBT.

  In the second partial region 32, the carrier concentration is adjusted to be thin. Therefore, the intensity of the electric field extending in the thickness direction of the second partial region 32 is made uniform. For this reason, in the semiconductor device 10, even if an external load connected to the semiconductor device 10 is short-circuited and a high voltage / high current is applied to the semiconductor device 10, the heat generation region is the second partial region 32, and thus the electric field holding region 38. Can be dispersed throughout. Thereby, as for the semiconductor device 10, destruction at the time of a short circuit is suppressed, and short circuit tolerance has improved.

The first partial region 34 is adjusted to have a high carrier concentration. For this reason, when the semiconductor device 10 is turned off, the extension of the depletion layer extending from the joint surface between the electric field holding region 38 and the body region 42 is suppressed by the first partial region 34. When the extension of the depletion layer is suppressed, the parasitic bipolar due to the p-type collector region 22 / n-type electric field holding region 38 / p-type body region 42 is suppressed from being turned on. Therefore, the occurrence of the avalanche phenomenon is also suppressed.
According to the semiconductor device 10, it is possible to suppress the occurrence of the avalanche phenomenon while improving the short-circuit tolerance.

Other features of the semiconductor device 10 will be described below.
(1) In the semiconductor device 10, the combination of the first partial region 34 and the second partial region 32 is repeated in one direction (left and right direction on the paper surface) in a plane orthogonal to the direction between the pair of main electrodes (up and down direction on the paper surface). Is formed. For this reason, the first partial region 34 and the second partial region 32 are formed in a dispersed manner in the electric field holding region 38. Therefore, the semiconductor device 10 can effectively obtain the effect of improving the short-circuit tolerance and the effect of suppressing the occurrence of the avalanche phenomenon.
(2) In the semiconductor device 10, the first partial region 34 is in contact with the bottom surface 52 b and the side surface 52 a of the gate insulating film 52 that covers the trench gate electrode 54. According to the semiconductor device 10, the side surface 52 a of the gate insulating film 52 covering the trench gate electrode 54 and the first partial region 34 can be made continuous. Therefore, when the semiconductor device 10 is turned on, electrons that move along the side surface of the trench gate electrode 54 can move between the collector electrode 22 and the emitter electrode 55 via the first partial region 34. The semiconductor device 10 can obtain a low on-voltage.

(Manufacturing method of the semiconductor device 10)
A method for manufacturing the semiconductor device 10 will be described with reference to FIGS.
First, the semiconductor device 10 is built up to the state shown in FIG. Specifically, after ion implantation of boron into the surface of the n-type semiconductor substrate 30, the body region 42 is formed by performing thermal diffusion. Next, phosphorus (or arsenic) and boron are selectively ion-implanted into a part of the surface portion of the body region 42, and then thermal diffusion is performed to form the emitter region 46 and the body contact region 44.
Next, a trench penetrating the body region 42 from the surface of the semiconductor substrate 30 is formed. A side wall of the trench is thermally oxidized to form a gate insulating film 52. Further, the trench gate electrode 54 is formed by filling the trench with polysilicon.
Next, after forming the insulating separation film 53 on the surface of the trench gate electrode 54, the emitter electrode 55 is formed on the surface of the semiconductor substrate 30.
Next, boron is ion-implanted from the back surface of the semiconductor substrate 30, and the collector region 24 is formed by low-temperature heat treatment at 600 ° C. or lower.
Through these steps, the semiconductor device 10 in the state shown in FIG. 2 is obtained.

Next, as shown in FIG. 3, a proton implantation step is performed.
First, a mask 62 in which a plurality of openings 63 are formed facing the surface of the semiconductor substrate 30 is provided. Next, protons are implanted toward the semiconductor substrate 30 through the opening 63 of the mask 62. At this time, the irradiation energy is set so that the projected range of protons (region where protons are most present) is slightly shallower than the collector region 24 (see region 65 in FIG. 3). In the projected range region 65, the protons interact with the nuclei of the silicon atoms and release the irradiation energy to stop the accelerated ions (nucleus stopping ability). Therefore, protons diffuse in the vertical direction and the horizontal direction in the projection range region 65.
On the other hand, in the passing region 64, the phenomenon in which the proton irradiation energy decreases is centered on the electron stopping ability. Therefore, in the passage region 64, the lateral spread of protons is small.

  In the projection range region 65, the spread of protons in the vertical and horizontal directions is approximately proportional to the irradiation energy. In this embodiment, by setting the irradiation energy to 4 MeV, the projection range region 65 is adjusted to about 150 μm from the surface of the semiconductor substrate 30, the vertical extent is 10 μm, and the lateral extent is 8 μm. Further, by setting the width 62a of the mask 62 (the width between the opening 63 and the opening 63 adjacent thereto) to 8 μm or less in the lateral direction, the range of accumulated protons is laterally changed in the projection range region 65. Can be continuous.

  Next, heat treatment is performed at a predetermined temperature and for a predetermined time. As a result, an electric field holding region 38 including a first partial region 34 having a high carrier concentration and a second partial region 32 having a low carrier concentration is formed in the upper portion of the semiconductor region 37. A buffer region 36 having a high carrier concentration is formed below the semiconductor region 37.

FIG. 4 shows the relationship between the amount of protons implanted and the carrier concentration in the depth direction from the surface of the semiconductor substrate 30. FIG. 4 shows the results when heat treatment is performed at 300 ° C. for 30 minutes after protons are implanted into the semiconductor substrate 30. The heat treatment at 300 ° C. for 30 minutes is a condition within a range where the emitter electrode 55 on the surface does not melt. The carrier concentration was measured by spreading resistance measurement.
As shown in FIG. 4, it can be seen that the carrier concentration in the passage region 64 decreases when the proton implantation amount is 1 × 10 ¹³ cm ⁻² or more. This is because when a proton passes, a crystal defect is formed in the passage region 64, and impurities in the passage region 64 are inactivated by the defect level. Therefore, in order to reduce the carrier concentration of a part of the semiconductor substrate 30, it is preferable to set the proton implantation amount to 1 × 10 ¹³ cm ⁻² or more.

FIG. 5 shows the relationship between the heat treatment time and the carrier concentration in the depth direction from the surface of the semiconductor substrate 30. FIG. 5 shows the results when the heat treatment temperature is 450 ° C. and the proton implantation amount is 1 × 10 ¹⁵ cm ⁻² . The heat treatment at 450 ° C. is a condition within a range where the emitter electrode 55 on the surface does not melt.
As shown in FIG. 5, the formation of the donor in the projection range 65 can be achieved even with a short heat treatment time. If a heat treatment time exceeding 1 second is secured, a donor can be formed in the projection range 65. However, when the heat treatment time reaches 300 seconds, defects in the passage region 64 are recovered, and the carrier concentration in the passage region 64 matches the original impurity concentration (initial concentration). Therefore, in order to reduce the carrier concentration in the passing region 64 while forming a donor in the projection range 65, it is desirable to set the heat treatment time to less than 300 seconds.

(Second embodiment)
FIG. 6 is a schematic cross-sectional view of the main part of the semiconductor device 100 according to the second embodiment. The same components as those of the semiconductor device 10 in FIG.
In the semiconductor device 100, the second partial region 132 is formed widely. The second partial region 132 is in contact with the entire surface of the bonding interface 42 a between the electric field holding region 138 and the body region 42. The first partial region 134 is in contact only with the bottom surface 52 b of the gate insulating film 52 covering the trench gate electrode 54.
In the semiconductor device 100, when an external load connected to the semiconductor device 100 is short-circuited, a high current can be passed through the second partial region 132. Since the second partial region 132 is adjusted to have a low carrier concentration, the intensity of the electric field extending in the thickness direction of the second partial region 132 is made uniform. Therefore, even if a high voltage and a high current are applied to the semiconductor device 100, the heat generation region can be dispersed throughout the second partial region 132. The short circuit tolerance of the semiconductor device 100 is remarkably improved.
In order to obtain the above-described effects, the second partial region 132 does not necessarily have to be in contact with the entire surface of the junction interface 42a between the electric field holding region 138 and the body region 42. If the second partial region 132 is in contact with a wide range of the bonding interface 42a between the electric field holding region 138 and the body region 42, the above-described effects can be obtained.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view of a main part of a semiconductor device 200 according to the third embodiment. The same components as those of the semiconductor device 10 in FIG.
The electric field holding region 238 of the semiconductor device 200 further includes a third partial region 231 having a low carrier concentration. The third partial region 231 is formed on the entire back surface portion of the electric field holding region 238.
In the semiconductor device 200, since the third partial region 231 having a low carrier concentration is formed on the entire back surface portion of the electric field holding region 238, the amount of electric field held in the vertical direction can be increased. Therefore, the breakdown voltage of the semiconductor device 200 can be improved.

(Fourth embodiment)
FIG. 8 schematically shows a cross-sectional view of a relevant part of a semiconductor device 300 of the fourth embodiment. The same components as those of the semiconductor device 10 in FIG.
The collector region 324 of the semiconductor device 300 is formed in a distributed manner on the collector electrode 22. The buffer region 336 is in contact with the collector electrode 22 via a region 336a between the collector regions 324 to be dispersed. The collector region 324 can be formed by selectively ion-implanting boron from the back surface of the semiconductor substrate and performing a heat treatment.
According to the semiconductor device 300, the electrons accumulated in the semiconductor region 37 when it is turned off are quickly discharged to the collector electrode 22 through the region 336 a between the collector regions 324. Therefore, the semiconductor device 300 can improve the switching speed. Furthermore, the semiconductor device 300 suppresses the operation of the parasitic bipolar diode formed by the p-type collector region 324, the n-type semiconductor region 37, and the p-type body region 42, thereby suppressing the occurrence of the avalanche phenomenon. Can do.

(5th Example)
FIG. 9 is a schematic cross-sectional view of a main part of a semiconductor device 400 according to the fifth embodiment. The same components as those of the semiconductor device 10 in FIG.
The semiconductor device 400 has a vertical MISFET structure. The semiconductor device 400 includes a drain electrode 422 instead of the collector electrode 22. The semiconductor device 400 includes a source electrode 455 instead of the emitter electrode 55. The semiconductor device 400 includes a drain region 424 containing an n-type impurity at a high concentration instead of the collector region 24. The semiconductor device 400 includes a source region 446 containing a high concentration of n-type impurities in place of the emitter region 46. Note that the drain region 424 and the buffer region 36 may be formed at the same concentration.
The semiconductor device 400 also includes the first partial region 34 and the second partial region 32 in the electric field holding region 38. If the entire electric field holding region 38 is composed only of the second partial region 32, the electric field strength in the vicinity of the junction interface between the electric field holding region 38 and the buffer region 36 is increased when a high voltage / high current is applied. It becomes higher and promotes the occurrence of the avalanche phenomenon.
On the other hand, since the electric field holding region 38 includes the first partial region 34 and the second partial region 32 as in the semiconductor device 400, even if a high voltage and a high current are applied, the electric field holding region 38 and the buffer region are provided. The phenomenon that the electric field strength in the vicinity of the 36 bonding interface becomes too high can be suppressed.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional drawing of the semiconductor device of 1st Example is typically shown. A manufacturing process of the semiconductor device of the first embodiment will be described (1). 2 shows a manufacturing process of the semiconductor device of the first embodiment (2). The relationship between the amount of proton implantation and the carrier concentration is shown. The relationship between heat treatment time and carrier concentration is shown. The principal part sectional drawing of the semiconductor device of 2nd Example is shown typically. The principal part sectional drawing of the semiconductor device of 3rd Example is shown typically. Sectional drawing of the principal part of the semiconductor device of 4th Example is shown typically. The principal part sectional drawing of the semiconductor device of 5th Example is shown typically.

Explanation of symbols

22: Collector electrode 24, 324: Collector region 32, 132: Second partial region 34, 134: First partial region 36, 336: Buffer region 37, 137, 237: Semiconductor region 38, 138, 238: Electric field holding region 42 : Body region 44: body contact region 46: emitter region 52: gate insulating film 53: insulating isolation film 54: trench gate electrode 55: emitter electrode 231: third partial region 422: drain electrode 424: drain region 446: source region 455 : Source electrode

Claims (16)

A semiconductor device comprising an electric field holding region where a depletion layer is formed when turned off between a pair of main electrodes,
The electric field holding region includes a first partial region having a relatively high carrier concentration and a second partial region having a relatively low carrier concentration in a plane perpendicular to the direction between the pair of main electrodes. A semiconductor device.   2. The semiconductor device according to claim 1, wherein the combination of the first partial region and the second partial region is repeatedly formed in at least one direction within a plane orthogonal to the direction between the pair of main electrodes. A semiconductor device comprising an electric field holding region where a depletion layer is formed when turned off between a pair of main electrodes,
A first main electrode;
A collector region formed on the first main electrode and containing a first conductivity type impurity;
A semiconductor region formed on the collector region;
A body region containing a first conductivity type impurity formed on the semiconductor region;
An emitter region that is separated from the semiconductor region by the body region and includes an impurity of a second conductivity type;
A second main electrode electrically connected to the emitter region;
A trench gate electrode penetrating the body region and facing the body region separating the semiconductor region and the emitter region via a gate insulating film,
The semiconductor region has an electric field holding region,
The electric field holding region includes a first partial region in which the second conductivity type carrier concentration is relatively high and a second conductivity type carrier concentration in the surface perpendicular to the direction between the pair of main electrodes. A semiconductor device comprising two partial regions. The semiconductor region further includes a buffer region having a high carrier concentration of the second conductivity type,
4. The semiconductor device according to claim 3, wherein the buffer region is formed between the collector region and the electric field holding region. The collector region is formed dispersed on the first main electrode,
5. The semiconductor device according to claim 3, wherein the semiconductor region is in contact with the first main electrode through the collector regions that are dispersed. A semiconductor device comprising an electric field holding region where a depletion layer is formed when turned off between a pair of main electrodes,
A first main electrode;
A drain region formed on the first main electrode and containing a second conductivity type impurity;
A semiconductor region formed on the drain region;
A body region containing a first conductivity type impurity formed on the semiconductor region;
A source region that is separated from the semiconductor region by the body region and that includes impurities of a second conductivity type;
A second main electrode electrically connected to the source region;
A trench gate electrode penetrating the body region and facing the body region separating the semiconductor region and the source region via a gate insulating film,
The semiconductor region has an electric field holding region,
The electric field holding region includes a first partial region in which the second conductivity type carrier concentration is relatively high and a second conductivity type carrier concentration in the surface perpendicular to the direction between the pair of main electrodes. A semiconductor device comprising two partial regions.   7. The semiconductor according to claim 3, wherein the combination of the first partial region and the second partial region is repeatedly formed in at least one direction within a plane orthogonal to the direction between the pair of main electrodes. apparatus.   8. The semiconductor device according to claim 3, wherein the concentration of the second conductivity type impurity introduced into the first partial region and the second partial region is substantially equal. The first partial region extends from the front surface to the back surface of the electric field holding region,
The semiconductor device according to claim 3, wherein the second partial region also extends from the front surface to the back surface of the electric field holding region.   The semiconductor device according to claim 9, wherein the second partial region is in contact with a junction interface between the electric field holding region and the body region.   11. The semiconductor device according to claim 10, wherein the second partial region is in contact with the entire surface of the junction interface between the electric field holding region and the body region. The electric field holding region further includes a third partial region in which the carrier concentration of the second conductivity type is relatively thin,
12. The semiconductor device according to claim 3, wherein the third partial region is formed on the entire back surface portion of the electric field holding region.   The semiconductor device according to claim 3, wherein the first partial region is in contact with a bottom surface and a side surface of the trench gate electrode. A method for manufacturing a semiconductor device comprising an electric field holding region in which a depletion layer is formed when turned off between a pair of main electrodes,
Providing a mask having a plurality of openings formed facing the surface of a semiconductor substrate containing impurities;
A step of implanting charged particles toward the semiconductor substrate through the opening of the mask;
A part of the impurity introduced into the region through which the charged particles have passed is inactivated, whereby a first partial region having a relatively high carrier concentration and a second portion having a relatively low carrier concentration in the semiconductor substrate. An electric field holding region having a region is formed.   In the implantation step, protons are used for the charged particles, and after the charged particles are implanted, heat treatment is performed to inactivate some of the impurities introduced into the region through which the charged particles have passed, thereby reducing the carrier concentration. 15. The manufacturing method according to claim 14, wherein the carrier concentration is increased by charged particles accumulated in a deep portion of the semiconductor substrate. The manufacturing method according to claim 15, wherein in the implantation step, charged particles are implanted at 1 × 10 ¹³ cm ⁻² or more.

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