JP2009152420A - Lateral mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the conventional lateral MOSFET 20 has a deficiency that Vt fluctuates because of hot carrier generation in a high electric field concentrated on the drain side edge, as a result of its inability reaching the drain side edge of the gate electrode 39, which is caused by the fact that a depletion layer a is not easily extended near an N type impurity region 44 with comparatively high impurity concentration, which is disposed for the purpose of reducing on-resistance. <P>SOLUTION: The lateral MOSFET 1 includes an N<SP>+</SP>type high concentration region 5 having higher impurity concentration than that of an N<SP>-</SP>type semiconductor layer 33 on the front surface layer of the N<SP>-</SP>type semiconductor layer 33 that lies between a P<SP>+</SP>type base region 35 and an N<SP>++</SP>type drain region 36; and a plurality of N<SP>-</SP>type low concentration regions 6 having lower impurity concentration than that of the N<SP>+</SP>type high concentration region 5 on the front surface layer of the N<SP>-</SP>type semiconductor layer 33 that extend towards the N<SP>++</SP>type drain region 36, while each one edge of the N<SP>-</SP>type low concentration regions touches the P<SP>+</SP>type base region 35. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a lateral MOSFET.

  An example of a conventional lateral MOSFET is shown in FIG. FIG. 8 is a longitudinal sectional view of an N-channel lateral MOSFET formed on an SOI substrate.

In FIG. 8, 20 is a conventional lateral MOSFET, 30 is an SOI substrate, 31 is an N-type or P-type silicon substrate, 32 is a silicon oxide film, 33 is an N ⁻ type semiconductor layer, 34 is an N ⁺ type well region, 35 Is a P ⁺ -type base region, 36 is an N ⁺⁺ -type drain region, 37 is an N ⁺⁺ -type source region, 38 is a gate insulating film, 39 is a gate electrode, 40 is a LOCOS oxide film, 41 is an interlayer insulating film, and 42 is a drain electrode. , 43 are source electrodes, and 44 is an N-type impurity region.

The SOI substrate 30 is composed of an N-type or P-type silicon substrate 31, a silicon oxide film 32 thereon, and an N ⁻ type semiconductor layer 33 thereon.

In a predetermined region of the surface layer of the N ⁻ type semiconductor layer 33, an N ⁺ type well region 34 that does not reach the silicon oxide film 32 and a P ⁺ type base region 35 that reaches the silicon oxide film 32 are a predetermined distance. They are formed apart from each other.

Further, an N-type impurity region 44 having an impurity concentration higher than that of the N ⁻ -type semiconductor layer 33 is formed in the surface layer of the N ⁻ -type semiconductor layer 33 between the P ⁺ -type base region 35 and the N ⁺ -type well region 34. , N ⁺ -type well region 34 serves to reduce on-resistance.

The surface layer of the N ⁺ -type well region 34, N ⁺ -type well region 34 end (in the figure, rightward) N ⁺⁺ type drain region 36 spaced a high impurity concentration by the predetermined distance is formed, on the surface layer of the P ⁺ -type base region 35, the P ⁺ -type base region 35 end (in the figure, to the left) a predetermined distance (channel length) spaced apart by a high impurity concentration N ⁺⁺ type source region 37 is formed Has been.

A gate electrode 39 made of polysilicon is formed on the surface of the P ⁺ -type base region 35 between the N ⁺⁺ -type drain region 36 and the N ⁺⁺ -type source region 37 via a gate insulating film 38.

Further, a thick LOCOS oxide film 40 is formed between the N-type impurity region 44 and the N ⁺⁺ type drain region 36, and serves to alleviate electric field concentration at the drain side end portion (E portion in the figure) of the gate electrode 39. I am doing.

A drain electrode 42 that is insulated from the gate electrode 39 by the interlayer insulating film 41 and electrically connected to the N ⁺⁺ type drain region 36, and a source that is electrically connected to the P ⁺ type base region 35 and the N ⁺⁺ type source region 37. The electrodes 43 are each formed of an aluminum film or the like. (For example, see Patent Document 1)

Japanese Patent Laid-Open No. 2004-63918 FIG.

  However, in the conventional lateral MOSFET 20, when a voltage is applied between the drain and the source, the depletion layer a (see FIG. (Indicated by a broken line in the enlarged view) was difficult to stretch.

  For this reason, the depletion layer a does not reach the drain side end portion (e portion) of the gate electrode 39, and the high concentration concentrated on the drain side end portion (e portion) despite the thick LOCOS oxide film 40 being disposed. An avalanche breakdown is caused by an electric field, hot carriers are generated, the hot carriers are trapped in the gate insulating film 38, and Vt (threshold voltage) fluctuates.

The lateral MOSFET of the present invention is
A first conductivity type semiconductor layer;
A drain region of a first conductivity type formed in the surface layer of the semiconductor layer;
A base region of a second conductivity type opposite to the first conductivity type formed in the surface layer of the semiconductor layer apart from the drain region;
A source region of a first conductivity type formed in a surface layer of the base region;
A high concentration region of a first conductivity type formed in a surface layer of the semiconductor layer between the base region and the drain region and having an impurity concentration higher than that of the semiconductor layer;
A lateral MOSFET having a plurality of low-concentration regions that are discretely arranged on the surface layer of the high-concentration region and have an impurity concentration lower than that of the high-concentration region.

  According to the lateral MOSFET of the present invention, it is possible to reduce electric field concentration at the drain side end of the gate electrode and reduce Vt (threshold voltage) fluctuation due to hot carriers while reducing the on-resistance.

  An example of the lateral MOSFET of the present invention is shown in FIGS. FIG. 1A is a plan view of an N-channel type lateral MOSFET formed on an SOI substrate, and FIG. 1B is a perspective view of a main part taken along line CC in FIG. FIG. 2 is a cross-sectional view taken along lines AA and BB in FIG. FIG. 1 shows a state where the interlayer insulating film, the source electrode and the drain electrode are removed (the gate electrode is indicated by a broken line). The same parts as those in FIG.

1 and 2, reference numeral 1 denotes a lateral MOSFET according to the first embodiment of the present invention, 5 denotes an N ⁺ type high concentration region as a first conductivity type high concentration region, and 6 denotes N as a first conductivity type low concentration region. ⁻ Type low concentration region, 30 is an SOI substrate, 31 is an N type or P type silicon substrate, 32 is a silicon oxide film, 33 is an N ⁻ type semiconductor layer as a first conductivity type semiconductor layer, and 35 is a P ⁺ type The base region 36 is an N ⁺⁺ type drain region, 37 is an N ⁺⁺ type source region, 38 is a silicon oxide film, 39 is a gate electrode, 41 is an interlayer insulating film, 42 is a drain electrode, and 43 is a source electrode.

The SOI substrate 30 is composed of an N-type or P-type silicon substrate 31, a silicon oxide film 32 thereon, and an N ⁻ type semiconductor layer 33 thereon.

A P ⁺ type base region 35 reaching the silicon oxide film 32 is formed in a predetermined region of the surface layer of the N ⁻ type semiconductor layer 33.

Further, on the surface layer of the N ⁻ type semiconductor layer 33, a high impurity concentration N ⁺⁺ type drain region 36 is formed in a predetermined region separated from the P ⁺ type base region 35 by a predetermined distance (to the right in the drawing). , the surface layer of the P ⁺ -type base region 35, the P ⁺ -type base region 35 end (in the figure, leftward) N ⁺⁺ type source region 37 spaced a high impurity concentration by a predetermined distance (channel length) Is formed.

A gate electrode 39 made of polysilicon is formed on the surface of the P ⁺ -type base region 35 between the N ⁺⁺ -type drain region 36 and the N ⁺⁺ -type source region 37 via a gate insulating film 38.

Also, one end of the surface layer of the N ⁻ -type semiconductor layer 33 between the P ⁺ -type base region 35 and the N ⁺ -type drain region 36 is the P ⁺ -type base region 35 and the other end is the N ⁺ -type drain region 36. In contact therewith, an N ⁺ type high concentration region 5 having an impurity concentration higher than that of the N ⁻ type semiconductor layer 33 is formed, and serves to reduce the on-resistance.

In addition, the surface layer of the N ⁺ -type high concentration region 5 has a plurality of stripes discretely arranged at predetermined intervals toward the N ⁺ -type drain region 36 with one end in contact with the P ⁺ -type base region 35. The N ⁻ type low concentration region 6 having an impurity concentration lower than that of the N ⁺ type high concentration region 5 is formed.

In the first embodiment, the other end of the N ⁻ -type low concentration region 6 reaches the N ⁺⁺ -type drain region 36 beyond the drain side end portion (e portion in the figure) of the gate electrode 39.

Due to the N ⁻ type low concentration region 6, when a voltage is applied between the drain and the source, the depletion layer b (indicated by a broken line in FIG. 2) is more than the drain side end portion (e portion) of the gate electrode 39. Extending to the N ⁺⁺ type drain region 36 side, the electric field concentration can be relaxed, and hot carriers can be prevented from being generated. As a result, fluctuations in Vt (threshold voltage) can be suppressed.

That is, while the N ⁺ type high concentration region 5 as a low resistance current path and the N ⁻ type low concentration region 6 for extending the depletion layer b are alternately arranged on the surface layer, the on-resistance is reduced. Electric field concentration can be reduced.

Here, if both the width w and the arrangement interval s of the N ⁻ type low concentration region 6 are set to about 1 to 2 μm, the depletion layers b of the adjacent N ⁻ type low concentration regions 6 are easily connected to each other with a space therebetween. Accordingly, the depletion layer b of the N ⁺ type high concentration region 5 sandwiched between the N ⁻ type low concentration regions 6 is also pulled by the N ⁺⁺ type drain region 36 and the drain side end portion of the gate electrode 39 (in the figure, The electric field concentration is relaxed beyond the portion e).

Further, if the depth d of the N ⁻ type low concentration region 6 with respect to the depth of the N ⁺ type high concentration region 5 is set to a range of about 1/3 to 1/2, the current path area of the N ⁺ type high concentration region 5. Therefore, it is preferable that an increase in on-resistance can be suppressed without excessively reducing.

A drain electrode 42 that is insulated from the gate electrode 39 by the interlayer insulating film 41 and electrically connected to the N ⁺⁺ type drain region 36, and a source that is electrically connected to the P ⁺ type base region 35 and the N ⁺⁺ type source region 37. The electrodes 43 are each formed of an aluminum film or the like.

In such a lateral MOSFET 1, the on-resistance is reduced by the N ⁺ type high concentration region 5, while the depletion layer b is formed by the gate electrode 39 by the N ⁻ type low concentration region 6 discretely arranged on the surface layer at a constant interval. Can extend to the N ⁺⁺ type drain region 36 side beyond the drain side end portion (e portion), and can reduce electric field concentration and suppress Vt (threshold voltage) fluctuation due to hot carriers.

  Next, a manufacturing method of the lateral MOSFET 1 will be described with reference to FIGS. 3, FIG. 4 (d), FIG. 5, and FIG. 6 are cross-sectional views of the device at the completion of each manufacturing process, and FIG. 4 (c) is a perspective view.

First, as shown in FIG. 3A, a thin silicon oxide film 11 is formed on the surface of the N ⁻ type semiconductor layer 33 by thermal oxidation, and phosphorus is ion-implanted to form an N ⁺ type high concentration region 5. .

Next, as shown in FIGS. 3B and 4C, boron, which is a P-type impurity, is selectively ion-implanted using a predetermined resist pattern 12 formed by photolithography as a mask (see FIG. 3B and FIG. 4C). An N ⁻ type low concentration region 6 is formed by a so-called reversal method.

Here, both the width w and the arrangement interval s of the N ⁻ type low concentration region 6 are about 1 to 2 μm, and the depth d of the N ⁻ type low concentration region 6 with respect to the depth of the N ⁺ type high concentration region 5 is: The range is about 1/3 to 1/2.

  Next, after removing the resist pattern 12, the silicon oxide film 11 is removed by wet etching.

  Next, as shown in FIG. 4D, a gate insulating film 38 made of a thin silicon oxide film is formed by a thermal oxidation method, a polysilicon film is grown thereon by a CVD method, and a photolithography method is used. Using the formed resist pattern (not shown) as a mask, unnecessary portions are removed by dry etching to form the gate electrode 39.

Next, as shown in FIG. 5E, the resist pattern 13 formed by using the gate electrode 39 and the photolithography method is used as a mask to selectively form the surface layer of the N ⁻ type semiconductor layer 33 by ion implantation. Then, boron is implanted, and after the resist pattern 13 is removed, a P ⁺ type base region 35 reaching the silicon oxide film 32 by thermal diffusion is formed.

Next, as shown in FIG. 5F, the N ⁻ type semiconductor layer 33 and the P ⁺ type base region 35 are formed by ion implantation using the gate electrode 39 and the resist pattern 14 formed by photolithography as a mask. Arsenic is selectively implanted into the surface layer, and after removing the resist pattern 14, thermal diffusion is performed to form an N ⁺⁺ type drain region 36 and an N ⁺⁺ type source region 37, respectively.

Finally, as shown in FIG. 2, the surface of the P ⁺ type base region 35, the N ^{+ +} type drain region 36, the N ^{+ +} type source region 37 and the gate electrode 39 is exposed after being covered with the interlayer insulating film 41 by the CVD method. Thus, a contact window is formed in the interlayer insulating film 41.

Then, after being coated with an aluminum film by a sputtering method, the aluminum film is selectively removed by a photolithography method and a dry etching method, and a drain electrode 42 electrically connected to the N ⁺⁺ type drain region 36, and a P ⁺ type A source electrode 43 electrically connected to the base region 35 and the N ⁺⁺ type source region 37 is formed.

In the above description, the configuration example in which the termination of the N ⁻ -type low concentration region 6 reaches the N ⁺⁺ -type drain region 36 has been described. However, the configuration in the case where the on-resistance is reduced as much as possible is shown in FIG. Will be described with reference to FIG.

  6A is a plan view of the lateral MOSFET 2 according to the second embodiment, and FIG. 6B is a perspective view of a main part taken along line FF in FIG. 6A. 7A is a cross-sectional view taken along the line DD of FIG. 6A, and FIG. 7B is a cross-sectional view taken along the line EE of FIG. 6A. FIG. 6 shows a state where the interlayer insulating film, the source electrode and the drain electrode are removed (the gate electrode is indicated by a broken line). The same parts as those shown in FIGS.

As shown in FIGS. 6 and 7, the N ⁻ -type low concentration region 6 terminates at a position slightly beyond the drain side end portion (e portion) of the gate electrode 37.

As a result, the length of the N ⁻ -type low concentration region 6 becomes shorter than that of the first embodiment, and the resistance can be reduced.

  Even in the configuration of the second embodiment, as long as the depletion layer b extends beyond the drain-side end portion (e portion) of the gate electrode 39, an electric field concentration relaxation effect substantially the same as that of the first embodiment is obtained. It is done.

That is, the balance between the electric field relaxation effect and the on-resistance reduction effect can be selected by appropriately changing the length L and the depth d of the N ⁻ type low concentration region 6.

More specifically, when a high voltage is applied between the drain and source, in order to prioritize the electric field concentration relaxation effect, for example, the N ⁻ type low concentration region 6 width w is increased or the depth d is increased. To do.

On the other hand, when a low voltage is applied between the drain and source, for example, in order to prioritize the on-resistance reduction effect, for example, the N ^- type low concentration region 6 width w is reduced or the depth is reduced. Reduce d.

  Although the examples of the lateral MOSFETs 1 and 2 using the SOI substrate 30 have been described in both the first and second embodiments, the invention is not particularly limited to this, and the present invention can be similarly applied to a lateral MOSFET that does not use the SOI substrate 30. It is.

  Further, although both the first and second embodiments have been described using the example of the N-type channel MOSFET, the present invention can be similarly applied to a P-type channel lateral MOSFET. In this case, the conductivity type of all the diffusion layers may be replaced with the opposite conductivity type.

  That is, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

The top view of the horizontal type | mold MOSFET of Example 1 of this invention, and the principal part cross-section perspective view in CC line Sectional drawing in the AA line and BB line of FIG. Cross-sectional view of the main part of the device at the completion of each manufacturing process of the lateral MOSFET of the present invention Cross-sectional view and perspective view of main part of device for each manufacturing process completion of lateral MOSFET of the present invention Cross-sectional view of the main part of the device at the completion of each manufacturing process of the lateral MOSFET of the present invention The top view of the horizontal type | mold MOSFET of Example 2 of this invention, and the principal part cross-section perspective view in the FF line Sectional drawing in the DD line and EE line of FIG. Sectional view and main part enlarged view of a conventional lateral MOSFET

Explanation of symbols

1 Lateral MOSFET of Embodiment 1 of the present invention
2 Lateral MOSFET of Example 2 of the present invention
5 N ⁺ type high concentration region as first conductivity type high concentration region 6 N ⁻ type low concentration region as first conductivity type low concentration region 11 Silicon oxide film 12, 13, 14 resist pattern 20 Conventional lateral MOSFET
30 SOI substrate 31 N-type or P-type silicon substrate 32 Silicon oxide film 33 N ⁻ type semiconductor layer 34 N ⁺ type well region 35 P ⁺ type base region 36 N ^{+ +} type drain region 37 N ^{+ +} type source region 38 Gate insulating film 39 Gate electrode 40 LOCOS oxide film 41 Interlayer insulating film 42 Drain electrode 43 Source electrode 44 N-type impurity region a, b Depletion layer d Depth of N ^- type low concentration region 6 e Drain side end of gate electrode 39 L N ⁻ type low concentration region 6 length s N ^- -type lower array spacing density region 6 w N ^- width Vt threshold voltage type low-concentration region 6

Claims (7)

A first conductivity type semiconductor layer;
A drain region of a first conductivity type formed in a surface layer of the semiconductor layer;
A base region of a second conductivity type opposite to the first conductivity type formed in a surface layer of the semiconductor layer apart from the drain region;
A source region of the first conductivity type formed in a surface layer of the base region;
A high concentration region of the first conductivity type formed in a surface layer of the semiconductor layer between the base region and the drain region and having an impurity concentration higher than that of the semiconductor layer;
A lateral MOSFET having a plurality of low-concentration regions that are discretely arranged on the surface layer of the high-concentration region and have an impurity concentration lower than that of the high-concentration region.   2. The lateral MOSFET according to claim 1, wherein the low concentration region is a region extending toward the drain region while contacting one end with the base region.   3. The lateral MOSFET according to claim 1, wherein the low concentration region is a striped region arranged at regular intervals on a surface layer of the high concentration region.   A gate electrode formed on a surface of the semiconductor layer between the source region and the drain region via a gate insulating film, and the other end of the low concentration region extends beyond a drain side end of the gate electrode. The lateral MOSFET according to claim 1, which extends toward the drain region.   The lateral MOSFET according to claim 4, wherein the other end of the low concentration region reaches the drain region.   6. The lateral MOSFET according to claim 1, wherein both the width and the arrangement interval of the low concentration region are in the range of 1 to 2 [mu] m.   The lateral MOSFET according to any one of claims 1 to 6, wherein the depth of the low concentration region is in a range of 1/3 to 1/2 of the depth of the high concentration region.

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