JP2014056881A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can keep manufacturing cost low and reduce turn-off power loss without generating metal pollution arising from heavy-metal atoms.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1 having first and second surfaces 11, 12 which are opposite to each other; a first conductivity type emitter region 3 formed on the first surface 11 of the semiconductor substrate 1; a second conductivity type base region 2 which is formed on the first surface 11 and forms pn junction with the emitter region 3; a first conductivity type drift region 1a which forms pn junction with the base region 2; a second conductivity type collector region 4 which is formed on the second surface 12 and forms pn junction with the drift region 1a; and an atom injection layer 5 is formed on the collector region 4 in the drift region 1a. The atom injection layer 5 includes one and more atoms selected from a group consisting of carbon, nitrogen, fluorine, sulfur, germanium and oxygen.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In recent years, in the field of power electronics typified by inverters, insulated gate bipolar transistors (IGBTs) are required not only for home appliances and industrial applications, but also for electric railways, vehicles, and transformers that require large capacity and high withstand voltage. It is used for such applications. As described above, the IGBT has become a mainstream element among the high breakdown voltage semiconductor elements. The IGBT has a structure in which a PN diode is added to the drain side of a vertical MOS (Metal-Oxide-Semiconductor) transistor. The IGBT is easy to control because of the gate voltage driving system, and realizes a low on-voltage for bipolar operation.

  When the IGBT is turned on, a voltage equal to or higher than the threshold voltage (about 0 to 20 V) is applied to the gate electrode, which is a control terminal, with a forward bias applied between the collector and the emitter. At this time, a channel is formed under the gate electrode, and electrons are injected from the emitter toward the drift region. At the same time, holes flow from the collector into the drift region in a manner that neutralizes the inflow electrons. As a result, conductivity modulation occurs and the resistance of the drift region is greatly reduced, so that a low on-voltage between the collector and the emitter is realized.

  When the IGBT is turned off, a voltage of 0 or a negative value is applied to the gate electrode with a forward bias applied between the collector and the emitter. As a result, the current is cut off, and the applied voltage between the collector and the emitter is held by the depletion layer generated between the base region (P layer) connected to the emitter layer and the drift region (N layer).

  In recent IGBTs for high withstand voltage applications, the carrier transport efficiency is increased by improving the mobility of carriers in the drift region in the ON state, thereby reducing the ON voltage. In addition, the breakdown voltage can be improved by increasing the width of the depletion layer generated between the base region (P layer) connected to the emitter side in the off state and the drift region (N layer) to reduce the electric field strength. Yes. For this reason, a silicon substrate using an FZ crystal manufactured by an FZ (Floating Zone) method having a low specific impurity concentration and a high specific resistance is generally used.

  However, in the FZ crystal having a low impurity concentration, the time until carriers accumulated in the drift region disappear due to recombination, that is, the lifetime increases. Therefore, when the IGBT is turned off from the on state to the off state, a tail current due to the residual carriers is generated, which causes a problem that power loss (turn-off loss) at the time of turn-off increases.

  In order to reduce this turn-off loss, various methods have been conventionally proposed. For example, Japanese Patent Laid-Open No. 6-21358 (Patent Document 1) proposes a method for shortening the lifetime of carriers by implanting light element ions such as hydrogen and helium into a wafer and selectively introducing crystal defects. Has been. Further, for example, Japanese Patent Laid-Open No. 1-253280 (Patent Document 2) proposes a method for performing lifetime control by diffusing heavy metal atoms such as gold into the drift region.

Japanese Patent Laid-Open No. 6-21358 JP-A-1-253280

  However, the technique described in the above-mentioned Japanese Patent Application Laid-Open No. 6-21358 requires a high acceleration voltage of several MeV or more when light element ions are implanted. This necessitates the use of special high energy accelerators such as cyclotrons and tandem pandegraphs. Therefore, there exists a problem that manufacturing cost becomes high.

  Further, in the technique described in the above Japanese Patent Application Laid-Open No. 1-253280, when heavy metal atoms are used as a lifetime killer, metal contamination may occur through a manufacturing apparatus inside a semiconductor factory. As a result, heavy metal atoms adhere to the surface of another element through the manufacturing apparatus, and the heavy metal atom may adversely affect element characteristics such as gate characteristics and junction characteristics.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing the turn-off loss without reducing the manufacturing cost and causing metal contamination by heavy metal atoms, and a method for manufacturing the same. It is to be.

  A semiconductor device of the present invention includes a semiconductor substrate, a first conductivity type emitter region, a second conductivity type base region, a first conductivity type drift region, a second conductivity type collector region, and an atom implantation layer. And. The semiconductor substrate has first and second surfaces facing each other. The emitter region of the first conductivity type is formed on the first surface of the semiconductor substrate. The base region of the second conductivity type is formed on the first surface and forms a pn junction with the emitter region. The drift region of the first conductivity type forms a pn junction with the base region. The collector region of the second conductivity type is formed on the second surface and forms a pn junction with the drift region. The atom injection layer is formed on the collector region in the drift region. The atom injection layer includes one or more atoms selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen.

  According to the semiconductor device of the present invention, the atomic injection layer containing one or more atoms selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen is formed on the collector region in the drift region. Since the atomic injection layer functions as a carrier recombination center, the carrier recombination is promoted, so that the lifetime is reduced. For this reason, turn-off loss can be reduced. Carbon, nitrogen, fluorine, sulfur, germanium and oxygen are implanted by a normal semiconductor device ion implantation apparatus. For this reason, manufacturing cost can be suppressed. Further, since carbon, nitrogen, fluorine, sulfur, germanium and oxygen are not heavy metal atoms, metal contamination by heavy metal atoms does not occur. Therefore, it is possible to reduce the turn-off loss without reducing the manufacturing cost and causing metal contamination by heavy metal atoms.

It is a schematic sectional drawing which shows the structure of the semiconductor device in one embodiment of this invention. It is a figure which shows the impurity concentration profile which follows the A-A 'line | wire of FIG. It is a schematic sectional drawing which shows 1 process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is a schematic sectional drawing which shows the next process of the process shown in FIG. It is a schematic sectional drawing which shows the next process of the process shown in FIG. It is a schematic sectional drawing which shows the next process of the process shown in FIG. It is a schematic sectional drawing which shows the next process of the process shown in FIG. It is a schematic sectional drawing which shows the next process of the process shown in FIG. It is a schematic sectional drawing which shows the next process of the process shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a configuration of a semiconductor device according to an embodiment of the present invention will be described. In one embodiment of the present invention, an IGBT is described as a semiconductor device.

  Referring to FIG. 1, a semiconductor substrate 1 is, for example, a silicon substrate containing a first conductivity type (n-type) impurity. The first conductivity type (n-type) impurity is, for example, a phosphorus atom. The semiconductor substrate 1 is produced, for example, by a floating zone (FZ) method. The semiconductor substrate 1 has a first surface 11 and a second surface 12 that face each other. A drift region 1 a is formed in the semiconductor substrate 1.

  A second conductivity type (p-type) base region 2 and a first conductivity type (n-type) emitter region 3 are formed on the first surface 11 of the semiconductor substrate 1. The base region 2 is formed by introducing a second conductivity type (p-type) impurity from the first surface 11 toward the inside of the semiconductor substrate 1. The base region 2 introduces a second conductivity type (p-type) impurity having a concentration higher than the first conductivity type (n-type) impurity concentration contained in the semiconductor substrate 1 into the semiconductor substrate 1 from the first surface 11. It is formed by doing. The second conductivity type (p-type) impurity is, for example, a boron atom.

  Base region 2 forms a pn junction with drift region 1a, and emitter region 3 also forms a pn junction. A channel region 2 a is formed in a portion of the base region 2 that is sandwiched between the drift region 1 a and the emitter region 3 and exposed on the first surface 11 of the semiconductor substrate 1.

  The emitter region 3 is formed by introducing a first conductivity type (n-type) impurity from the first surface 11 toward the inside of the semiconductor substrate 1. The emitter region 3 is provided in the base region 2, and has a first conductivity type (n-type) impurity having a higher concentration than the second conductivity type (p-type) impurity concentration contained in the base region 2 on the first surface. 11 is introduced into the base region 2. This first conductivity type (n-type) impurity is, for example, an arsenic atom.

  A collector region 4 is formed on the second surface 12 of the semiconductor substrate 1. The collector region 4 is formed by introducing a second conductivity type (p-type) impurity from the second surface 12 toward the inside of the semiconductor substrate 1. The second conductivity type (p-type) impurity is, for example, a boron atom. The collector region 4 forms a pn junction with the drift region 1a.

  An atom injection layer 5 is formed on the collector region 4 in the drift region 1a. The atom implantation layer 5 includes one or more atoms selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen. The atom implantation layer 5 is formed between the base region 2 and the collector region 4. The atom implantation layer 5 is formed in the drift region 1 a in contact with the collector region 4. The atom implantation layer 5 is formed so as to cover the entire region of the collector region 4 on the first surface 11 side. That is, the atomic injection layer 5 covers the entire region on the first surface 11 side of the collector region 4 not only in a sectional view but also in a plan view.

  A gate electrode 7 is provided on the first surface 11 of the semiconductor substrate 1 via a gate insulating film 6 so as to cover at least the channel region 2a. The gate insulating film 6 is made of, for example, silicon dioxide. The gate electrode 7 is made of, for example, polycrystalline silicon. An emitter electrode 8 is provided on the first surface 11 of the semiconductor substrate 1 so as to ensure electrical connection with the base region 2 and the emitter region 3. The emitter electrode 8 is made of a metal film such as aluminum.

  An interlayer insulating film 9 is provided between the gate electrode 7 and the emitter electrode 8. A collector electrode 10 is provided on the second surface 12 of the semiconductor substrate 1 so as to ensure electrical connection with the collector region 4. The collector electrode 10 is made of a multilayer metal film containing, for example, aluminum.

  Subsequently, an impurity concentration profile of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2, the impurity concentration of the atom implantation layer is higher than the impurity concentration of the drift region on the first surface side.

  The structure of the unit cell of the IGBT element has been described above. Usually, the IGBT element is composed of a plurality of such unit cells juxtaposed, a termination processing region surrounding the unit cell, and a plurality of pad regions for taking out current to the outside.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.
Referring to FIG. 3, a semiconductor substrate 1 having a first surface 11 and a second surface 12 facing each other and having a first conductivity type (n-type) drift region 1a is prepared. For example, phosphorus atoms are introduced as the impurities of the first conductivity type (n-type). The semiconductor substrate 1 is formed by the FZ method. The semiconductor substrate 1 includes a silicon crystal formed by the FZ method.

  Subsequently, referring to FIG. 4, gate insulating film 6 made of, for example, silicon dioxide is selectively formed on first surface 11 of semiconductor substrate 1. A gate electrode 7 made of, for example, polycrystalline silicon is formed on the gate insulating film 6.

  Next, referring to FIG. 5, the second conductivity type base region 2 and the first conductivity type emitter region 3 are formed on the first surface 11, respectively. Base region 2 is formed to form a pn junction with emitter region 3.

  Specifically, the base region 2 is selectively formed on the first surface 11 by introducing a second conductivity type (p-type) impurity from the first surface 11 toward the inside of the semiconductor substrate 1. . The base region 2 is formed by thermally diffusing a second conductivity type (p-type) impurity having a concentration higher than the first conductivity type (n-type) impurity concentration contained in the semiconductor substrate 1 from the first surface 11. It is formed by introducing into. For example, boron atoms are introduced as the second conductivity type (p-type) impurities.

  Further, by introducing a first conductivity type (n-type) impurity from the first surface 11 toward the inside of the semiconductor substrate 1, the emitter region 3 is selectively formed on the first surface 11. The emitter region 3 is provided in the base region 2, and has a first conductivity type (n-type) impurity having a higher concentration than the second conductivity type (p-type) impurity concentration contained in the base region 2 on the first surface. 11 is introduced into the base region 2 by thermal diffusion. For example, arsenic atoms are introduced as the first conductivity type (n-type) impurities.

  Subsequently, referring to FIG. 6, interlayer insulating film 9 is formed so as to cover gate insulating film 6 and gate electrode 7. An emitter electrode 8 is formed so as to cover interlayer insulating film 9 and to be electrically connected to base region 2 and emitter region 3. The emitter electrode 8 is formed of a metal film such as aluminum.

  Next, referring to FIG. 7, carbon (C), nitrogen (N), fluorine (F), sulfur (S) from the second surface 12 side to the drift region 1 a constituting the pn junction with the base region 2. One or more atoms selected from the group consisting of germanium (Ge) and oxygen (O) are implanted. Thereby, the atom implantation layer 5 is formed.

Here, a case where carbon atoms are implanted into the semiconductor substrate 1 will be described. Carbon atoms are implanted, for example, at about 6 KeV, 2 × 10 ¹⁵ (at / cm ² ), and are formed within a depth of 1 μm. Carbon atoms are implanted so that the second surface 12 of the semiconductor substrate 1 becomes amorphous. The atomic injection layer 5 is also formed by injecting nitrogen, fluorine, sulfur, germanium and oxygen.

  Referring to FIG. 8, impurities of the second conductivity type are continuously implanted from second surface 12 of semiconductor substrate 1, and then the implanted atoms are activated by heat treatment to form collector region 4. As a result, the second conductivity type collector region 4 that forms the pn junction with the drift region 1 a is formed on the second surface 12. At this time, the collector region 4 is formed by implanting impurity ions into the second surface 12 which has become amorphous.

  Next, referring to FIG. 9, collector electrode 10 is formed on second surface 12 on which collector region 4 is formed. Collector electrode 10 is formed of a multilayer metal film containing, for example, aluminum.

Next, the operation of the semiconductor device according to the embodiment of the present invention will be described.
Referring again to FIG. 1, when the IGBT is turned on, a predetermined positive voltage (for example, 600 V) is applied between collector electrode 10 and emitter electrode 8, and gate electrode 7, emitter electrode 8, A voltage equal to or higher than the threshold voltage (for example, 15 V) is applied during the period. As a result, the conductivity type of the channel region 2a immediately below the gate electrode 7 is inverted to form a first conductivity type channel. Electrons are supplied as majority carriers from the emitter region 3 to the drift region 1a via the first conductivity type channel. At the same time, holes are injected from the collector region 4 into the drift region 1a as minority carriers.

  When minority carriers are injected into the drift region 1a, conductivity modulation occurs in the drift region 1a, and its conduction resistance is greatly reduced. For this reason, a large current flows between the collector electrode 10 and the emitter electrode 8. In this way, the IGBT is turned on and transitions to the on state.

  Next, when the IGBT is turned off, a voltage equal to or lower than the threshold voltage (for example, −15 V) is applied between the gate electrode 7 and the emitter electrode 8 in the conductive IGBT. As a result, the first conductivity type channel formed in the channel region 2a immediately below the gate electrode 7 disappears. Therefore, the supply of majority carriers (electrons) from the emitter region 3 to the drift region 1a is stopped. At the same time, the injection of minority carriers (holes) from the collector region 4 to the drift region 1a stops. For this reason, minority carriers remain in the drift region 1a.

  At the same time as the supply of carriers is stopped, the second conductivity type base region 2 connected to the emitter electrode 8 to which a negative voltage is applied to the collector electrode 10, the first conductivity type drift region 1 a, In this junction, a reverse bias is applied, and the depletion layer begins to spread. The depletion layer spreads according to the voltage applied between the base region 2 and the drift region 1a, so that the voltage between the collector electrode 10 and the emitter electrode 8 is secured and the breakdown voltage is maintained.

  At this time, the minority carriers remaining in the drift region 1a move in the drift region 1a while being pushed by the spreading depletion layer. A part of the minority carriers recombine with the majority carriers in the drift region 1a and disappear, but the remaining part recombines and disappears in the atom injection layer 5 formed on the collector region 4 in the drift region 1a. When all the remaining minority carriers disappear, a current flowing from the collector electrode 10 to the emitter electrode 8, that is, a so-called tail current stops. Thus, the IGBT is turned off and transitions to the off state.

  It is necessary to shorten the time until the transition to the off state, that is, the turn-off time, in order to reduce the turn-off loss. The reduction in turn-off loss depends on how short the minority carrier lifetime is and how quickly it disappears.

  In the above-described atom implantation layer 5, carbon atoms implanted into the silicon crystal of the semiconductor substrate 1 easily form substitutional and interstitial lattice defects with the silicon atoms. Since this lattice defect has a defect level that is higher by about 0.1 eV to 0.2 eV than the valence band of silicon atoms, it functions as a recombination center of holes that are minority carriers and contributes to a reduction in lifetime.

Next, the function and effect of the embodiment of the present invention will be described.
According to the semiconductor device of one embodiment of the present invention, the atom implantation layer 5 including one or more atoms selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen is provided in the collector region in the drift region 1a. 4 is formed. Since the atomic injection layer 5 works as a carrier recombination center, the carrier recombination is promoted, so that the lifetime is reduced. For this reason, turn-off loss can be reduced. Carbon, nitrogen, fluorine, sulfur, germanium and oxygen are implanted by a normal semiconductor device ion implantation apparatus. For this reason, manufacturing cost can be suppressed. Further, since carbon, nitrogen, fluorine, sulfur, germanium and oxygen are not heavy metal atoms, metal contamination by heavy metal atoms does not occur. Therefore, it is possible to reduce the turn-off loss without reducing the manufacturing cost and causing metal contamination by heavy metal atoms.

  In the semiconductor device according to the embodiment of the present invention, it is preferable that the atom injection layer 5 is formed in the drift region 1 a in contact with the collector region 4. This makes it possible to control the minority carrier lifetime in the drift region 1a locally in the vicinity of the collector region 4 along the minority carrier flow path during turn-off. For this reason, the turn-off loss can be reduced while suppressing the rise of the on-voltage as much as possible.

  That is, if the lifetime of the minority carriers is simply reduced in the entire drift region 1a, the conduction characteristics are deteriorated, so that a trade-off relationship occurs in which the turn-off loss is reduced but the on-voltage is increased. Therefore, in order to achieve both the on-voltage and the turn-off loss in an appropriate balance and obtain desired device characteristics, it is necessary to appropriately control the lifetime of minority carriers in the drift region 1a instead of the entire drift region 1a. Desired.

  In the semiconductor device according to the embodiment of the present invention, it is preferable that the atomic injection layer 5 is formed so as to cover the entire region on the first surface 11 side of the collector region 4. For this reason, recombination of minority carriers is promoted by the atom injection layer 5 in the entire region of the collector region 4 on the first surface 11 side. Therefore, the minority carrier lifetime can be efficiently reduced.

  According to the method of manufacturing a semiconductor device of one embodiment of the present invention, one or more kinds selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen from the second surface 12 side to the drift region 1a. Atoms are injected. This atom acts as a carrier recombination center, which promotes carrier recombination, thereby reducing the lifetime. For this reason, turn-off loss can be reduced. Carbon, nitrogen, fluorine, sulfur, germanium and oxygen are implanted by a normal semiconductor device ion implantation apparatus. For this reason, manufacturing cost can be suppressed. Further, since carbon, nitrogen, fluorine, sulfur, germanium and oxygen are not heavy metal atoms, metal contamination by heavy metal atoms does not occur. Therefore, it is possible to reduce the turn-off loss without reducing the manufacturing cost and causing metal contamination by heavy metal atoms.

  In addition, according to the method of manufacturing a semiconductor device of one embodiment of the present invention, atoms are implanted so that the second surface 12 becomes amorphous, and impurities are introduced into the amorphous second surface 12. Ions are implanted. For this reason, the distribution of the impurity ions, that is, the collector region 4 can be shallowly formed. As a result, the on-voltage and the turn-off loss can be reduced while suppressing a decrease in the breakdown voltage. The reason will be described below.

  By injecting carbon atoms in advance into the second surface 12 serving as an impurity ion implantation surface, the lattice structure of the silicon crystal is destroyed and made amorphous. For this reason, when impurity ions such as boron are subsequently implanted, it is possible to prevent a channeling phenomenon in which the implanted ions reach the deep position of the semiconductor substrate 1 through the gap in the atomic arrangement. For this reason, the collector region 4 conventionally formed with a depth of several μm can be formed as shallow as 1 μm or less.

  In the IGBT, reducing the thickness of the semiconductor substrate 1 reduces the resistance component between the emitter and the collector and further reduces minority carriers accumulated in the drift region 1a. For this reason, it is possible to reduce the on-voltage and the turn-off loss by reducing the thickness of the semiconductor substrate 1.

  However, the breakdown voltage of the IGBT is proportional to the square of the width of the depletion layer extending from between the base region 2 and the drift region 1a, as shown in the following formula (1). That is, there is a correlation that the breakdown voltage is proportional to the square of the width of the drift region 1a where the depletion layer extends. Therefore, reducing the thickness of the semiconductor substrate 1 without reducing the depth of the collector region 4 means that the thickness of the drift region 1a is simply reduced. In other words, this means that the width of the depletion layer is reduced, which causes a significant drop in breakdown voltage.

BV = (q × Nd × W ² ) / 2ε (1)
Here, each code | symbol of Formula (1) is demonstrated. BV is a breakdown voltage (V), W is a depletion layer width (cm), q is an electron charge amount (C), Nd is a carrier concentration (atoms / cm ³ ) of the silicon substrate, and ε is It is a dielectric constant (F / cm) of silicon.

  Therefore, by forming the impurity ion implantation region shallowly, the thickness of the semiconductor substrate 1 can be reduced while maintaining the thickness of the drift region 1a, and the on-voltage and turn-off loss can be reduced while suppressing the decrease in breakdown voltage. Can be reduced.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate 1 includes a silicon crystal formed by a floating zone method. Since the lifetime of minority carriers increases in a silicon crystal formed by the FZ method having a low impurity concentration, turn-off loss can be effectively reduced by applying the method for manufacturing a semiconductor device according to an embodiment of the present invention. Can do.

  Although specific embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these, and various modifications can be made. Even with such a configuration, similar effects can be obtained. For example, in the above description, regarding the conductivity type in the semiconductor substrate, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. There may be.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 Semiconductor substrate, 1a drift region, 2 base region, 2a channel region, 3 emitter region, 4 collector region, 5 atom injection layer, 6 gate insulating film, 7 gate electrode, 8 emitter electrode, 9 interlayer insulating film, 10 collector electrode 11 First surface, 12 Second surface.

Claims (6)

A semiconductor substrate having first and second surfaces facing each other;
A first conductivity type emitter region formed on the first surface of the semiconductor substrate;
A base region of a second conductivity type formed on the first surface and constituting a pn junction with the emitter region;
A drift region of a first conductivity type constituting a pn junction with the base region;
A collector region of a second conductivity type formed on the second surface and constituting a pn junction with the drift region;
An atomic injection layer formed on the collector region in the drift region,
The semiconductor device according to claim 1, wherein the atomic injection layer includes one or more atoms selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen.   The semiconductor device according to claim 1, wherein the atomic injection layer is formed in the drift region in contact with the collector region.   The semiconductor device according to claim 1, wherein the atomic injection layer is formed so as to cover the entire region on the first surface side of the collector region. Preparing a semiconductor substrate having first and second surfaces facing each other and having a drift region of a first conductivity type;
Forming a first conductivity type emitter region on the first surface and a second conductivity type base region forming a pn junction with the emitter region;
Implanting one or more atoms selected from the group consisting of carbon, nitrogen, fluorine, sulfur, germanium, and oxygen from the second surface side into the drift region constituting the pn junction with the base region;
Forming a second conductivity type collector region forming a pn junction with the drift region on the second surface. The step of implanting the atoms includes the step of implanting the atoms such that the second surface is amorphous;
The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the collector region includes a step of implanting impurity ions into the second surface that has become amorphous. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate includes a silicon crystal formed by a floating zone method.

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