JP2725131B2 - Electrostatic induction type semiconductor device having an electrostatic induction main electrode short circuit structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of power semiconductor devices, and more particularly, to the reduction of storage time and fall time and the amount of charge extracted from a gate electrode in turn-off switching performance of an electrostatic induction device. An electrostatic induction semiconductor device having a distributed main electrode structure in which the turn-off performance is greatly reduced as compared with the electrostatic induction semiconductor device having a distributed main electrode structure. The present invention relates to an inductive semiconductor device.

[0002]

2. Description of the Related Art Conventionally, various structural devices for improving the switching performance of an electrostatic induction semiconductor device have been proposed. As a first conventional example, in order to reduce an input capacitance between a gate and a source or between a gate and a cathode for an electrostatic induction transistor or an electrostatic induction thyristor having a buried structure, electrons from a source region or a cathode region are reduced. A structure for improving the injection efficiency has already been disclosed by Tamaki Nishizawa and JP-A-1-91474. FIG. 22 is a schematic sectional structural view of the first conventional example. In FIG. 22, 1 is an n ⁻ high resistance layer, 3 is an anode region, 4 is a gate region, 5 is a channel region, and 11 is a cathode region.

In the first prior art, a semiconductor region serving as a cathode or a source is provided only above a channel formed between buried gates, and the capacitance between the gate and the cathode or between the gate and the source is reduced. The switching speed is improved without reducing the current.

Since the high impurity concentration semiconductor region serving as the n ⁺ cathode region 11 or the source region is provided only above the channel region 5 formed between the buried gates,
The junction capacitance between the p ⁺ gate region 4 and the n ⁺ cathode region 11 or the source region is smaller than in the prior art. Therefore, the time constant consisting of the product of the gate resistance and the junction capacitance becomes smaller than before, and the speed at which the gate-cathode voltage or the gate-source voltage propagates to the gate remote from the gate electrode becomes faster than before. This results in turn-on time,
The turn-off time is reduced, and high-speed switching becomes possible.

FIG. 23 shows a second conventional example. FIG.
1 is a sectional structural view of an electrostatic induction thyristor invented by Kawamura and Morikawa and disclosed in Japanese Patent Application Laid-Open No. 4-257266. In FIG. 23, 1 is an n ⁻ high resistance layer, and 3 is p ⁺
An anode region, 4 is a p ⁺ gate region, 6 is an n ⁺ short-circuit layer,
7a is a cathode electrode, 7b is a gate electrode, 7c is an anode electrode, 11 is an n ⁺ cathode region, and 13 is a p ⁺ short-circuit layer. An object of the invention shown in FIG. 23 is to provide an SI thyristor having an excellent turn-off characteristic and an excellent current capacity and withstand voltage by improving a cathode area utilization rate of an SI thyristor using a cathode short-circuit structure. .

[0006] n ^- in ^- (base layer n) static induction thyristor with a one main surface to the n ⁺ cathode region 11 1 and the p ⁺ short layer 13, the n ^- high resistance layer on the base layer 1 p ⁺ Gate region 4 is divided into a plurality of portions, arranged in a direction parallel to the main surface and embedded, and the n ⁺ cathode region 11 is formed at a position facing a channel region between the p ⁺ gate regions 4 , and The p ⁺ short-circuit layer 13 has a configuration as an electrostatic induction thyristor, which is formed at a position facing at least a part of the divided p ⁺ gate region 4 .

That is, the p ⁺ gate region 4 of the SI thyristor
Was formed as a buried structure, ap ⁺ short-circuit layer 13 was formed on the upper surface of the p ⁺ gate region 4 on the cathode surface of the SI thyristor, and the other region was an n ⁺ cathode region 11. Therefore, the region serving as the main current path on the cathode surface is n ⁺
It becomes the cathode region 11 and is configured to increase the effective area utilization rate.

FIG. 24 shows a third conventional example. FIG.
1 is a sectional structural view of an example of an electrostatic induction thyristor invented by Muraoka and disclosed in Japanese Patent Application Laid-Open No. 60-152563. In FIG. 24, 1 is an n ⁻ high resistance layer, 3 is a second high concentration layer (p ⁺ anode region), and 4 is p ⁺
A gate region, 7a is a cathode electrode, 7b is a gate electrode,
7c is an anode electrode, 11 is a first high concentration layer (n ⁺ cathode region), 12 is a support electrode, and 14 and 14 'are insulating layers. The invention described above relates to the p ⁺ gate region 4 as a buried layer.
Reduces the effect of the parasitic bipolar transistor formed in the portion facing the n ⁺ cathode region 11 and the p ⁺ anode region 3 , prevents re-ignition by the parasitic bipolar transistor, improves dv / dt resistance immediately after turn-off,
It is intended to improve gate loss at the time of turn-on during high-frequency operation.

It is an object of the third prior art invention to provide a static induction thyristor having a new structure which eliminates the parasitic effect of the conventional electrostatic induction thyristor as described above and significantly improves the production yield. It is in.

In order to achieve the above object, according to the third prior art, the first high concentration layer 11 is embedded
When one side surface of the semiconductor layer is viewed from the p ⁺ gate region 4 as the only layer in a direction perpendicular to the one side surface, the region directly above the p ⁺ gate region 4 has a shallower junction depth of the first high-concentration layer 11. The junction depth of the first high-concentration layer 11 is provided deep in the other semiconductor layers.

Dv With this configuration, it is possible to maintain the ──── tolerance immediately after the turn-off at a required high value dt, to reduce gate loss at the time of turn-on during high-frequency operation, and to significantly improve the manufacturing yield. be able to.

In implementing the third prior art invention, the second high-concentration layer 3 described above is further replaced with p ⁺ as a buried layer.
When the other side surface of the semiconductor layer is viewed from the gate region 4 in a direction perpendicular to the other side surface, a region immediately below the p ⁺ gate region 4 is the second region.
The junction depth of the high-concentration layer 3 may be shallow, and the junction depth of the second high-concentration layer 3 may be deep in other semiconductor layers. With this dv configuration, the effect of further increasing the ────withstand capacity immediately after turn-off is obtained dt.

Further, in implementing the third prior art invention, in each of the electrostatic induction thyristors having the above-described configuration, the area between the above-mentioned p ⁺ gate region 4 and the anode electrode 7c is provided between An insulating film 14 ' may be provided. With such a configuration, the various effects described above can be further enhanced.

However, the present inventor has found that in the same structure as the second conventional example, at the time of turn-off, the p ⁺ buried gate region 4 and the p ⁺ short-circuit layer 13 are short-circuited, and extra holes are formed in the p ⁺ short-circuit layer. 13 to the n ⁻ high resistance layer 1,
A phenomenon has been found that the amount of charge extracted from the gate electrode 7b is increased. Therefore, the reverse effect of increasing the turn-off time was found.

On the other hand, in the first conventional example, the main object is to reduce the parasitic capacitance, and the arrangement of the cathode electrode is not mentioned at all. Therefore, the flow of holes at the time of turn-on and the flow of holes at the time of turn-off are not described. The flow is unclear , and no mention is made of the effect of reducing the amount of holes drawn in the present invention described later. Further, in the third conventional example as well, the main purpose is to reduce the effects of the parasitic bipolar transistor and the parasitic diode, and the movement of the holes at the time of turn-on and turn-off is not mentioned at all. No effect of reducing the amount of holes pulled out was found.

Further, the inventor of the present invention has found that in an electrostatic induction device having a buried gate structure, the buried diffusion layer (p ⁺ gate region 4 ) immediately below the region where the n ⁺ cathode region 11 is formed has a high diffusion speed and a wide area even with the same heat treatment time. In contrast, the buried diffusion layer (p ⁺ gate region 4 ) immediately below the region where the n ⁺ cathode region 11 is not formed diffuses relatively slowly, and diffuses to an extremely wide region even with the same heat treatment time. I found that the experiment was not done. That is, FIG. 25 is a schematic cross-sectional structure diagram for explaining the above situation. The p ⁺ gate region 4 as a buried layer immediately below the n ⁺ cathode region 11 is greatly expanded, while the n ⁺ cathode region 11
Schematically shows that the p ⁺ gate region 4 immediately below the region where no is formed has a relatively small spread.
What is clear from FIG. 25 is that the distance between the gate and the cathode varies depending on the portion of the buried layer. As a result, it is apparent that the breakdown voltage between the p ⁺ gate region 4 and the n ⁺ cathode region 11 tends to vary within each segment constituting the electrostatic induction thyristor. In particular, p just below the n ⁺ cathode region 11
^{Since the +} gate region 4 spreads quickly also in the direction of the n ⁺ cathode region 11 , the substantial distance between the gate and the cathode is reduced, so that the withstand voltage between the gate and the cathode is determined by this portion. . Therefore, it is necessary to accurately grasp the condition setting for obtaining a predetermined withstand voltage, and it is necessary to suppress the withstand voltage variation within and between segments.

In the above-mentioned conventional examples 1 to 3, no proposal has been made with respect to the cathode layout arrangement pattern for suppressing the variation in breakdown voltage due to the above-mentioned diffusion variation. The reason for this is that the n ⁺ cathode region 11 is often formed mainly uniformly in the past, and was not formed non-uniformly or non-uniformly as a distributed structure as in the present invention.

FIG. 26 is a schematic cross-sectional view of the element segment in the longitudinal and transverse directions of a unit segment portion of a conventional electrostatic induction thyristor having a buried gate structure in which the n ⁺ cathode region 11 is formed uniformly and uniformly, and a top view thereof. FIG.

[0019] As is evident by FIG. 26, the cathode electrode 7a in the upper part of the n ⁺ cathode region 11 is arranged to fit to the n ⁺ cathode region 11, n-type region (d
It does not contact the ( axial layer) 10 . FIG. 27 shows an SI thyristor 1250 having such a conventional structure.
It is an example of a typical switching waveform in V-100A. In FIG. 27, _IT is an anode current waveform, V _D
Is the anode voltage waveform, I _GP is the gate peak current value, I _RG
Indicates a gate current waveform, and V _RG indicates a gate voltage waveform.

In the waveform of FIG. 27, holes and electrons are separated in the element structure of the SI thyristor by being divided into an on period t ₀ , an accumulation period t ₁ , a falling (fall) period t ₂ , and a tail period t _3. FIGS. 28 to 31 are diagrams schematically showing how they move. 28 corresponds to the ON period t ₀ , FIG. 29 corresponds to the accumulation period t ₁ , FIG. 30 corresponds to the falling (fall) period t ₂ , and FIG. 31 corresponds to the tail period t ₃ . 28 to 31, white circles (（) schematically show holes, and black circles (●) schematically show electrons.

During the ON period (period t ₀ ) , electrons flow from the cathode to the anode, and holes flow from the anode to the cathode via the channel or the gate even if the forward bias between the gate and the cathode is not continuously applied. (FIG. 28). When a reverse bias is applied between the gate and the cathode, hole current from the anode flows into the gate, and holes distributed in a channel portion near the gate and in the n-epitaxial layer between the gate and the cathode also have a reverse bias. Pulled into the gate. On the other hand, electrons continue to flow from the cathode to the anode, but some of them re-enter the cathode region as the potential barrier height in the channel is increased by the reverse gate bias. Accumulation period (t ₁
During the period, the hole current flowing from the anode to the gate is iha, the charge amount is Qha, the hole current flowing from the n epitaxial layer near the channel and between the gate and the cathode is ihb, and the charge amount is Qhb. Further, as described above, the electron current flowing again into the cathode region is represented by ie,
The charge amount is shown in FIG. 29 as Qe.

When the amount of charge extracted from the gate is evaluated, 12
At the time of 50V-300A interruption,

[0023]

## EQU1 ## Qha + Qhb + Qe = 456.6 (μC)

It was. This value is a value obtained from the switching waveform of the conventional SI thyristor at the time of L load.

When the depletion layer spreads between the gates and a sufficiently high potential barrier is formed in the channel, the injection of electrons from the n ⁺ cathode region 11 stops, and during the period t ₂ , that is, during the falling period Enter (FIG. 30).

FIG. 31 corresponds to the tail period (t ₃ period), and shows how the tail current flows.

The problem of the SI thyristor having the conventional structure is that the value of Qha + Qhb + Qe is extremely large. That is, the amount of charge to be extracted from the gate is extremely large. A particularly important point is that Qhb is large. As described above, since the amount of charge extracted from the gate is large, the size of the gate drive circuit is increased, and this is an obstacle to increase the switching speed of the thyristor.
In addition, an increase in turn-off loss at a high temperature causes a destruction of the device.

[0028]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the storage time and the fall time in the turn-off switching performance of an electrostatic induction type semiconductor device, and to significantly reduce the amount of charge drawn from a gate electrode as compared with the prior art. An electrostatic induction semiconductor device having a distributed main electrode structure, which has a reduced turn-off performance and is easy to use, and an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure for further reducing the turn-off withdrawal charge amount. To provide.

Another object of the present invention is to provide an electrostatic induction type semiconductor device having a uniform electrostatic induction main electrode short-circuit structure, which suppresses variations in breakdown voltage between a gate and a source or between a gate and a cathode. The purpose is to provide.

Further, one of the objects of the present invention is to reduce the non-uniformity in the distance after diffusion in the layout of the source or the cathode in order to make the breakdown voltage between the gate and the source or between the gate and the cathode uniform and uniform. An object of the present invention is to provide an electrostatic induction semiconductor device having an extremely suppressed electrostatic induction main electrode short-circuit structure.

More specifically, one of the objects of the present invention is to provide an electrostatic induction type semiconductor device having an electrostatic induction main electrode short-circuit structure capable of effectively extracting a part of the gate extraction charge amount at turn-off from the cathode or source electrode. To provide.

More specifically, one of the objects of the present invention is to provide a distribution structure in a cathode region or a source region so as to easily extract a part of the gate extraction charge amount at the time of turn-off from a cathode or a source electrode, and to provide electrostatic induction. An object of the present invention is to provide an electrostatic induction semiconductor device having a short circuit structure for a main electrode for electrostatic induction, which is provided with a short circuit structure.

More specifically, one of the objects of the present invention is that the gate drive circuit is simplified by effectively reducing the amount of gate withdrawal charge at the time of turn-off, and has an easy-to-use electrostatic induction main electrode short-circuit structure. An object of the present invention is to provide an electrostatic induction semiconductor device.

More specifically, one of the objects of the present invention is to provide an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure with improved gate loss destruction resistance at high temperatures by reducing the gate withdrawal charge amount. To provide.

[0035]

SUMMARY OF THE INVENTION The present invention provides a static induction thyristor or transistor, the cathode metal
An element structure having a distributed main electrode structure in which the electrode or the source metal electrode is in contact with the surface of the substrate where the channel is formed in addition to the cathode diffusion layer or the source diffusion layer on the surface in contact with the semiconductor substrate; , A cathode short circuit or a source short circuit surrounded by a cathode diffusion layer or a source diffusion layer.

The electrostatic induction main electrode (cathode or source) short-circuit structure means a structure in which a short-circuit structure by an electrostatic induction effect is realized in a cathode region or a source region. Specifically, a short-circuit region of the same conductivity type as the control region with the opposite conductivity type to the main electrode region is formed in a relatively low impurity density region surrounded by a relatively high impurity density region in the distributed main electrode structure. Form. The main electrode region and the short-circuit region are short-circuited by the main electrode. The short-circuit region is surrounded by a depletion layer extending from a region having a relatively high impurity density to a region having a relatively low impurity density. There is a potential barrier whose height is controlled by the electrostatic induction effect between the short-circuit region and the control region. Therefore, carriers flowing between the gate, which is the control region, and the short-circuit region are subjected to potential barrier control by the electrostatic induction effect. By providing such a short-circuit region, the effect of bypassing minority carriers to the main electrode can be enhanced.

Further, in the distributed main electrode structure in which the cathode diffusion layer or the source diffusion layer is distributed to suppress the withstand voltage variation, the above-mentioned main electrode short-circuit structure is provided.

The main electrode region is formed of a region having a relatively high impurity density and a region having a relatively low impurity density so that a part of the gate extraction charge at the time of turn-off can be easily extracted from the cathode electrode or the source electrode. In addition, a short-circuit region is provided in a part of a region having a relatively low impurity density, and an electrode structure is formed in contact with a cathode electrode or a source electrode. The region having a relatively low impurity density serves as a so-called conductive channel for bypassing minority carriers to be extracted from the gate region, the short-circuit region serves as a drain so-called, and a part of the minority carriers is also provided from the cathode electrode or the source electrode. It has a configuration that further enhances the effect of easy pulling out.

The distribution type main electrode structure refers to a structure in which the impurity density in the main electrode region is not formed uniformly and non-uniformly, but is formed non-uniformly and non-uniformly. This includes a structure in which a region having a lower impurity density than the region is formed. Alternatively, both of these regions may be of the same conductivity type or of opposite conductivity types. Electrode structure such as cathode electrode or source electrode,
Both regions are in contact at least in part. The point is that the conduction channel of minority carriers is also set in the main electrode region.

On the other hand, the electrostatic induction main electrode short-circuit structure is different from the above-mentioned distributed type main electrode structure in that a main electrode short-circuit structure is further provided, and carriers flowing into the short-circuit region are controlled by potential barrier control by an electrostatic induction effect. This is a structure in which a short-circuit region is provided to further enhance the effect of absorbing minority carriers.

Accordingly, the configuration of the electrostatic induction semiconductor device having the short circuit structure of the electrostatic induction main electrode of the present invention is as follows. That is, the first main electrode regions formed on the first major surface of the high resistivity layer (1) (11,10,15), first or second main of the high resistivity layer (1) A second main electrode region (3) formed on the surface and a control region formed near the first main electrode region (11, 10, 15)
(4) , wherein the control region (4) forms a channel region (5) in the high-resistance layer region (1) and includes a first main electrode region (11, 10, 15) and a second main electrode region (11) . Main current flowing between the main electrode regions (3) of the channel region (5).
In the electrostatic induction type semiconductor device controlled by controlling the height of the potential barrier formed in the first main electrode region,
(11, 10, 15) are regions with relatively high impurity density
The short-circuit region ( ) formed in the region (10) having a relatively low impurity density sandwiched between the region (10) having a relatively low impurity density and the region (11) having a relatively low impurity density. 15) has a structure distributed to each other, and
The electrode structure in contact with the main electrode regions ( 11, 10, 15) is not only in contact with the high impurity density region (11) but also in the low impurity density region (10) and the short-circuit region (15). The short-circuit area (15) is the control area
(4) and having a conductivity type opposite to the relatively high impurity concentration first main electrode region of the same conductivity type (11), the relative from the relatively high impurity concentration regions (11) the potential barrier between the control area by a depletion layer spreading in a region lower (10) within the impurity density (4) possess the said first
1 electrode structure contacting the main electrode regions (11, 10, 15)
The structure is defined as the region (11) having a relatively high impurity density.
It has ohmic contact and has a relatively low impurity density.
Ohmic contact, non-
It has ohmic contact or Schottky contact, the second
1 electrode structure contacting the main electrode regions (11, 10, 15)
In the structure, the relatively low impurity density region (1)
0) The electrode material of the portion in contact with Al, Mo, W, P
t, Ti, Ni or alloys of these with Si, or
A first main electrode region (11,
10, 10), the region having a relatively high impurity density.
(11) is a configuration or stripe that is divided into islands
Or a combination of these
And has a configuration as an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure characterized by having a distribution structure of:

Alternatively, the first main electrode region (1
Regions with relatively high impurity density in (1, 10, 15)
(11) and the region (10 ) having a relatively low impurity density have the same conductivity type as each other and the control region (4).
And has a configuration as an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure characterized by being of the opposite conductivity type.

Alternatively, the first main electrode region (1
Of the regions (1, 10 , 15), the region (10) having a relatively low impurity density is the region (1) having a relatively high impurity density.
It has a configuration as an electrostatic induction type semiconductor element having an electrostatic induction main electrode short-circuit structure, which is of the opposite conductivity type to 1) and of the same conductivity type as the control region (4) .

Alternatively, the control region (4) has a structure as an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure characterized by having an embedded structure.

Alternatively, the control region (4) has a configuration as an electrostatic induction semiconductor device having a short-circuit structure of the electrostatic induction main electrode, characterized by having a notch structure.

Alternatively, the control region (4) has a structure as an electrostatic induction semiconductor device having a short-circuit structure of an electrostatic induction main electrode, which has a planar structure.

Alternatively, the electrostatic induction type semiconductor element is an electrostatic induction thyristor, and has a configuration as an electrostatic induction type semiconductor element having an electrostatic induction main electrode short-circuit structure.

Alternatively, the electrostatic induction type semiconductor device has a configuration as an electrostatic induction type semiconductor device having an electrostatic induction main electrode short-circuit structure, characterized in that it is an electrostatic induction transistor.

Alternatively, the second main electrode region (3)
Is in contact with the short-circuit layer (6) to form the electrostatic induction anode short-circuit.
The structure of the electrostatic induction main electrode short circuit characterized by having
Having a configuration as an electrostatic induction type semiconductor device.

[0050]

The principle of operation of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to the present invention will be described by taking an electrostatic induction thyristor as an example and comparing it with a conventional structure.

FIGS. 16 to 21 are views for explaining the operation principle of the electrostatic induction thyristor having the electrostatic induction main electrode (cathode) short-circuit structure of the present invention, and FIG. 16 is shown in FIG. This is an example in which the cathode electrode 7 a is partially in contact with the n-type region 10. The shape is a combination of an electrostatic induction cathode short circuit and a distributed cathode structure. 17 to 20 show an ON period (t ₀ period), an accumulation period (t ₁ period),
FIG. 9 is a diagram illustrating movement of carriers in a falling period (t ₂ period) and a tail period (t ₃ period). FIG. 21 is a schematic diagram of a potential distribution corresponding to the structure near the cathode, and shows that holes are easily removed to the cathode electrode 7a . However, FIG. 21 is a schematic diagram and does not correspond to FIG.

17 to 20 for explaining the operation principle of the present invention are shown in FIGS. 28 to 31 for explaining the operation principle of the conventional structure.
Respectively.

[0053] The effect of a conventional structure and comparing the distributed cathode structure and the static induction shorted, who of the invention are faster and turn-off gate peak current I _GP is also reduced, and the turn-off time of the gate pull-out charges The amount is also small.

A comparison between FIG. 17 and FIG. 28 shows that there is not much difference in carrier movement during the ON period (t ₀ period). In the present invention, the cathode electrode 7a is n
Since it is also in contact with the n-type region (n-epitaxial layer) 10 and the p ⁺ cathode short-circuit region 15, the hole current in the ON state is not only in the n ⁺ cathode region 11 but also in the n-type region ( cathode electrode 7a via n epitaxial layer) 10 and p ⁺ cathode short-circuit region 15
Flows into. Rather, in the on state, the hole current is reduced by the n-type region (n epitaxial layer) 1 having a relatively low impurity density.
It easily flows to the cathode electrode 7a through the portions of the 0 and p ⁺ cathode short-circuit regions 15 .

A characteristic point in the operation of the present invention appears in the movement of carriers during the accumulation period (t ₁ period) in FIG.
When a reverse bias is applied between the gate and the cathode, the potential (potential) of the gate increases, and the height of the potential barrier of the channel increases. Along with this, holes are extracted from the gate, and its component is mainly Qha due to the hole current iha from the anode. p ⁺ gate region 4
The n epitaxial layer (1) in the vicinity and between the gate and the cathode
A part of Qhb due to the component of hole current ihb due to holes distributed in 0) is extracted from p ⁺ gate region 4, but mainly ihb is p ⁺ cathode short-circuit region 15.
In addition, since the charge flows into the cathode electrode 7a via the n-type region 10, the charge does not become a gate extraction charge. This is because the holes near the n ⁺ cathode region 11 are n-type regions (n
This is because the cathode electrode 7a easily escapes from the p ⁺ cathode short-circuit region 15 formed for the ( axial layer) 10 . The IE component is the same as in the conventional example.

Therefore, in the conventional structure, as shown in FIG.
The gate extraction current was iha + ihb + ie, and the gate extraction charge was Qha + Qhb + Qe, whereas in the present invention, iha−ihb + i, respectively.
e, Qha−Qhb + Qe. Compared with a mere distributed type main electrode structure in which the p ⁺ cathode short-circuit region 15 is not set, the gate extraction charge amount is reduced.

With the introduction of the electrostatic induction main electrode short-circuiting structure of the present invention, the amount of gate withdrawal charge at the time of turn-off is considerably reduced as compared with the conventional example.

The falling period (t ₂ ) shown in FIGS.
Operation period) and tail period (t ₃ period) is the same as the conventional structure.

FIG. 21 is a diagram schematically showing a structure near the cathode of an SI thyristor having an electrostatic induction cathode short-circuit structure of the present invention and a corresponding potential distribution. A-
Along the A 'line and the BB' line, a potential distribution is shown by a broken line and a solid line, respectively. In front of the p ⁺ cathode short-circuit region 15, there is an intrinsic cathode point K ^* having the highest potential barrier height for holes, and the gate-
Intrinsic gate points G ^* exist in the channel region between the gates to control the flow of holes and electrons, respectively. As is apparent from the potential distribution, the holes are formed between the cathode electrode 7a and the n-type region (n epitaxial layer) 10a.
Therefore, the ihb component at the time of turn-off tends to flow mainly into the cathode electrode 7a because the ihb component easily accumulates at the interface with the P ⁺ cathode short-circuit region 15 . Therefore, the Qhb component is reduced from the charge discharged from the gate at the time of turn-off.

[0060]

Embodiment 1 FIG. 1 is a schematic sectional view and a top view of an electrostatic induction semiconductor device having a short circuit structure of an electrostatic induction main electrode according to a first embodiment of the present invention. FIG. 1 shows a unit segment portion. Since 3 is a p ⁺ anode region, the structure of FIG. 1 corresponds to an electrostatic induction thyristor.
If 3 becomes the n ⁺ region, it becomes an electrostatic induction transistor. Hereinafter, a thyristor will be described as an example. In FIG. 1, 1
Is an n ⁻ high resistance layer, 4 is a p ⁺ gate region as a buried layer , 5 is a channel region, and 7a, 7b, and 7c are a cathode electrode, a gate electrode, and an anode electrode, respectively. Reference numeral 10 denotes an n-type region, which is formed by an epitaxial growth layer or the like. 11 is an n ⁺ cathode region, and 15 is a p ⁺ cathode short-circuit region. A structural feature of the first embodiment is that the cathode electrode 7a contacts not only the n ⁺ cathode region 11 but also the n-type region 10 and the p ⁺ cathode short-circuit region 15. N ⁺ cathode region 11 and p ⁺ cathode short-circuit region 15 are short-circuited by cathode electrode 7a. The material of the cathode electrode 7a is Al, Al-S
i, Mo, W, Pt, Ti, Ni, or an alloy or silicide layer thereof. The cathode electrode 7a is n ⁺
The cathode region 11 and the p ⁺ cathode short-circuit region 15 are in ohmic contact, while the n- type region 10 is in ohmic contact, non-ohmic contact, or Schottky contact. The holes distributed in the n-type region 10 are n
N ⁺ (1) so as to be easily accumulated in the contact interface between the mold region 10 and the cathode electrode 7a and in the p ⁺ cathode short-circuit region 15.
An impurity density difference is set between 1) and n (10), and the structure is easily absorbed by the p ⁺ cathode short-circuit region 15. As is clear from the top view, the n ⁺ cathode region 11 is formed in a stripe shape, but the peripheral portion is an n-type region 10 having a relatively low impurity density.
⁺ (11) with respect to the distribution cathode region of n (10), a cathode electrode 7a is in contact with both, to form a distributed cathode electrode structure, furthermore cathode electrode 7a is p ⁺ cathode short-circuit regions 15 and n ⁺ cathode Region (11) is short-circuited.

The n-type region 10 may be a region in which holes are easily accumulated, and may be formed as a p ⁻ region having a lower impurity density than the p ⁺ gate region 4.
In this case, it is desirable that the contact with the cathode electrode 7a be a Schottky contact.

A potential barrier whose height is controlled by the electrostatic induction effect is formed in the depleted region between the p ⁺ cathode short-circuit region 15 and the p ⁺ gate region 4, so that the p ⁺ gate region 4 and the p ⁺ The flow of conduction carriers (holes) with the cathode short-circuit region 15 is controlled.

That is, the p ⁺ cathode short-circuit region 15 is short-circuited to the n ⁺ cathode region 11 and the n ⁺ region 11 sandwiched between the n ⁺ cathode regions 11 has n ⁺ (11) n
(10) The depletion layer expands due to the diffusion potential due to the junction.
The depletion layers are connected to each other, and a potential barrier for holes is formed in front of the p ⁺ cathode short-circuit region 15. The position of the intrinsic cathode K ^* having the highest potential barrier height is schematically shown in FIG. FIG.
As is clear from the potential distribution for holes shown in FIG. 1, holes distributed on the surface side of K ^* are efficiently formed.
It is absorbed by the p ⁺ cathode short-circuit region 15. Such a p
⁺ By actively introducing cathode short-circuit regions 15, corresponding to the formation of the drain region when said of the holes to be absorbed by the cathode electrode 7a. Compared to a structure in which holes are absorbed into the cathode electrode 7a via a simple Schottky junction, the structure has a higher hole absorption effect due to the diffusion potential of the p ⁺ region (15) n (10) junction.

In FIG. 1, the cathode electrode 7a is
However, it is needless to say that it does not necessarily need to be in contact with the n-type region 10. That is,
It may be configured to contact only the n ⁺ (11) p ⁺ (15) region .

[0065]

Embodiment 2 FIG. 2 is a schematic sectional structure view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a second embodiment of the present invention. FIG. 2 corresponds to a buried gate type SI thyristor. Structural features of Figure 2 sandwich the n-type region 10 in n ⁺ cathode region 11, to set the p ⁺ cathode short-circuit regions to further sandwiched between n-type region 10 and the cathode electrode 7a this n ⁺
The point is that the n-type region 10 and the p ⁺ cathode short-circuit region 15 sandwiched by the cathode region 11 are in contact with each other.

By introducing a cathode short-circuit structure in such a distributed main electrode (cathode) structure, holes accumulated in the n-type region 10 having a relatively low impurity density can be efficiently removed from the p ⁺ cathode short-circuit region. 15 to the cathode electrode 7a. As is apparent from the top view, the n ⁺ cathode region 11 is formed in the shape of two stripes, and ap ⁺ cathode short-circuit region 15 is formed in the n-type region 10 sandwiched between the stripes.
⁺ (11) n (10) n ⁺ (11) region and n ⁺ (1
1) Transversely contacting the p ⁺ (15) n ⁺ (11) region. The cathode electrode 7a has an n ⁺ cathode region 11 and p
^{The +} cathode short-circuit region 15 has ohmic contact, and the n-type region has ohmic contact or non-ohmic contact or Schottky contact. Further, n-type region 10 may be formed as a p ⁻ region having a lower impurity density than p ⁺ gate region 4 or a p region.

[0067]

Embodiments 3 and 4 FIGS. 3 and 4 show the third and fourth embodiments of the present invention.
3A and 3B are a schematic sectional structure view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure as an example of the present invention.

[0068] Structural features of FIGS. 3 and 4 are in the arrangement pattern of p ⁺ cathode short-circuit regions 15 sandwiched between the arrangement pattern and the n ⁺ cathode region 11 of the n ⁺ cathode region 11. That is, as described as a problem of the conventional example, the p ⁺ buried gate region 4 immediately below the diffused region of the n ⁺ cathode region 11 greatly expands, causing a variation in the diffusion depth.
In order to solve the problem that the breakdown voltage distribution between the gate and the cathode is varied, the n ⁺ cathode region 11 is divided into small regions, arranged in segments, and formed into a shape sandwiched between the n ⁺ cathode regions 11. p ⁺ cathode short circuit area 15
Is formed. Since the n ⁺ cathode region 11 is divided and arranged on the region corresponding to the channel region 5, the diffusion variation between the gate and the cathode in the unit segment is reduced, and the breakdown voltage distribution becomes uniform.

[0069] an example that is combined with a stripe-shaped n ⁺ cathode region 11 in the third embodiment, the cathode electrode 7a such n ⁺ cathode region 11 and the n-type region 10
Cathode region and p ⁺ cathode short-circuit region 15
As shown in the top view.

[0070] In Example 4 of FIG. 4 n ⁺ cathode region 11
Is still divided into small areas, and no stripes are included. The p ⁺ cathode short-circuit region 15 is formed in a shape sandwiched between these n ⁺ cathode regions 11. The cathode electrode 7a has n ⁺ (11) p ⁺ (15) n ⁺ (11) p ⁺
(15) ... Transversely contacting the distributed cathode short-circuit region.

In Examples 3 and 4, the cathode electrode 7a
And n ⁺ cathode region 11 and p ⁺ cathode short-circuit region 15
Is an ohmic contact, and is an ohmic contact, a non-ohmic contact or a Schottky contact with the n-type region 10. Furthermore, n-type region 10 may be formed as a p ⁻ region or a p region. The point is that the structure is such that holes are accumulated in the n-type region 10 or the p ⁺ cathode short-circuit region 15 having a relatively low impurity density and are easily absorbed by the cathode electrode 7a.

It is to be noted that the electrostatic induction (SI) main electrode short-circuit structure is realized as in the first and second embodiments.
That depletion, together with the cathode short-circuit regions 15 is shorted to the n ⁺ cathode region 11, the n ⁺ A n-type region 10 sandwiched between the cathode region 11, n ⁺ (11) n (10) diffusion potential by bonding Spreads. The depletion layers are connected to each other, and a potential barrier for holes is formed in front of the cathode short-circuit region 15. The position where the height of the potential barrier is the highest is the intrinsic cathode K ^*.
The position of ^* is schematically shown in FIGS. FIG.
Holes efficiently distributed in the surface side than the K ^* As apparent from the potential distribution for holes illustrated in p
⁺ Absorbed in cathode short-circuit region 15. Such p ⁺
By positively introducing the cathode short-circuit region 15, the holes absorbed in the cathode electrode 7a correspond to the formation of the drain region. Compared to a structure in which holes are absorbed into the cathode electrode 7a via a simple Schottky junction, the structure has a higher hole absorption effect due to the diffusion potential of the p ⁺ region (15) n (10) junction.

3 and 4, the cathode electrode 7a has a structure in which the cathode electrode 7a is also in contact with the n-type region 10;
Of course, it is not necessary to touch 0. That is, it may be configured to contact only the n ⁺ (11) p ⁺ (15) region .

[0074]

Embodiments 5 and 6 FIGS. 5 and 6 show the fifth and sixth embodiments of the present invention.
FIG. 4 is a schematic cross-sectional view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure as an example of the present invention. This is an example of a buried gate type SI thyristor. The n ⁺ cathode region 11 is divided into small regions similarly to the third and fourth embodiments, and the p ⁺ cathode short-circuit region 15 utilizing the electrostatic induction effect is replaced with the n ⁺ cathode region 11. It is arranged sandwiched. Electrostatic induction main electrode (cathode) shorted structure of the present invention has the effect of reducing further pulled out of the gate charge amount compared to not having the distributed main electrode structure shorted structure, among the turn-off time, and falling accumulation time t _s This is a structure in which the turn-off time t _{gq, which} is the sum of the times t _f , is reduced. However, it is difficult to reduce the tail time t _tail peculiar to the thyristor structure only by the distributed main electrode (cathode) structure. Therefore, the fifth embodiment corresponds to an example in which the electrostatic induction cathode short-circuit structure and the lifetime control are combined. As the lifetime control, a method such as proton irradiation, electron beam irradiation, and γ-ray irradiation or heavy metal diffusion is performed. In FIG. 5, a mark (x) indicates a position where a desirable defect region is formed in the case of proton irradiation. For example, the thickness of the p ⁺ anode region 3 is about 5 μm, and is formed at a position about 15 μm from the anode surface. p ⁺ anode region 3
In this case, the lime time of electrons is effectively controlled to reduce the tail time.

On the other hand, the sixth embodiment shown in FIG. 6 is an embodiment in which the electrostatic induction cathode short-circuit structure and the electrostatic induction anode short-circuit structure are combined. 6 is an n ⁺ short-circuit layer. The anode short-circuit structure shown in FIG. 6 is an anode short-circuit structure utilizing an electrostatic induction effect, and is an SI anode short-circuit structure. By combining the electrostatic induction cathode short-circuit structure and the SI anode short-circuit structure, the turn-off time t _{gq and} the tail time t _tail can be reduced. Needless to say, lifetime control may be further performed in the sixth embodiment.

[0076] controllable potential barrier by electrostatic induction effect is formed also on the front of the p ⁺ cathode short-circuit regions 15 in Example 5, 6, p ⁺ cathode short-circuit region 15 of the hole to be absorbed into the cathode electrode 7a It is a drain.

[0077]

Embodiments 7, 8, and 9 FIGS. 7, 8, and 9 show an electrostatic induction semiconductor device having a short circuit structure of an electrostatic induction main electrode according to a seventh, eighth, and ninth embodiment of the present invention. 3A and 3B are a schematic sectional structural view and a top view of a unit segment portion of FIG. Example 7-
9 corresponds to an SI thyristor having a notched gate structure, each of which is a static induction main electrode (cathode).
Features a short-circuit structure.

[0078] As is apparent from Example 7 in FIG. 7, n ⁺
The cathode region 11 is formed in a stripe shape, and the cathode electrode 7a is composed of a distributed cathode region composed of n ⁺ (11) and n (10) and an electrostatic induction p sandwiched between the n ⁺ cathode regions 11.
⁺ Transverse contact with cathode short-circuit region 15

In the eighth embodiment, as apparent from FIG. 8, the n ⁺ cathode region 11 is divided into small regions and arranged, and the cathode electrode 7a is composed of the n ⁺ (11) n (10) distributed cathode region and the n ⁺ cathode region 11. Across the electrostatic induction p ⁺ cathode short-circuit region 15 sandwiched between them.

[0080] As is clear from Figure 9 In Example 9, n ⁺
Cathode region 11 is formed in a divided stripe shape and has n region 10 sandwiched between these regions. In n region 10, ap ⁺ cathode short-circuit region 15 is formed, and cathode electrode 7a is ⁺ (11) n (10) distributed cathode region and n ⁺ (11) p ⁺ (15) n ⁺ (11)
It is in transverse contact with the SI cathode short circuit area.
n region (10) sandwiched between n ⁺ cathode region 11 and p
^The structure is such that holes are easily absorbed from the cathode short-circuit region 15 to the cathode electrode 7a efficiently.

In all of the seventh to ninth embodiments, an SI thyristor is used as an example. However, if an n ⁺ region is used instead of the p ⁺ anode region 3, an SIT having a notched gate structure can be formed.

The cathode electrode 7a has an n ⁺ cathode region 11
Ohmic contact with p ⁺ cathode short-circuit region 15 and ohmic contact, non-ohmic contact or Schottky contact with n-type region 10. The n-type region 10 is p
⁺ P ⁻ having relatively lower impurity density than gate region 4
It may be formed as a region or a p region. In such a case, it is desirable to make Schottky contact.

The p ⁺ cathode short-circuit region 15 of the seventh to ninth embodiments
Has a peak of the potential barrier height at the intrinsic cathode point K ^* , which controls the flowing hole current. Holes on the surface side from the K ^* point are efficiently absorbed in the p ⁺ cathode short-circuit region 15.

[0084]

Embodiments 10 and 11 FIGS. 10 and 11 show a first embodiment of the present invention.
It is a typical sectional structure figure near the main electrode of an electrostatic induction type semiconductor element which has an electrostatic induction main electrode short circuit structure as an 0th and an 11th example. Embodiments 10 and 11 each correspond to a static induction semiconductor device having a planar gate structure (planar gate structure). Although it can be formed as a thyristor or a transistor, a thyristor will be described here as an example.

In the embodiment 10 shown in FIG. 10, the n ⁺ cathode region 11 is formed in two stripes, and the p ⁺ cathode short-circuit region 15 is formed between the n ⁺ cathode regions 11. Cathode electrode 7a contacts not only n ⁺ cathode region 11 but also p ⁺ cathode short-circuit region 15. That is, the cathode electrode 7a is in transverse contact with the electrostatic induction cathode short-circuited structure composed of n ⁺ (11) p ⁺ (15) n ⁺ (11). The holes distributed in the n ⁻ / p ⁻ region 10a have a structure that is easily absorbed by the cathode electrode 7a mainly from the p ⁺ cathode short-circuit region 15 sandwiched by the n ⁺ cathode region 11. On the other hand, in Example 11 of FIG. 11, the n ⁺ cathode region 11 is formed in one stripe, and the cathode electrode 7a contacts not only the n ⁺ cathode region 11 but also the surrounding n ⁻ / p ⁻ region 10a. doing. In the n ⁺ cathode region 11, ap ⁺ cathode short-circuit region 15 is formed in an island shape. FIG. 12 is a schematic top view of a unit channel portion of the eleventh embodiment shown in FIG. Striped n ⁺ cathode region 11 and island-shaped p
^The state in which the cathode electrode 7a is in transverse contact with the ⁺ cathode short-circuit region 15 and the n ⁻ / p ⁻ region 10a is shown.

[0086]

Embodiments 12, 13 and 14 The electrostatic induction main electrode short-circuit structure of the present invention comprises an n ⁺ cathode region 11 and an n ⁺ cathode region 1.
Various modifications the arrangement pattern of the p ⁺ cathode short-circuit regions 15 sandwiched between 1 are possible points is the same in planar gate structure. FIG. 13 to FIG. 15 are top views showing an embodiment of such an arrangement of the cathode region 11.
That is, FIG. 13 shows a twelfth embodiment of the present invention, in which an n ⁺ cathode region 1 is provided in a unit channel having a planar structure.
1 is divided into small regions, and the cathode region 11 is divided into small regions.
The p ⁺ cathode short-circuit region 15 is arranged in an island shape.
The cathode electrode 7a is n ⁺ (11) n ⁻ / p ⁻ (10a)
Cathode distribution structure and n ⁺ (11) p ⁺ (15) n
⁺ (11) This is an example of contact with the SI cathode short-circuit structure so as to cover the whole. FIG. 14 shows a thirteenth embodiment of the present invention. In the same planar structure, a cathode electrode 7 is provided for an n ⁺ cathode region 11 arranged in a plurality of channels and a p ⁺ cathode short-circuit region 15 therein.
a and the n ⁺ cathode region 11
This is an example of contact with the n ⁻ / p ⁻ region 10a in the peripheral portion of FIG. Further 15 further sets a wide stripe width of the cathode electrode 7a than in FIG. 14, n ⁺ cathode region 1
Example 14 is Example 14 formed so as to cover the entirety of the 1 and p ⁺ cathode short-circuit regions 15. By arranging and configuring in this manner, the effect of absorbing holes distributed in the n ⁻ / p ⁻ region 10a can be enhanced.

A comparison result between the first embodiment shown in FIG. 1 and the conventional structure shown in FIG. 26 will be described below. Reduction of electrostatic induction main electrode shorted structure according if the gate peak current value I _Gp of the present invention compared with the conventional structure having a uniform cathode electrode structure, increase in the Taofugein G _OFF, reduce the storage time t _s, falling The time t _f is reduced, and thus the turn-off time t _gq (= t
_s + t _f ) and the turn-off switching energy E _OFF (mJ / pulse) are realized.

In particular, holes distributed between the p ⁺ gate region 4 and the n ⁺ cathode region 11 are efficiently formed by the electric field generated by the diffusion potential between the p ⁺ cathode short-circuit region 15 and the n-type region 10. , The amount of charge Q withdrawn from the gate is significantly reduced. The load on the gate drive circuit is reduced by that much, and the t-type weight can be reduced.

When the amount of charge Q (μC) extracted from the gate is compared, it is found that the first embodiment of the present invention is about １ ／ of the conventional example.
It is as follows.

The element of the structure example of the first embodiment shown in FIG.
A comparison of the turn-off switching between the element having the conventional structure shown in FIG. 26 and the element subjected to the life lime control by performing the γ-ray irradiation under a predetermined condition shows that the lifetime control by the γ-ray irradiation is performed for the conventional structure. As compared with the case where the present invention is implemented, the SI thyristor having the electrostatic induction cathode short circuit structure of the present invention has a higher speed and a gate pull-out voltage.
The load Q is small and excellent performance of low loss is exhibited.

[0091] The forward current of the conventional example - Doing comparison voltage characteristic, the V _T in is higher forward voltage drop (ON voltage) V _T large current area in the compared with the conventional example low current region Lower. Therefore, the SI thyristor having the electrostatic induction cathode short circuit structure of the present invention has a high surge withstand capability.

When comparing the relationship between the short-circuit rate of the n ⁺ cathode region and the p ⁺ cathode short-circuit region in the electrostatic induction main electrode (cathode) short-circuit structure and the on-voltage, the short-circuit ratio was suppressed to 30% or less. if a rapid increase in the oN voltage V _T is suppressed.

Embodiments of the present invention are not limited to Embodiments 1 to 14, and various modifications are possible. For example, a shallow p region may be formed in the n ⁺ cathode region 11 at the interface with the cathode electrode 7a without interposing a channel structure. The effect of the p region is that holes distributed in the n ⁺ cathode region 11 are absorbed. This shallow p region can be formed as a shallow layer of about several tens of degrees due to, for example, sintering of Al-Si. This structure may be used in combination with the above p ⁺ cathode short-circuit structure. In the embodiment of the present invention, it has been described that the n-type region 10 may be a p ⁻ or p region. In this case, the shallow p region is in contact with the n-type region (or p ⁻ or p region) 10. It is preferable that the region is surrounded by the n ⁺ cathode region 11 or is surrounded by a potential barrier so as not to cause the problem.

The electrostatic induction main electrode short-circuit structure of the present invention is SI
The present invention can be applied not only to T and SI thyristors but also to other devices having a cathode or source structure. For example, the present invention can be similarly applied to an IGBT, a MOS control thyristor, and the like.

Further, it is needless to say that a configuration in which the conductivity type is reversed in the above embodiment is also possible.

[0096]

According to the electrostatic induction semiconductor device having the electrostatic induction main electrode short-circuited structure of the present invention, the following remarkable effects can be obtained particularly when applied to a thyristor. That is,

The turn-off time (the sum of the accumulation time t _s and the fall time t _f ) can be reduced, and the turn-off switching loss E _OFF can be reduced. Therefore, since the particular storage time t _s in the application surface, such as a high frequency PWM inverter is reduced, it is possible to provide an easy device very easy to use. Further, since the accumulation time t _s can be reduced for each segment, the in-plane variation amount of the wafer is reduced, and the diameter of the wafer can be easily increased.

Furthermore, the amount of charge discharged from the gate is significantly reduced by the main electrode short-circuit structure, and the turn-off gain G
_{Since the OFF} increases, the gate drive circuit can be simplified and downsized, and the price of the entire device can be reduced.

The breakdown voltage characteristics and the leakage current at high temperatures are almost the same as those of the device having the conventional structure in which the lifetime control is not performed.
, The on-characteristics, which are usually in a trade-off relationship, can be kept good despite the improvement in turn-off performance.

[0100] ON voltage V _T at the time of particularly high frequency operation since it has a positive temperature characteristic, since it is difficult to thermally runaway, can be applied to high-frequency operation.

Even if the turn-off performance is extremely increased to the same level as the SIT, the ignition characteristics are hardly affected. That is, the gate voltage and the gate current at the time of ignition hardly change. Even if the turn-off performance is improved, the turn-on switching loss E _ON hardly changes in a low current region. The turn-on high uplink time t _r and E _ON tends to increase the delay time t _d in the high current region does not change. There is also an effect that the surge withstand capability in a high current region is increased.

When the structure of the present invention is applied to the SIT, the above-mentioned effects as advantages of the thyristor can be similarly enjoyed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view and a top view of a unit segment portion of an electrostatic induction semiconductor device having a short circuit structure of an electrostatic induction main electrode according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional structural view and a top view of a unit segment portion of an electrostatic induction semiconductor element having an electrostatic induction main electrode short-circuit structure according to a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional structural view of a unit segment portion of an electrostatic induction type semiconductor device having an electrostatic induction main electrode short-circuit structure according to a fifth embodiment of the present invention.

FIG. 6 is a schematic sectional structural view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a sixth embodiment of the present invention.

FIG. 7 is a schematic sectional view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a seventh embodiment of the present invention.

FIG. 8 is a schematic sectional structural view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to an eighth embodiment of the present invention.

FIG. 9 is a schematic sectional view and a top view of a unit segment portion of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a ninth embodiment of the present invention.

FIG. 10 is a schematic sectional view showing the vicinity of a main electrode of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to a tenth embodiment of the present invention.

FIG. 11 is a schematic sectional view showing the vicinity of a main electrode of an electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure according to an eleventh embodiment of the present invention.

FIG. 12 is a schematic top view of a unit channel portion of the eleventh embodiment shown in FIG.

FIG. 13 shows an example of an electrostatic induction cathode short circuit structure of an electrostatic induction semiconductor device having an electrostatic induction main electrode short circuit structure according to a twelfth embodiment of the present invention.

FIG. 14 shows an example of an electrostatic induction cathode short circuit of an electrostatic induction semiconductor device having an electrostatic induction main electrode short circuit structure according to a thirteenth embodiment of the present invention.

FIG. 15 shows an example of an electrostatic induction cathode short circuit of an electrostatic induction semiconductor device having an electrostatic induction main electrode short circuit structure according to a fourteenth embodiment of the present invention.

FIG. 16 is a schematic diagram for explaining the operation principle of the present invention (combination structure of a distributed cathode structure and an electrostatic induction short-circuit structure).

FIG. 17 is a diagram showing movement of a carrier in an ON state.

FIG. 18 is a diagram showing movement of carriers during an accumulation period.

FIG. 19 is a diagram showing the movement of carriers during a falling period.

FIG. 20 is a diagram showing the movement of carriers during a tail period.

FIG. 21 is an explanatory diagram of the electrostatic induction main electrode short-circuit structure and potential distribution of the present invention.

FIG. 22 is a schematic cross-sectional view of a conventional SI thyristor (conventional example 1).

FIG. 23 is a schematic cross-sectional view of a conventional SI thyristor (conventional example 2).

FIG. 24 is a schematic cross-sectional view of a conventional SI thyristor (conventional example 3).

FIG. 25 is a schematic view showing a state in which a large buried layer immediately below the n ⁺ cathode is formed.

FIG. 26 is a schematic sectional structural view and a top view of a conventional static induction thyristor having a buried gate structure in which a cathode region is formed uniformly and uniformly.

FIG. 27: Typical switching (1250V-100A) in a conventional structure example (without distributed cathode)

FIG. 28 is a diagram showing movement of a carrier in an ON state.

FIG. 29 is a diagram showing the movement of carriers during an accumulation period.

FIG. 30 is a diagram showing the movement of carriers during a falling period.

FIG. 31 is a diagram showing the movement of carriers during a tail period.

[Explanation of symbols]

Reference Signs List 1 n ⁻ high resistance layer 1 a substrate 1 b epitaxial layer 3 p ⁺ anode region 4 p ⁺ gate region 5 channel region 6 n ⁺ short-circuit layer 7 a cathode electrode 7 b gate electrode 7 c anode electrode 10 n-type region 10 an ⁻ / p ⁻ region 11 n ⁺ cathode region 12 support electrode 13 p ⁺ short-circuit layer 14, 14 'insulating layer 15 p ⁺ cathode short-circuit region K ^* intrinsic cathode point G ^* intrinsic gate point

Claims (9)

(57) [Claims] 1. A first main electrode region formed on a first main surface of a high resistance layer region, and a second main electrode formed on a first or second main surface of the high resistance layer region. And a control region formed in the vicinity of the first main electrode region. The control region forms a channel region in the high-resistance layer region, and forms a first main electrode region and a second main electrode region. In an electrostatic induction semiconductor device in which a main current flowing between main electrode regions is controlled by controlling a height of a potential barrier formed in the channel region, the first main electrode region has a relatively high impurity density. A region having a relatively low impurity density and a short-circuit region formed in a relatively low impurity density region interposed between the relatively high impurity density regions; The electrode structure in contact with the main electrode area Partially contacts not only a region with a high material density but also a region with a low impurity density and a short-circuit region, and the short-circuit region is of the same conductivity type as the control region and is a first main electrode region with a relatively high impurity density. opposite conductivity type have, have a potential barrier between said control region by a depletion layer spreading from the relatively high impurity density regions in the relatively impurity density lower region and said first The electrode structure in contact with the main electrode area of
Ohmic contact with the region with high impurity density
Note that the part that contacts the relatively low impurity density area
Ohmic contact, non-ohmic contact or Schottky
An electrode structure having a contact and in contact with the first main electrode region;
Contact with the region having a relatively low impurity density
The electrode material of the part to be used is Al, Mo, W, Pt, Ti, N
i or an alloy or silicide layer of these with Si
And the first main electrode region has a relatively low impurity density.
High areas are divided into islands or striped
Or a combination of these
An electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuit structure, characterized by having a distribution structure comprising: 2. A region having a relatively high impurity density and a region having a relatively low impurity density in the first main electrode region have the same conductivity type as each other and are opposite in conductivity to the control region. 2. An electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuited structure according to claim 1. 3. The first main electrode region, wherein the region having a relatively low impurity density has a conductivity type opposite to that of the region having a relatively high impurity density, and has the same conductivity as the control region. 2. An electrostatic induction semiconductor device having an electrostatic induction main electrode short-circuited structure according to claim 1. Wherein said control region of claim 1 to claim 3, characterized in that it has a buried structure, static induction type semiconductor device having an electrostatic induction main electrode shorted structure according to any one. Wherein said control region of claim 1 to claim 3, characterized by having a notch structure, static induction type semiconductor device having an electrostatic induction main electrode shorted structure according to any one. Wherein said control region of claim 1 to claim 3, characterized in that it has a planar structure, static induction type semiconductor device having an electrostatic induction main electrode shorted structure according to any one of . 7. The method of claim 1 to claim, wherein the static induction type semiconductor device is a static induction thyristor 6
An electrostatic induction semiconductor device having the electrostatic induction main electrode short-circuit structure according to any one of the preceding claims. 8. The semiconductor device according to claim 1, wherein said static induction semiconductor device is a static induction transistor.
7. An electrostatic induction semiconductor device having the electrostatic induction main electrode short-circuit structure according to any one of 6 . 9. The second main electrode region is in contact with a short circuit layer.
Characterized by having an electrostatic induction anode short structure
The static induction main electrode short-circuit structure according to claim 7,
Electric induction type semiconductor element.