JPH0685082A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To surely assure electrical connection between a polycrystalline silicon film and a wiring diffusion layer even through mask alignment is deviated. CONSTITUTION:After forming a gate oxide film 2 and a first polycrystalline silicon film 3 on a substrate 1, a buried contact 5 is formed, and a connecting layer 7 is formed inside the contact 5. Then, framing oxide films 21a and 21b, which have widths larger than the deviation of mask alignment during mask forming and function as stopper when removing polycrystalline silicon, are formed around the inside of the contact 5. Moreover, after forming a second polycrystalline silicon film 8, a resist film 4b whose center line 31 is set above the oxide film 21a is formed as a mask and, by using this mask, unnecessary polycrystalline silicon films 3 and 8 and a gate oxide film 2 are so removed that the surface of substrate is exposed. Thereafter, a wiring layer 10 is formed on the surface of the exposed substrate, the wiring layer 10 and connecting layer 7 are contacted each other by heat treatment thereby connecting both the layers together.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a contact for connecting a wiring layer formed of a diffusion layer and a polycrystalline silicon film is improved.

[0002]

2. Description of the Related Art Conventionally, various methods have been proposed as a method for connecting a diffusion layer and a polycrystalline silicon film in a manufacturing process of a semiconductor device, one of which is a buried contact (gate contact). There is technology. For example, “Electronic Materials, June 1989 issue, 3
A specific example is shown on page 6. 7 and 8 show the outline of the manufacturing method in the order of steps, and the manufacturing method of the buried contact will be described with reference to these drawings.

In FIG. 7, first, a gate oxide film 2 having a thickness of about 15 nm is formed on one main surface of a P-type silicon semiconductor substrate 1 by a thermal oxidation method, and then LPCVD (Low Pres
The first polycrystalline silicon film 3 having N-type conductivity is deposited by the sureChemical Vapor Deposition method (FIG. 7).
(a)). This first polycrystalline silicon film 3 will be described later with reference to FIG.
In order to prevent the resist film from being directly formed on the gate oxide film 2 and deteriorating the performance as a transistor when the resist film 4a made of an organic material as shown in (b) is formed. Has a function as a protective film.

Next, as shown in FIG.
As shown in (b), the resist film 4a having a desired pattern shape
To form. With this photolithography method, an unexposed resist film is spin-coated on a silicon semiconductor substrate, and a mask of a pattern formed by chromium that does not pass ultraviolet rays is placed on the coated unexposed resist film, This is a technique in which a desired resist film 4a is obtained by irradiating ultraviolet rays from a projection analer or a step-and-repeat machine to expose a resist film in a portion without a chrome pattern and then developing. However, in this lithographic technique, the relative position of the mask pattern and the silicon semiconductor substrate may be displaced, so that the position of the formed resist film may be slightly displaced from the correct position. , Abbreviated as mask misalignment).

By the way, as the miniaturization of semiconductor devices progresses, the required mask misalignment (maximum value) becomes smaller (for example, about ± 0.1 μm), which is smaller than the overlay misalignment that can be realized by an exposure machine. This is the current situation. Now, using the resist film 4a formed in the desired pattern as a mask, for example, RIE (Reac
first polycrystalline silicon film 3 by the tive ion etching method.
Are etched using the gate oxide film 2 as an etching stopper, and the gate oxide film 2 is etched using the P-type silicon semiconductor substrate 1 as a stopper to form a buried contact 5. After that, for example, with the resist film 4a as a mask, arsenic 6 is implanted by an ion implantation method at an implantation energy of 40 KeV and an implantation amount of 2.0 × 10 ¹⁵ pieces / cm ² .
The N ⁺ connection layer 7 is formed (FIG. 7B).

After that, the resist film 4a is removed and the LPC is removed.
A second polycrystalline silicon film 8 having N-type conductivity is deposited to a thickness of about 100 nm by the VD method (FIG. 7 (c)). Next, the resist film 4 is formed by the photolithography method described above.
b at a predetermined position, that is, the end of the resist film 4b is shown in FIG. 7 (d).
Of the second polycrystalline silicon film 8 and the first polycrystalline silicon film 3 using the resist film 4b as a mask and the gate oxide film 2 as an etching stopper, and then the gate oxide film 2 is formed. Is etched using the P-type silicon semiconductor substrate 1 as an etching stopper to form a first gate 9 formed by stacking the first polycrystalline silicon film 3 and the second polycrystalline silicon film 8.

After that, for example, arsenic 6 is implanted with an implantation energy 4 by an ion implantation method using the resist film 4b as a mask.
An N ⁺ wiring layer 10 is formed by injecting 0 KeV and an injection amount of 3.0 × 10 ¹⁵ pieces / cm ² (FIG. 7D). Finally, after removing the resist film 4b, the N ⁺ connection layer 7 and the N ⁺ wiring layer 1 are removed.
Heat treatment is performed to activate and diffuse 0, and the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 are brought into contact with each other as shown in FIG.
As a result, the first gate 9 and the N ⁺ wiring layer 10 are electrically connected through the buried contact 5.

[0008]

However, due to the misalignment of the mask, the resist film 4b formed by the photolithography method as shown in FIG.
In other words, if + x ₁ (x ₁ > 0) shifts to the right from the center line 30,
The left end of the ion-implanted N ⁺ wiring layer 10 using the resist film 4b as a mask is shifted to the right by + x ₁ . As a result, the relative positions of the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 become distant, and the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 do not contact each other even if heat treatment is performed to diffuse both N ⁺ layers. Therefore, there is a problem that the first gate 9 and the N ⁺ wiring layer 10 are not electrically connected to each other.

Also, due to the misalignment of mask alignment,
As shown in FIG. 10, the resist film 4b formed by the photolithography method is -x ₂ (x ₂ > 0) to the left of the center line 30.
If it shifts, the first gate 9 is formed using the resist film 4b as a mask.
In the portion in the buried contact 5 where there is no gate oxide film 2 that serves as an etching stopper when etching is performed by the RIE method, the P-type silicon semiconductor substrate 1 is etched by the amount of overetching to form the groove 11.
When ions are implanted using the resist film 4b as a mask, N ⁺
The wiring layer 10 is formed on the surface of the semiconductor substrate 1 and the bottom surface of the groove 11. As a result, as shown in FIG. 10, the depth of the groove 11 is N ^+.
When the depth of the wiring layer 10 is larger than that, the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 are not connected to each other at the groove 11, so that the first gate 9 and the N ⁺ wiring layer 10 are not electrically connected. . Although the depth of the groove 11 is determined by the degree of over-etching, what percentage of the film thickness of one gate 9 to be etched is over-etched depends on the level difference of the base of the film to be etched.

Further, if such a groove 11 is formed, the substrate leakage current will increase. That is, normally, the current path is the N ⁺ wiring layer 10, and the current does not flow to the P-type silicon substrate 1 because it passes through the N ⁺ wiring layer 10, but in the case of FIG. Since the P-type silicon substrate 1 is exposed, it means that the N ⁺ wiring layer 10 which is a current path is cut midway, and the current unavoidably flows to the substrate, increasing the leakage current to the substrate. I will end up.
Therefore, such a semiconductor device cannot be used.

In view of the above points, the present invention has been made in order to solve the above problems, and reliably connects the polycrystalline silicon film and the wiring diffusion layer even if mask misalignment occurs. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of achieving the above.

[0012]

In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises a step of sequentially forming a gate oxide film and a first polycrystalline silicon film on a main surface of a semiconductor substrate. Then, a buried contact is opened in these so as to expose the surface of the semiconductor substrate, and a connection layer is formed in this buried contact. Then, a sidewall film having a width larger than the maximum value of the mask overlay deviation and serving as an etching stopper at the time of removing the polycrystalline silicon film is formed only around the buried contact, and is further contacted with the connection layer. A polycrystalline silicon film 2 is formed. Next, a resist pattern in which a center line to be etched is set is formed on the film serving as an etching stopper, and the resist pattern is used as a mask for the unnecessary first
Then, the second polycrystalline silicon film and the gate oxide film are sequentially removed so that the surface of the semiconductor substrate is exposed, a wiring layer is formed on the exposed surface of the semiconductor substrate, and the connection layer and the wiring layer are further formed by thermal diffusion. It is made to contact.

A method of manufacturing a semiconductor device according to another invention of the present invention is a method of manufacturing a gate oxide film on a main surface of a semiconductor substrate.
After sequentially forming the first polycrystalline silicon film, the resist pattern is used as a mask to remove the unnecessary first polycrystalline silicon film and the gate oxide film until the surface of the semiconductor substrate is exposed. After forming the wiring layer, an interlayer insulating film is formed on the entire surface. Next, a mask of a resist pattern having an opening end portion is formed at a position separated from the end of the wiring layer by a distance larger than the maximum value of the mask overlay deviation, and this mask is used to form the interlayer insulating film and the first mask. After the crystalline silicon film and the gate oxide film are sequentially removed until the semiconductor substrate surface is exposed, the buried contact is opened, and a connection layer having a portion overlapping the wiring layer is formed on the exposed semiconductor substrate surface in the buried contact. The second polycrystalline silicon film is formed in contact with the connection layer in the buried contact.

[0014]

In the present invention, the sidewalk film, which is larger than the mask misalignment of the photolithography method and serves as an etching stopper for the etching of polycrystalline silicon, is bonded so that it has a fixed positional relationship with the polycrystalline silicon film. Since the wiring layer is formed using a resist pattern mask that is formed in the contact and the resist end is positioned on the sidewall film, even if the mask is misaligned, the semiconductor substrate is etched to form a groove. In such a case, the polycrystalline silicon film and the wiring layer can be surely electrically connected.

Further, in another invention of the present invention, a polycrystalline silicon film to be connected and a wiring layer are formed, and a resist having an opening end portion at a position apart from the edge of the wiring layer by a mask misalignment or more. Since the mask of the pattern is formed and the connection layer is formed using this mask, the polycrystalline silicon film and the wiring layer can be surely connected via the connection layer.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. Embodiment 1 FIGS. 1 (a) to 2 (c) are main manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention, which are shown by sectional structural views. Further, FIGS. 3A to 3C are manufacturing process diagrams in the case where the misalignment of the mask alignment is displaced to the right in this embodiment, and as a result, the resist film 4b is displaced to the right of the center line.
(a) to (c) are manufacturing process diagrams in the case where the mask alignment shift in the present embodiment shifts to the left and the resist film 4b shifts to the left from the center line as a result. Also, FIG. 1 (a) to FIG.
Among the reference numerals shown in (c), the same reference numerals as those shown in FIGS. 7 and 8 are the same or corresponding portions.

First, FIG. 1 (a) is the same as that shown in FIG. 7 (b), and the manufacturing method up to that point is the same as the method of the conventional example described above. That is, a gate oxide film 2 having a thickness of about 15 nm is formed on one main surface of a P-type silicon semiconductor substrate 1 by a thermal oxidation method, a first polycrystalline silicon film 3 is deposited by an LPCVD method, and then a photolithography method is performed on the upper surface thereof. After the resist film 4a having a desired pattern shape is formed by using the resist film 4a as a mask, the polycrystalline silicon film 3 and the gate oxide film 2 are etched by the RIE method to form a buried contact 5. Next, the semiconductor substrate 1 exposed in the buried contact 5 is ion-implanted by an ion implantation method to form an N ⁺ connection layer 7 (FIG. 1A).

Next, an interlayer oxide film 21 is deposited on the silicon semiconductor substrate 1 by LPCVD to a film thickness a (for example, about 150 nm here) (FIG. 1 (b)). After that, when the interlayer oxide film 21 is etched by the deposited film thickness a, that is, about 150 nm by, for example, the RIE method, only the end portion of the first polycrystalline silicon film 3 is framed by a framed oxide film having a width b. Membranes 21a and 21b
Remain (Fig. 1 (c)). The framed oxide films 21a and 2a
The width b of 1b is almost the same as the film thickness a of the previously deposited interlayer oxide film 21, and in this case, it is about 150 nm. Further, according to this method, the framed oxide films 21a and 21a
b can always be formed with a desired width only in the end portion of the first polycrystalline silicon film 3. Then, for example, LPCV
An N-type conductive second polycrystalline silicon film 8 is deposited to a thickness of about 100 nm by the D method (FIG. 1 (d)).

Next, a resist film 4b having a desired shape is formed by photolithography (FIG. 2 (a)). here,
The resist film 4b shown in FIG. 2 (a) is formed in a state where there is no mask misalignment, and the mask center line 3
The position of 1 is located to the left of the center line 30 of the related art, and the mask is set so as to be on the framed oxide film 21a.

After that, the resist film 4b is used as a mask for etching by the RIE method, for example. At this time, the second
The polycrystalline silicon film 8 and the first polycrystalline silicon film 3 use the framed oxide film 21a and the gate oxide film 2 as stoppers for etching, and the gate oxide film 2 is the P-type silicon semiconductor substrate 1.
Is used as an etching stopper. Then, after unnecessary portions of the second polycrystalline silicon film 8, the first polycrystalline silicon film 3 and the gate oxide film 2 are etched, the resist film 4b and the framed oxide film 21a are used as a mask, and arsenic 6 is formed by, for example, ion implantation. With an implantation energy of 40 KeV and an implantation amount of 3.0 × 10 ¹⁵ pieces / cm ² to form an N ⁺ wiring layer 10 on the substrate surface (FIG. 2).
(b)).

Finally, the resist film 4b is removed, and the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 are activated and diffused by heat treatment to bring the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 into contact with each other (FIG. 2 (c). )). As a result, the first gate 9 which is a laminated film of the first polycrystalline silicon film 3 and the second polycrystalline silicon film 8 is
It is possible to electrically connect to the N ⁺ wiring layer 10 through the N ⁺ connection layer 7 formed in the buried contact 5.

Next, FIG. 3A shows a case where the resist film 4b is displaced to the right of the center line 31 by + x ₁ (x ₁ > 0).
This will be explained in ~ (c). FIG. 3A is a structural cross-sectional view in the case where the resist film 4b is formed by being shifted + x ₁ to the right of the center line 31 due to mask misalignment. This resist film 4b
As a mask, the second polycrystalline silicon film 8 and the first polycrystalline silicon film 3 use the gate oxide film 2 as an etching stopper, and the gate oxide film 2 uses the P-type silicon semiconductor substrate 1 as an etching stopper. Is etched by.

At this time, since the resist film 4b is shifted to the right from the center line 31 by + x _{1 and} the edge of the resist film 4b is not on the framed oxide film 21a, the second polycrystalline silicon film 8 and the first polycrystalline silicon film 8 are formed. Only the gate oxide film 2 acts as a stopper for etching the silicon film 3. After this etching, using resist film 4b as a mask, arsenic 6 is implanted in the same manner as described above to form N ⁺ wiring layer 10 (FIG. 3B).
At this point, the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 are not in contact with each other.

After that, N ⁺ connection layer 7 and N
^{The +} wiring layer 10 is activated and diffused, and both N ⁺ layers are brought into contact with each other (FIG. 3 (c)). In this case, the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 can be brought into contact with each other by the same heat treatment as that of the conventional example described above because the center line 31 is located on the left side of the conventional center line 30 (FIG. 2A). That is, if the resist pattern having the center line 31 on the framed oxide film 21a is used, the resist film 4
Even if b is shifted to the right by + x ₁ , the resist film 4b approaches the conventional center line 30, so that the relative positions of the N ⁺ connection layer 7 and the N ⁺ wiring layer 10 are different from the center line 31 and the conventional center line. Line 30
It approaches as much as the difference of. Therefore, even if the heat treatment is the same as the conventional one, both N ⁺ layers come into contact with each other, and eventually the first gate 9
And the N ⁺ wiring layer 10 can be electrically connected to each other.

On the contrary, when the resist film 4b is displaced from the center line 31 to the left by -x ₂ (x ₂ > 0), FIG.
This will be explained in ~ (c). FIG. 4A is a structural sectional view in the case where the resist film 4b is displaced from the center line 31 to the left by −x ₂ due to the misalignment of the mask. Using the resist film 4b as a mask, etching is performed by, for example, the RIE method. First, the second polycrystalline silicon film 8 and the first polycrystalline silicon film 3 are etched by using the framed oxide film 21a and the gate oxide film 2 as etching stoppers, but the deviation x of the resist film 4b x
₂ is smaller than the width b of the framed oxide film 21a.

That is, the mask misalignment in the photolithography method has a maximum value of about 0.1 μm in the current technology, and the misalignment x ₂ is 0.1 when the maximum value.
It becomes μm. In the case of this embodiment, the framed oxide film 21a
The width b is set to 150 nm, that is, 0.15 μm as described above, so that the relationship of x ₂ <b is established. That is, even if the deviation x ₂ is the maximum value, the resist film 4
The end of b is on the framed oxide film 21a. Further, when the mask alignment deviation x ₂ is expected to be about 0.2 μm, if the film thickness a of the interlayer oxide film 21 is set to 0.3 μm and the width b of the framed oxide film 21a is also set to 0.3 μm, After all x
The relationship of ₂ <b is established.

[0027] In this embodiment Thus, since a major framing oxide film width b (= thickness a) than the mask misalignment x _2, the deviation x ₂ in the resist film 4b is framed oxide film 21a The width b is smaller than the width b, the end of the resist film 4b does not reach the place where the framed oxide film 21a is not present, and the semiconductor substrate 1 is not etched. As shown in FIG. Both N ⁺ layers are no longer separated by the groove 11.

Next, the gate oxide film 2 is etched using the P-type silicon semiconductor substrate 1 as an etching stopper. Then, using the resist film 4b and the framed oxide film 21a as a mask, arsenic 6 is ion-implanted in the same manner as described above to form the N ⁺ wiring layer 10 on the substrate (FIG. 4B). Then, the resist film 4b is removed, and a heat treatment is performed to remove both N ^+.
The layers are brought into contact with each other to electrically connect the first gate 9 and the N ⁺ wiring layer 10 through the N ⁺ connection layer 7 (FIG. 4C).

As described above, according to the manufacturing method of this embodiment,
When connecting the first gate 9 and the wiring layer 10, after forming the connection layer 7 on the semiconductor substrate 1 exposed in the buried contact 5, a film thickness larger than the maximum value of mask misalignment in the photolithography method. Of an oxide film 21 serving as a stopper for the etching of the polycrystalline silicon is deposited by a film thickness a, and then framed oxidation of a width b (almost equal to the film thickness a) only around the buried contact 5 is performed by the RIE method. Membrane 21
Leave a and 21b. Further, after depositing the second polycrystalline silicon film 8, a resist film 4b is formed on the framed oxide film 21a using a mask having a center line 31 set, and the first and second resist films 4b are used as a mask. After selectively etching the second polycrystalline silicon films 3 and 8 and the gate oxide film 2, a wiring layer 10 is formed.

As a result, even if the mask alignment shifts and the resist film 4b shifts to the left, the silicon semiconductor substrate 1 is not etched and the N ⁺ wiring layer 10 and the N ⁺ connection layer 7 are not separated from each other. Even if the mask alignment shift occurs and the resist film 4b shifts to the right, the original center line 31 position is set to the left of the conventional center line 30 position. The resist film 4b comes close to the resist film 4b and is sufficiently diffused by the conventional heat treatment, so that both N ⁺ layers 7 and 10 are diffused.
Connect. Therefore, the first gate 9 can be reliably connected to the wiring layer 10 through the buried contact 5 even if the resist film 4b is misaligned.

Embodiment 2 FIGS. 5A to 5D and FIG. 6 are main manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention, each of which is shown by a sectional structural view. However, in these figures, the same or corresponding parts as those in FIGS. 7 and 8 are designated by the same reference numerals. First, a gate oxide film 2 having a thickness of about 15 nm is formed on the P-type silicon semiconductor substrate 1 by, for example, a thermal oxidation method, and then an N-type conductive first polycrystalline silicon film 3 is deposited by, for example, an LPCVD method (FIG. 5). (a)). Up to here, the conventional figure 7
This is the same as the manufacturing method shown in (a).

Next, a resist film 4c is formed thereon by a photolithography method, and by using this as a mask, unnecessary portions of the first polycrystalline silicon film 3 and the gate oxide film 2 are removed by etching in this order by, for example, the RIE method. Then, using the resist film 4c as a mask, arsenic 6 is implanted by, for example, an ion implantation method at an implantation energy of 40 KeV and an implantation amount of 3.0 × 10.
Implanting only ¹⁵ pieces / cm ² forms the N ⁺ wiring layer 10 (FIG. 5B).

Then, for example, a BPSG film is deposited by the atmospheric pressure CVD method, and it is reflowed by heat treatment to form an inter-layer reflow oxide film 23. Then N ⁺
A resist film 4d having a pattern such that the opening end is located at a position separated from the end of the wiring layer 10 by a predetermined distance y (y> 0).
Are formed by a photolithography method (FIG. 5C).
Although there is a mask misalignment when forming the resist film 4d, y is set to a value larger than the maximum value of the misalignment. That is, the value of y is a shift of the resist film 4d to the left side by the photolithography method −x
_It is set to a value larger than ₂ (x ₂ > 0), that is, a value satisfying the expression y> x ₂ .

This will be described in detail. The position of the N ⁺ wiring layer 10 is determined by the position of the resist film 4c. This is done using the resist film 4c as a mask as shown in FIG.
This is because the polycrystalline silicon film 3 is etched and then ions are implanted. Next, the edge of the resist film 4d (denoted by the center line 31 in FIG. 5C) is the edge of the N ⁺ wiring layer 10,
That is, it is set at a position separated by a distance y from the end of the resist film 4c. This setting is such that they are separated by a distance y on the photolithographic mask used to form the resist film 4c and the resist film 4d by the photolithography method. Incidentally, when the resist film 4d is formed as shown in FIG. 5C, it means that there is no mask misalignment.

Therefore, as shown in FIG. 5C, "-x ₂ (x ₂ >
0) ”and“ + x ₁ (x ₁ > 0) ”are offset from the center line 31 due to mask superposition. Therefore, if the maximum value of mask misalignment is, for example, 0.1 μm (= x ₂ = x ₁ ), y> 0.2 μm must be set if y> 0.2 μm in the design.
The relationship of x ₂ is established.

Next, using the resist film 4d as a mask, the interlayer reflow oxide film 23, the first polycrystalline silicon film 3 and the gate oxide film 2 are covered with the resist film 4d by the RIE method with the same etching rate. The inter-layer reflow oxide film 23, the first polycrystalline silicon film 3, and the gate oxide film 2 which are not exposed are etched until the surface of the P-type silicon semiconductor substrate 1 is exposed. Continuously, the resist film 4d
With the mask as a mask, for example, arsenic 6 is implanted by ion implantation at an implantation energy of 40 KeV and a dose of 2.0 × 10 ¹⁵ / cm ^2.
Then, the N ⁺ wiring layer 7 is formed (FIG. 5D).

At this time, the center line 31 of the resist film 4d is N
⁺ It is separated from the end of the wiring layer 10 by y, and the value of y is larger than the shift to the left side of the resist film 4d by the photolithography method −x ₂ (x ₂ > 0), that is, y> x ₂ In order to satisfy the formula, even if the resist film 4d is shifted to the left side by −x ₂ , the interlayer reflow oxide film 23, the first polycrystalline silicon film 3, and the gate oxide film 2 are formed on the P-type silicon semiconductor substrate using the resist film 4d as a mask. When etching is performed until 1 is visible, the N ⁺ wiring layer 10 is always exposed in a part of the P-type silicon semiconductor substrate 1 exposed on the surface with a width of y−x ₂ . Then, after that, arsenic 6 is implanted by using the resist film 4d as a mask to form the N ⁺ connection layer 7, so that the N ⁺ wiring layer 10 and the N ⁺ connection layer 7 are always overlapped.

On the contrary, the resist film 4d moves to the right + x ₁ to the right.
Even if the mask misalignment is caused only by (x ₁ > 0) by the photolithography method, only the width y + x ₁ of the exposed P-type silicon semiconductor substrate 1 is exposed as N ⁺ wiring layer 10 on the surface. As a result, the N ⁺ wiring layer 10 and the N ⁺ connection layer 7 also overlap each other. Finally, the resist film 4d is removed, and the N-type conductive second polycrystalline silicon film 8 is formed into a desired shape by, for example, the LPCVD method to form the polycrystalline silicon film 8 and the N ⁺ wiring layer 10. Can be electrically connected via the N ⁺ connection layer 7.

As described above, according to this embodiment, the polycrystalline silicon film 8 to be connected and the wiring layer 10 are formed on the silicon semiconductor substrate 1, and the position y is separated from the end of the wiring layer 10 by a mask misalignment or more. Resist film 4 with resist edge on
Since d is used as a mask and then the connection layer 7 is formed, the polycrystalline silicon film 8 can be surely connected to the wiring layer 10 even if the photoresist film 4d is misaligned (FIG. 6). .

[0040]

As described above, according to the present invention, when the polycrystalline silicon film is connected to the wiring layer through the buried contact, after forming the connection layer, the width is larger than the maximum mask misalignment value. By forming the framed oxide film as a stopper only in the buried contact and setting the center line of the mask resist film of a desired shape on the framed oxide film, there is a mask overlay deviation of the resist film. Also, it becomes possible to reliably electrically connect the polycrystalline silicon film and the wiring layer.

According to another aspect of the present invention, the position of the center line of the mask resist film is made larger than the maximum value of the mask misalignment and separated from the wiring layer, so that the exposed semiconductor substrate is always exposed. Since the wiring layer is exposed and overlaps the connection layer, the connection layer and the wiring layer can be reliably connected even if there is a mask overlay deviation of the resist film. As a result, unlike the conventional example, a groove is not formed on the semiconductor substrate to cause characteristic defects, and the performance and yield of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a structural cross-sectional view after the process of FIG. 1 which similarly illustrates the first embodiment.

FIG. 3 is a manufacturing process diagram when the resist film is displaced to the right of the center line in the first embodiment.

FIG. 4 is a manufacturing process diagram when the resist film is displaced to the left of the center line in the first embodiment.

FIG. 5 is a structural cross-sectional view explaining the method of manufacturing a semiconductor device according to the second embodiment of the invention.

FIG. 6 is a structural cross-sectional view after the process of FIG. 5 which similarly illustrates the second embodiment.

FIG. 7 is a structural cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a structural cross-sectional view after the step of FIG. 7 for explaining a conventional example.

FIG. 9 is a structural cross-sectional view for explaining the problems of the conventional example.

FIG. 10 is a structural cross-sectional view for explaining the problem of the conventional example.

[Description of Reference Signs] 1 P-type silicon semiconductor substrate 2 Gate oxide film 3 First polycrystalline silicon film 4a, 4b, 4c, 4d Resist film 5 Verid contact 6 Arsenic 7 N ⁺ connection layer 8 Second polycrystalline silicon film 9 First gate 10 N ⁺ Wiring layer 21 Interlayer oxide film 21a, 21b Framed oxide film 22 Interlayer reflow oxide film

Claims (2)

[Claims] 1. A gate oxide film and a first polysilicon film of a first conductivity type are sequentially formed on a main surface of a semiconductor substrate of a second conductivity type, and the gate oxide film and the first polysilicon film are then formed. A step of opening a buried contact for exposing the surface of the semiconductor substrate on the film; and an impurity is injected into the surface of the semiconductor substrate exposed in the buried contact to form a connection layer of the first conductivity type, and then a mask Forming a sidewall film having a width larger than the maximum value of overlay deviation around the buried contact, and contacting the connection layer on the surface of the semiconductor substrate including the connection layer, 2 forming a polycrystalline silicon film, and applying a resist to the entire surface of the semiconductor substrate to form a resist pattern having a center line to be etched on the sidewall film. And a step of forming the first and second resist patterns using the resist pattern as a mask.
Of sequentially removing the polycrystalline silicon film and the gate oxide film so that the surface of the semiconductor substrate is exposed, and after implanting impurities into the exposed surface of the semiconductor substrate to form a wiring layer of the first conductivity type, A method of manufacturing a semiconductor device, comprising: diffusing the wiring layer and the wiring layer into contact with each other by heat treatment. 2. A gate oxide film and a first polycrystalline silicon film of the first conductivity type are sequentially formed on a main surface of a second conductivity type semiconductor substrate, and then a resist pattern is formed on the semiconductor substrate. Using this as a mask, the unnecessary first polycrystalline silicon film and gate oxide film are removed by etching until the surface of the semiconductor substrate is exposed; After forming the wiring layer, a step of forming an interlayer insulating film on the entire surface, and applying a resist on the entire surface of the semiconductor substrate, and separating from the edge of the wiring layer by a distance larger than the maximum value of mask overlay deviation. A step of forming a resist pattern having an opening end portion at a position, and the semiconductor substrate surface exposing the interlayer insulating film, the first polycrystalline silicon film and the gate oxide film using the resist pattern as a mask Until the opening of the buried contact by sequential etching and removing impurities, and implanting impurities into the surface of the semiconductor substrate exposed in the buried contact to form a first conductive type connection layer having a portion overlapping with the wiring layer. A method of manufacturing a semiconductor device, comprising: a step of forming a second polycrystalline silicon film of a first conductivity type in contact with the connection layer in the buried contact.