JPH0684892A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a problem that film quality is adversely affected by a step of a wiring layer of a lower layer of a final protection film in a semiconductor element regarding a formation method of the protection film. CONSTITUTION:After a final wiring layer 2 is formed, a plasma CVD silicon oxide film 3 is formed. Thereafter, a plasma chemical vapor growth silicon nitride film or a silicon nitride oxide film 4 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a final protective film.

[0002]

2. Description of the Related Art First of all, reference will be made to the description of the technology of the present invention.

Reference 1: Proceedings of the 3rd Dry Process Symposium IV-2 (1981) (Japan) p. 135
-141 Reference 2: Oki Electric Research and Development, 55 [1] (Sho 63-1)
p. 69-74 Document 3: IEDM88 Tech. Digest, (1
988) IEEE p. 22-25 Document 4: Japanese Journal of A
Applied Physics, 27 [10] (198)
8-8) p. 1962-1965 Reference 5: Japanese Journal of A
Applied Physics, 25 [9] (1986)
-9) p. 764 to 766 In the following, when the above documents are mentioned in the text, they are indicated by the above symbols.

Conventionally, as a final protective film of a semiconductor device,
Plasma chemical vapor deposition silicon nitride film (hereinafter P-SiN
Is used widely.

The forming method is shown in FIG. 2 and will be described below. Insulating film 11 formed on a semiconductor substrate (not shown)
On top of the Al alloy-based material such as Al-1% Si-0.5
% Cu or the like is grown to a thickness of 8000 Å by sputtering, and then the final wiring layer 12 is formed by photolithography (photolithography) patterning and etching.
After this, plasma chemical vapor deposition (hereinafter referred to as plasma CV
D) SiH ₄ and NH ₃ or SiH _4, NH ₃ and N ₂ to be 8000Å grow P-SiN13 as a source gas.
Then, a structure as shown in FIG. Final wiring layer 12
2 after the formation of P-SiN13 before the growth of P-SiN13.
The oxide thin film 14 may be grown as in (b). The thin film 14 is often a phosphorus silicon oxide film (PSG) formed by atmospheric pressure chemical vapor deposition or a plasma CVD silicon oxide film (hereinafter referred to as P-SiO). PSG is the entire final protective film (that is, P
SG + P-SiN) is used for the purpose of reducing the film stress and increasing the reliability of the final wiring layer 12.
SiO is grown for the purpose of preventing the lifetime of the MOSFET from being deteriorated by P-SiN as shown in the above-mentioned reference 3.

[0006]

However, in the above-mentioned method of forming the final protective film, as shown in the above-mentioned reference 1, the step side wall portion, that is, PS of 2A portion and 2B portion of FIG.
The film quality of iN13 deteriorates, and the moisture resistance, which is an important function of P-SiN, is impaired.

Further, the extent to which the film quality of the 2A and 2B portions deteriorates depends on the width and height between the steps, that is, 2C in FIG. 2A and the wiring film thickness. For example, in a certain P-SiN, the 5% hydrofluoric acid etching rate of the 2D portion in FIG.
Å / min. However, the 5% hydrofluoric acid etching rate of the 2A part where the step height is 8000Å and the width between steps is 4 μm is 360Å / min, and the 5% hydrofluoric acid etching rate of the 2B part where the step width is 9000Å is 800Å / mi
n. Is. As described above, the 2A portion having a width of 4 μm between steps has an etching rate about 2 to 3 times that of the flat portion and the 2B portion having a width of 9000 Å shows about 5 times the etching rate of the flat portion, and the P-SiN film quality deteriorates accordingly. I can see that As described above, the poorer the film quality is, the more narrow the space between the steps is, and the film quality of the final protective film P-SiN13 is the poorest in the narrowest space between the steps due to the final wiring layer of the semiconductor element, where the moisture resistance of the semiconductor element is. It determines your ability. In other words, even if the photolithographic patterning and etching techniques are developed and the final wiring layer can be miniaturized, the final protective film P-SiN13
2A, the minimum width of FIG. 2A is limited, which becomes a limiting factor for miniaturization.

The above is the fact that P-SiN is plasma CV.
The same applies to the D silicon oxynitride film (hereinafter P-SiON).

The present invention is based on the above-mentioned final protective film PS.
The film quality of iN deteriorates at the side wall of the step, and its weakness becomes weaker as the width between the steps becomes narrower. Therefore, the iN becomes weakest at the portion where the width between the steps is narrow, and this portion determines the moisture resistance ability. In order to eliminate the problem of becoming a limiting factor, a voltage was applied to the wafer susceptor side after the final wiring layer was formed (hereinafter referred to as bias voltage application).
Plasma-based CVD (Chemical Vapor Deposition) (Plasma CV
D, ECR (Electron Cyclotron
(Resonance) plasma CVD) to grow a silicon oxide film and fill a narrow step portion, and then P-Si
It is an object of the present invention to provide a semiconductor element having a high moisture resistance without a portion having a weak film quality by growing N so that P-SiN does not have a narrow and steep step.

[0010]

In order to achieve the above object, the present invention is directed to the above-mentioned plasma CVD silicon after the final wiring layer is formed and before P-SiN is grown in the final protective film formation of a semiconductor device. By growing an oxide film, P-SiN is grown so that there is no steep narrow step for P-SiN.

[0011]

As described above, according to the present invention, the plasma system C in which the bias voltage is applied to the wafer susceptor side is not used, but P-SiN is already grown after the final wiring layer is formed.
Since the VD insulating film is grown to fill the steep and narrow step formed in the final wiring layer, P at the step side wall portion is formed.
It is possible to avoid the problem that the film quality of SiN becomes weak and the moisture resistance ability is determined there.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a process sectional view of an embodiment of the present invention, which will be described below.

In FIG. 1A, the process is the same as the conventional process until the final wiring layer 2 is formed on the insulating film 1 formed on the semiconductor substrate (not shown). After that, a wafer (substrate) is placed on the wafer susceptor (mounting table) of the CVD device, and a bias voltage is applied to the wafer susceptor side to grow the plasma CVD silicon oxide film 3 by 12000Å. As shown, the silicon oxide film 3 fills the step A of the wiring layer 2. The reason why the silicon oxide film 3 fills the step A of the final wiring layer 2 as described above is that a part of Sf of the raw material gas acts as an etching species and the etching rate is This is because there is etching surface dependency. In this embodiment, an ECR (Elect) capable of applying a bias voltage to the wafer susceptor side as shown in Reference 4 for forming the silicon oxide film 3.
ron Cyclotron Resonance) plasma CVD apparatus was used. The growth condition is that a microwave power source of 2.45 GHz is used as an ECR plasma power source, the output thereof is 2.3 KW, and the bias voltage is 1
A voltage of 1.2 kW was output with an RF (radio frequency) power source of 3.56 MHz. SiH ₄ = 42 as source gas
sccm, O ₂ = 110 sccm, Ar = 140 scc
m, and Ar mainly acts as an etching species. The reaction pressure is 3.2 × 10 ⁻³ Torr. Silicon oxide film 3
When P-SiN4 is grown to 7,000 Å after growing Pt, the result is as shown in FIG. 1 (b). As can be seen from FIG. 1 (b), since P-SiN4 does not grow on a steep step,
There is no portion where the film becomes weak unlike the portions 2A and 2B in FIG. 2 of the conventional technique. At best, it only grows on the protrusion as shown in FIG. 1 (b) B, and the film quality at this portion is extremely weak. The protrusion C of the silicon oxide film 3 is
The width is determined by the etching amount of the portion indicated by D. For example, increasing the Ar flow rate under growth conditions,
By increasing the RF power, which is the bias voltage, the D portion can be enlarged to eliminate the protrusion of C, but the growth rate of the silicon oxide film 3 becomes slower. Was used. Further, although the silicon oxide film 3 is grown in the present embodiment, it may not necessarily be the silicon oxide film.
H ₃ and B ₂ H ₆ may be added to grow a phosphorus boron silicon oxide film, a phosphorus silicon oxide film, or a boron silicon oxide film. That is, the effect of the present invention is not affected as long as it is an insulating film. Of course, various source gases can be used, such as TEO.
It may be S (tetraethoxylane / O ₂ / Ar).

SiH ₄ / NH ₃ / N ₂ O / Ar or SiH ₄ / NH ₃ / N ₂ / N ₂ O / Ar is used to produce Si.
An ON film (silicon oxynitride film) may be grown,
A SiN film (silicon nitride film) may be grown using SiH ₄ / NH ₃ / Ar or SiH ₄ / N ₂ / Ar.

Further, in this embodiment, the silicon oxide film 3 was grown immediately after the final wiring layer 2 was formed. However, as shown in References 2 and 3, PSG and P-SiO are grown before the silicon oxide film is grown. May be grown to about 500 to 1000Å. Depending on the growth conditions of the silicon oxide film 3, PSG and P
-SiO is not necessary either, but even if grown, it does not affect the effect of the present invention.

The reason why various growth conditions and types of films must be considered in this way is as follows.

When the film growth condition or the film type changes, the film characteristics naturally change, and the step filling property, the film stress, the film growth rate, the moisture resistance and the like also change.

That is, the step embedding characteristics are taken into consideration in consideration of the step shape at the time when the final wiring layer of the semiconductor element is formed, and the film stress is taken into consideration in consideration of the wiring reliability as shown in Document 2. Further, in consideration of mass productivity, film growth conditions and film types are determined in consideration of the film growth rate, and step filling is performed.

For the film to be grown next, the growth condition and the type of film are determined in consideration of the film growth rate from the viewpoint of mass productivity and the moisture resistance from the element moisture resistance. Examples are P-SiN, P-S
Since the manufacturing is aimed at moisture resistance of about iON, the film to be grown later is naturally limited to P-SiN or P-SiON.

[0020]

As described above, according to the present invention, as a final protective film for a semiconductor device, a bias voltage is applied to the wafer susceptor side instead of growing P-SiN immediately after forming a final wiring layer. Since the applied plasma-based CVD insulating film is grown so as to fill the steep and narrow step formed in the final wiring layer, the film quality of P-SiN becomes weak at the step side wall portion, and the moisture resistance ability is determined there. It is possible to avoid the problem of being lost. Moreover, since the limiting factor from P-SiN is not added to the miniaturization of the final wiring layer, the present invention becomes more effective as the semiconductor element is miniaturized in the future.

[Brief description of drawings]

FIG. 1 Example of the present invention

FIG. 2 Conventional example

[Explanation of symbols]

 1 Insulating film 2 Wiring layer 3 Silicon oxide film 4 P-SiN

Claims (1)

[Claims] 1. (a) a step of forming an insulating film by a plasma CVD method or an ECR plasma CVD method on a final wiring layer formed on a semiconductor substrate, and (b) on the insulating film, A method of manufacturing a semiconductor device, comprising the steps of forming a plasma-enhanced chemical vapor deposition silicon nitride film or a plasma-enhanced chemical vapor deposition silicon oxynitride film, and the above steps.