JPH07161703A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH07161703A
JPH07161703A JP33956593A JP33956593A JPH07161703A JP H07161703 A JPH07161703 A JP H07161703A JP 33956593 A JP33956593 A JP 33956593A JP 33956593 A JP33956593 A JP 33956593A JP H07161703 A JPH07161703 A JP H07161703A
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step
film
substrate
plasma cvd
high frequency
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Japanese (ja)
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Akihiro Fuse
晃広 布施
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Ricoh Co Ltd
株式会社リコー
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Priority to JP33956593A priority Critical patent/JPH07161703A/en
Publication of JPH07161703A publication Critical patent/JPH07161703A/en
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Abstract

PURPOSE: To restrain damage on a semiconductor device by a bias ECR plasma CVD method, and form a high reliability insulating film with excellent controllability which has an excellent step-covering form.
CONSTITUTION: Firstly a bias ECR plasma CVD process is performed for a specified period by introducing film forming material gas and argon gas, and a silicon oxide film 3 having an overhang form to some extent is formed on a metal wiring 2 as shown by (A). Secondly the introduction of film forming gas is interrupted, and a sputter etching process is performed for a specified period. By primarily etching the overhang part of the silicon oxide film 3, a form shown by (B) is obtained. After that, the bias ECR plasma CVD process and the sputter etching are sequentially repeated, and an insulating film 3 having excellent step-covering form wherein the part between the metal wirings 2 and 2 is filled without voids and flattened as shown by (H) is finally formed.
COPYRIGHT: (C)1995,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体集積回路装置の製造プロセスにおいて層間絶縁膜やパッシベーション膜などの絶縁膜を形成する工程を含む半導体装置の製造方法に関するものである。 The present invention relates to a method of manufacturing a semiconductor device including a step of forming an insulating film such as an interlayer insulating film or a passivation film in the manufacturing process of the semiconductor integrated circuit device. 特に、本発明は半導体集積回路装置の製造プロセスにおいて、層間絶縁膜やパッシベーション膜などの絶縁膜をバイアスECRプラズマCVD法により形成する方法に特徴をもつ半導体装置の製造方法に関するものである。 In particular, the present invention is in the manufacturing process of the semiconductor integrated circuit device, a method for manufacturing a semiconductor device having a feature in a method of forming an insulating film such as an interlayer insulating film or a passivation film by a bias ECR plasma CVD method.

【0002】 [0002]

【従来の技術】現在、LSI(大規模集積回路)に代表される半導体装置の製造プロセスにおいて、特に層間絶縁膜やパッシベーション膜の形成手段としてECR(電子サイクロトロン共鳴)プラズマCVD法が積極的に検討されている。 Presently, LSI in the production process (large scale integrated circuit) on a semiconductor device typified, especially ECR (electron cyclotron resonance) as means for forming the interlayer insulating film or a passivation film plasma CVD method is actively considering It is. ECRプラズマCVD法は低温で膜形成が可能なことや、利用するラジカルやイオンのエネルギーの大きさが揃っていること、また従来の高周波プラズマCVD法に比べてプラズマにより基板が受けるダメージが少なく、さらに高真空領域で膜形成が可能であることなど、多くの利点を備えている。 ECR plasma CVD method that capable of low temperature film formation and it has uniform magnitude of energy of radicals and ions to be used, also less damage the substrate is subjected by the plasma as compared with the conventional high-frequency plasma CVD method, such that it is possible further film formation in a high vacuum region, and a number of advantages.

【0003】また、基板に高周波バイアスを印加し、アルゴンなどのガスを添加して成膜と同時にアルゴンなどのイオンによるスパッタエッチングを起こさせることにより、段差被覆性を向上させたバイアスECRプラズマCVD法が提案されている。 [0003] The high frequency bias is applied to the substrate, by causing the ions by sputter etching such as gas simultaneously argon and deposited by adding such as argon, a bias ECR plasma CVD method with improved step coverage There has been proposed. バイアスECRプラズマC Bias ECR plasma C
VD法は基板に高周波バイアスを印加し、ECRプラズマによりイオン化された陽イオンを基板近傍に発生したイオンシースによる自己バイアス効果により引き寄せ、 VD method a high frequency bias is applied to the substrate, pulled by the self-bias effect by the ion sheath generated positive ions ionized in the vicinity of the substrate by the ECR plasma,
陽イオンによるスパッタエッチングの効果を利用する方法である。 A method of utilizing the effect of sputter etching by cations. スパッタエッチングは基板表面の傾斜部においてより顕著に現われることから、絶縁膜のオーバーエッチング部を優先的にエッチングし、金属配線間をボイドなく埋め込む手法として注目されている。 Sputter etching from appearing more pronounced in the inclined portion of the substrate surface, the over-etching portions of the insulating film is preferentially etched, it has attracted attention as a technique of embedding without voids between the metal wires.

【0004】一般に、バイアスECRプラズマCVD法は成膜とエッチングの同時進行による競争反応である。 [0004] In general, the bias ECR plasma CVD method is a competitive reaction by the simultaneous progress of the deposition and etching.
スパッタエッチングの速度は基板に印加する高周波電力の大きさに比例する。 Rate of sputter etching is proportional to the magnitude of the high-frequency power applied to the substrate. ECRプラズマCVD法の特徴の1つである高い成膜速度に対抗するスパッタエッチング速度を得るため、一般的なバイアスECRプラズマCV To obtain a sputter etch rate against higher deposition rate is one of the characteristics of the ECR plasma CVD method, a general bias ECR plasma CV
D法は、基板に印加する高周波電力が少なくとも600 D method, the high-frequency power applied to the substrate is at least 600
W、通常は1kW程度で使用されている。 W, which is usually used in the 1kW about.

【0005】しかし、このような高出力の高周波バイアスを印加すると、段差被覆性は向上しても、高い高周波電力を印加することにより次のような問題が発生する。 However, when applying a high frequency bias of such high power, even if improved step coverage, the following problem is generated by applying a high frequency power.
その1つは、アルゴンイオンなどの陽イオンのスパッタリングにより金属配線そのものがエッチングされてしまい、配線の寿命を低下させるという問題である。 One is the metal wiring itself by sputtering cations such as argon ions is etched, a problem of lowering the wiring life. 他の問題は、絶縁膜表面のチャージアップが起こり、基板表面とプラズマの間で局所放電が起こり、異物が発生して表面性が著しく低下する点である。 Another problem is occurs charge-up of the insulating film surface, occurs locally discharge between the substrate surface and the plasma is that the surface foreign substance occurs is significantly reduced. これらの問題は積層配線を実現する上では大きな問題となる。 These problems become serious problem in realizing a laminated wiring. また、一般的なバイアスECRプラズマCVD法は、膜形成とスパッタエッチングの同時進行による競争反応であるため、その条件設定が難しいという問題点も挙げられる。 Moreover, typical bias ECR plasma CVD method are the competing reaction by simultaneous film formation and sputter etching, the condition setting and the like is also a problem that it is difficult.

【0006】これらの問題点を解決する方法として次の方法が提案されている。 [0006] The following method as a method for solving these problems have been proposed. 絶縁膜形成の初期過程は高周波バイアスを印加しないか、又は低出力の高周波バイアスを印加して金属配線に損傷を与えないようにし、その後はより高出力の高周波バイアスを印加して絶縁膜の形成を行なう(特開平3−280539号公報参照)。 Or initial process of the insulating film formation without applying a high-frequency bias, or by applying a low output of the high frequency bias so as not to damage the metal wire, then formation of the applied insulating film higher output of the high frequency bias It is carried out (see Japanese Patent Laid-Open No. 3-280539). しかし、その方法によれば、金属配線への損傷は確かに避けられるものの、より高出力の、例えば出力600Wの高周波バイアスを印加しての絶縁膜形成工程では、絶縁膜表面でのチャージアップは避けられず、局所放電による異物の発生や絶縁破壊の問題がある。 However, according to the method, although damage to the metal wiring is certainly avoided, higher-output, for example, in the insulating film forming step of applying a high frequency bias output 600W, charge-up on the surface of the insulating film inevitable not, there is a problem of generation and breakdown of foreign object by the local discharge.

【0007】別の提案として、基板に高周波バイアスを印加せず、またアルゴンガスなどのスパッタリングガスとなるガスを導入しないで成膜のみを行なう工程と、高周波バイアスを印加し、アルゴンなどの陽イオンでスパッタエッチングのみを行なう工程とを繰り返す方法が提案されている(特開平3−52232号公報参照)。 [0007] As another proposal, without applying high frequency bias to the substrate, also the step of performing only deposition without introducing a gas as a sputtering gas such as argon gas, and applying a high frequency bias, cations such as argon method of repeating the step of performing only sputter etching in has been proposed (see Japanese Patent Laid-Open No. 3-52232). しかし、その方法は、成膜工程とスパッタエッチング工程を分離して、成膜のみの工程とスパッタエッチングのみの工程とを繰り返す方法であるため、成膜とスパッタエッチングの同時進行による段差被覆性の向上というバイアスECRプラズマCVD法の特徴を全く利用していない。 However, the method separates the film forming step and the sputter etching process, because it is a method of repeating the only step process and sputter etching of the deposition only, the step coverage by simultaneous film formation and sputter etching It does not use any features of the bias ECR plasma CVD method of improving. そのため、次のような問題が発生する。 For this reason, the following problem occurs. 一般にEC In general, EC
RプラズマCVD法の場合、基板に高周波バイアスを印加しないで成膜を行なうと、金属配線上の絶縁膜形状はオーバーハング形状となることはよく知られており、このオーバーハング形状が金属配線間のスペースのボイドの原因となる。 For R a plasma CVD method, when a film is formed without applying high frequency bias to the substrate, the insulating film shape on the metal interconnection are well known that the overhang shape, between the overhang shape metal wire cause of the void of space. ECRプラズマCVD法の場合は、一般にその成膜速度が大きく、シリコン酸化膜で数1000 For ECR plasma CVD method, generally large its film formation rate, the number of silicon oxide film 1000
Å/分〜数μm/分の値である。 Å / min to the number of which is μm / min value. したがって、半導体装置の素子寸法及び金属配線の微細化が進むにつれて、オーバーハング形状によるボイドの発生という問題は、絶縁膜形成開始後のごく短時間のうちに決定的となり、その後にスパッタエッチングを行なってもボイドの解消は不可能となる。 Thus, as the device size and miniaturization of metal wiring of a semiconductor device advances, the problem that the generation of voids due to overhang shape becomes a decisive within a very short time after the start of the insulating film formed, subjected to subsequent sputter etching elimination of voids also becomes impossible. この問題を解決するには、成膜工程開始後のごく僅かの時間、例えば成膜速度が1μm/分、デザインルールのライン・アンド・スペース(L/S)が0.5μm/0.5μmの場合では10〜20秒程度の時間を制御下におくことが必要となるが、プラズマ状態の不安定さからいっても再現性が低く、非常に不安定なプロセスになるという問題がある。 To resolve this problem, very little time after the start film formation step, for example, the deposition rate is 1 [mu] m / min, line and space of the design rule (L / S) of 0.5 [mu] m / 0.5 [mu] m Although it is necessary to be under the control of about 10 to 20 seconds in the case, even if the instability of the plasma state low reproducibility, there is a problem that the very unstable process.

【0008】 [0008]

【発明が解決しようとする課題】本発明は以上に述べたような問題点を解決するために、バイアスECRプラズマCVD法の特徴を有しつつ、しかも半導体装置に与える損傷を抑え、優れた段差被覆形状を有する信頼性の高い絶縁膜を制御性よく形成することを特徴とするものである。 [SUMMARY OF THE INVENTION The present invention to solve the problems as described above, while having the features of the bias ECR plasma CVD method, moreover suppress damage to the semiconductor device, excellent step it is characterized in that to form the insulating film having a high reliability having a coating shape with good controllability.

【0009】 [0009]

【課題を解決するための手段】本発明は、絶縁膜を形成する工程では、基板に低出力の高周波バイアスを印加しつつ、成膜原料となるガスと、イオン化して陽イオンとなる元素を含むガスとを同時に導入し、成膜と陽イオンによるスパッタエッチングとを同時に行なわせる第1の工程と、基板に低出力の高周波バイアスを印加しつつ、 The present invention SUMMARY OF THE INVENTION, in the step of forming an insulating film, while applying the high frequency bias of the low output to the substrate, the gas as a film forming material, an element made of a cation to ionize simultaneously introducing a gas comprising a first step of causing the sputter etching by film formation and cation simultaneously while applying the high frequency bias of the low output to the substrate,
成膜原料となるガスを導入せず、イオン化して陽イオンとなる元素を含むガスのみを導入して陽イオンによるスパッタエッチングのみを行なわせる第2の工程とを繰り返すことを特徴とする半導体装置の製造方法である。 Without the introduction of gas as a film forming material, wherein a repeating the second step of introducing only gas containing an element serving as cations ionized performed only sputter etching by cation it is a method of manufacture. これにより、バイアスECRプラズマCVDプロセスによる成膜と、陽イオンによるスパッタエッチングのプロセスを繰り返すことによって、半導体装置に与える損傷を抑え、金属配線間をボイドなしに埋め込み、かつ優れた段差被覆性を有する絶縁膜を形成する。 Thus, with the film deposition by a bias ECR plasma CVD process, by repeating the process of sputter etching by cation, suppressing damage to the semiconductor device, embedded between metal lines without a void, and excellent step coverage forming an insulating film.

【0010】好ましい態様では高周波バイアスの電力を50〜500Wに設定する。 [0010] In a preferred embodiment sets the power of the high frequency bias 50~500W. 本発明での好ましい条件は、第1の工程の成膜速度をA(Å/分)、その第1の工程の1回当りの成膜時間をt 1 (分)とし、第2の工程のエッチング速度をB(Å/分)、その第2の工程の1回当りのエッチング時間をt 2 (分)としたとき、次の関係式が成り立つように設定する。 Preferred conditions in the present invention, the deposition rate of the first step A (Å / min), and the deposition time per the first step t 1 and (minute), the second step the etch rate B (Å / min), when the etching time per the second step t 2 and (min) is set so that the following relationship is established. 0.4≦A・t 1 /B・t 2 ≦20 0.4 ≦ A · t 1 / B · t 2 ≦ 20

【0011】本発明に用いるECRプラズマCVD装置は、基板に高周波バイアスを印加できるECRプラズマCVD装置である。 [0011] ECR plasma CVD apparatus used in the present invention is a ECR plasma CVD apparatus capable of applying high frequency bias to the substrate. 一般に用意されている高周波電源はその出力が1kW以上の能力を有するものが多いが、本発明では低出力の高周波バイアスで効果が得られるので、高々500Wクラスの高周波電源を用意すればすむ。 While high frequency power supply which are generally prepared has many of its output has a capacity of more than 1 kW, in the present invention the effect is obtained at a high frequency bias of low power, need be no more than provide a high frequency power source 500W class.

【0012】本発明においてスパッタエッチング用として用いるガスはイオン化して陽イオンとなる元素を含むガスであれば使用可能であり、通常はスパッタ効率や取扱いの容易さからいってAr(アルゴン)ガスを選ぶのが最も適切である。 [0012] Gas used for the sputter etching in the present invention can be used as long as the gas containing an element serving as cations ionized, usually the sputtering efficiency and handling of said ease Ar (argon) gas it is most appropriate to choose. He(ヘリウム)もまたイオン化してHeイオンを供給するので、単体で、又はArガスとの混合ガスとして使用することができる。 Since He (helium) also ionized to supply the He ions can be used as a mixed gas of alone or in Ar gas. 絶縁膜形成用に用いる原料ガスは、形成する膜がシリコン酸化膜の場合はシラン(SiH 4 )と酸素が好ましく、また形成する膜がシリコン窒化膜の場合はシランと窒素が好ましい。 Raw material gas used for the insulating film formation film to form the oxygen is preferred as silane (SiH 4) in the case of silicon oxide film, and if the film to be formed is a silicon nitride film silane and nitrogen are preferred.

【0013】 [0013]

【実施例】図1に本発明に従ってシリコン酸化膜を形成したときのプロセスを工程順に示す。 It shows a process when forming the silicon oxide film according to the present invention in EXAMPLES 1 in order of steps. 成膜原料ガスとしてシランと酸素を用い、またスパッタリング用のガスとしてアルゴンを用いた。 Using silane and oxygen as a film-forming raw material gas and argon was used as the gas for sputtering. 図中で(A),(C), In Figure (A), (C),
(E),(G)は成膜原料ガスとスパッタリング用ガスをともに導入して行なう、いわゆるバイアスECRプラズマCVD工程後の形状を示している。 (E), shows (G) is performed by introducing both the film-forming raw material gas and the sputtering gas, the shape after the so-called bias ECR plasma CVD process. 一方、(B), On the other hand, (B),
(D),(F),(H)はスパッタリング用ガスのみを導入して行なうスパッタエッチング工程後の形状を示している。 (D), shows (F), (H) the shape after the sputter etching step performed by introducing only sputtering gas. 両工程での基板に印加する高周波バイアスの出力は250Wとした。 The output of the high frequency bias applied to the substrate in both steps was 250 W.

【0014】先ず、バイアスECRプラズマCVD工程を所定の時間行なうと、(A)のように、基板1上の金属配線2上のシリコン酸化膜3は多少オーバーハング形状を有するものとなる。 [0014] First, when a bias ECR plasma CVD process a predetermined time, as shown in (A), a silicon oxide film 3 on the metal wiring 2 on the substrate 1 is assumed to have some overhang. 通常のバイアスECRプラズマCVDではこのようなオーバーハング形状が発生しないように高出力の高周波バイアスを印加するが、本発明では後にスパッタエッチング工程を有するため、多少のオーバーハング形状は許容できる。 While normal bias ECR plasma CVD in such overhang shape to apply a high output of the high frequency bias so as not to generate, because it has a sputter etch step after the present invention, some overhang shape is acceptable.

【0015】次に、成膜原料ガスの導入を中止し、スパッタエッチング工程に移る。 Next, to stop the introduction of the film-forming material gas, it moves to a sputter etching process. スパッタエッチング工程を所定時間行なったときの形状は、オーバーハング部が優先的にスパッタエッチングされ、その結果(B)に示されるような形状となる。 Shape when subjected to sputter etching process a predetermined time, the overhang portion is preferentially sputter etching, a shape as shown in the result (B). その後さらにバイアスECRプラズマCVD工程を行なうと、(C)に示される形状となり、その後さらにスパッタエッチングを行なうと(D)に示される形状となる。 When then further performing bias ECR plasma CVD process, the a shape shown (C), the shape then further shown in Doing sputter etching (D).

【0016】このようにバイアスECRプラズマCVD [0016] The bias ECR plasma CVD in this way
工程とスパッタエッチング工程を順次繰り返していくことによって、最終的には(H)に示されるように、金属配線2,2間がボイドなく埋め込まれ、平坦化も行なわれた優れた段差被覆形状を有する絶縁膜3が形成される。 By sequentially repeating the steps a sputter etching process, as is ultimately shown in (H), while the metal wires 2, 2 are embedded without voids, excellent step coverage shape was also performed planarized insulating film 3 having is formed. このように、バイアスECRプラズマCVD工程とスパッタエッチングを繰り返すことにより、低出力の高周波バイアスであっても優れた段差被覆性を有する絶縁膜が半導体装置に与える損傷を抑えながら形成させることができる。 Thus, by repeating a bias ECR plasma CVD process and sputter etching, it can be formed while suppressing damage insulating film having a step coverage excellent even radio frequency bias of low output has on the semiconductor device.

【0017】(実施例1)4インチの単結晶シリコンウエハ上に既知の方法によりアルミニウム薄膜を約900 [0017] (Example 1) to 4 inches aluminum thin film by a known method on a single crystal silicon wafer of about 900
0Åの厚さに形成し、写真製版とエッチングによりライン・アンド・スペース(L/S)=0.7μm/0.7μ Formed to a thickness of 0 Å, photolithography and etching by a line-and-space (L / S) = 0.7μm / 0.7μ
mにパターン化したものを基板とした。 Those patterned to the substrate to m. バイアスECR Bias ECR
プラズマCVD及びスパッタエッチングの条件は以下の通りである。 Conditions of the plasma CVD and sputter etching are as follows.

【0018】バイアスECRプラズマCVD工程 SiH 4流量: 10sccm O 2流量 : 15sccm Ar流量 : 20sccm スパッタエッチング工程 Ar流量 : 20sccm 両工程とも圧力は1mTorr、基板温度は150℃、マイクロ波電力は700W、高周波(13.56MHz)電力は250Wである。 The bias ECR plasma CVD process SiH 4 flow rate: 10 sccm O 2 flow rate: 15 sccm Ar flow rate: 20 sccm sputter etching process Ar flow rate: 20 sccm pressure both step 1 mTorr, substrate temperature 0.99 ° C., the microwave power 700 W, a high frequency ( 13.56MHz) power is 250W.

【0019】各工程の条件をこのように設定し、バイアスECRプラズマCVD工程の単位時間を3分間、スパッタエッチング工程の単位時間を5分間とし、またそれらを交互に繰り返す繰返し回数を8回とした。 [0019] set to the conditions of each process, the bias ECR plasma CVD process unit time 3 minutes, the unit time of the sputter etching step was for 5 minutes, also was 8 times the number of repetitions to repeat them alternately . その結果、金属配線間をボイドなく埋め込んで、かつ表面性も平坦なシリコン酸化膜が得られた。 As a result, embedded without voids between the metal wires, and the surface properties were also obtained flat silicon oxide film.

【0020】(実施例2)実施例1と同様であるが、基板のライン・アンド・スペース(L/S)=0.5μm [0020] (Example 2) is similar to Example 1, the substrate of line and space (L / S) = 0.5 [mu] m
/0.5μmとし、バイアスECRプラズマCVD工程の単位時間を2分間、スパッタエッチング工程の単位時間を6分間とし、繰返し回数を8回とした。 And /0.5Myuemu, bias ECR plasma CVD process unit time 2 minutes, the unit time of the sputter etching step was 6 minutes, and the number of repetitions and 8 times. その結果、 as a result,
金属配線間をボイドなく埋め込んで、かつ表面性も平坦なシリコン酸化膜が得られた。 Embedded without voids between the metal wires, and the surface properties were also obtained flat silicon oxide film.

【0021】第1の工程、すなわちバイアスECRプラズマCVD工程の成膜速度をA(Å/分)、その1回当りの成膜時間、すなわち第1の工程の単位時間をt The first step, i.e. the deposition rate of a bias ECR plasma CVD process A (Å / min), the film formation time of the per, i.e. a unit time of the first step t
1 (分)とする。 And 1 (minute). 第2の工程、すなわちスパッタエッチング工程のエッチング速度をB(Å/分)、その1回当りのエッチング時間、すなわち第2の工程の単位時間をt The second step, i.e., the etch rate of the sputter etching process B (Å / min), the etching time of the per, i.e. a unit time of the second step t 2 (分)とする。 And 2 (minutes).

【0022】図2に、基板に印加する高周波バイアスの出力を変化させながら、バイアスECRプラズマCVD [0022] Figure 2, while changing the output of the high frequency bias applied to the substrate, the bias ECR plasma CVD
法によりシリコン酸化膜を成膜したときの成膜速度を示す。 It shows the deposition rate at the time of forming a silicon oxide film by law. 高周波バイアス電力が0のときの成膜速度はバイアスを印加しない場合の成膜速度であり、約800Å/分である。 Deposition rate at a high frequency bias power is 0 is the deposition rate when no bias is applied, is about 800 Å / min. 一方、高周波バイアス電力を250W印加した場合の成膜速度Aは、グラフから約600Å/分と読み取ることができる。 On the other hand, the film forming speed A in the case of 250W applying high frequency bias power is capable of reading about 600 Å / min from the graph. また、この結果から、高周波バイアスを250W印加することによって得られる見掛けのエッチング速度Bは、 800−600=200(Å/分) と考えられる。 Further, from these results, the etching rate B of apparent obtained by 250W applying high frequency bias is believed to 800-600 = 200 (Å / min). ここで、第1の工程の成膜速度Aと単位時間t 1との積A・t 1と、第2の工程のエッチング速度Bと単位時間t 2との積B・t 2との比A・t 1 /B・t 2によって両工程の繰返し周期を評価する。 Here, first the product A · t 1 the deposition rate A and the unit time t 1 step, the ratio A and the product B · t 2 between the etching rate B and the unit time t 2 of the second step by · t 1 / B · t 2 to evaluate the repetition period of both steps.

【0023】実施例1及び2を含み、さらに条件を変えて測定を行ない、金属配線間にすがなく埋め込めるかどうかを評価した結果を表1に示す。 [0023] include Examples 1 and 2, further subjected to measurement under different conditions are shown in Table 1 The results of evaluation of whether embed no be between the metal wires.

【0024】 [0024]

【表1】 [Table 1]

【0025】条件の欄で、例えば(5,3)×5は第1 [0025] In the conditions of column, for example, (5,3) × 5 is first
の工程の単位時間が5分、第2の工程の単位時間が3 Units of the process time is 5 minutes, the unit time of the second step 3
分、繰返し回数が5回であることを示している。 Minute, shows that the number of repetitions is 5 times. ライン・アンド・スペース(L/S)は小さい方が良好な絶縁膜の形成が難しく、表中の○は金属配線間の層間膜にすがなく埋込みができた結果を示し、×印はすが発生した結果を示している。 Line and space (L / S) is smaller is difficult to form a good insulating film, ○ in the table shows the results that could embedding no to the interlayer film between the metal wiring, × mark to There are shown the results that occurred.

【0026】 [0026]

【発明の効果】本発明によれば低出力の高周波バイアスによるバイアスECRプラズマCVD工程とスパッタエッチング工程を繰り返すことにより、半導体装置に与える損傷を抑えることができ、金属配線間をボイドなく埋め込んで、かつ表面性も平坦な、段差被覆性に優れた絶縁膜を得ることができる。 According to the present invention by due to the low output of the high frequency bias repeated bias ECR plasma CVD process and the sputter etching process, it is possible to suppress damage to the semiconductor device, embedded without voids between the metal wires, and surface resistance even flat, it is possible to obtain an excellent insulating film step coverage. また、本発明の工程はバイアスECRプラズマCVD工程とスパッタエッチング工程であり、それぞれの時間と繰返し回数という制御しやすいパラメータを最適化することにより、種々の配線寸法に対応することができので、再現性も得られやすく、制御性に優れている。 Further, the process of the present invention is a bias ECR plasma CVD process and the sputter etching process, by optimizing the control easily the parameters that each time the number of repetitions, so it is possible to cope with various wiring sizes, reproduction sex easily be obtained, and excellent controllability.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】一実施例におけるシリコン酸化膜形成工程を示す工程断面図である。 1 is a process cross-sectional view showing a silicon oxide film forming step in an embodiment.

【図2】一実施例における高周波バイアス電力に対する成膜速度を示す図である。 2 is a diagram showing a deposition rate for the high-frequency bias power in an embodiment.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 シリコン基板 2 金属配線 3 シリコン酸化膜 1 silicon substrate 2 wiring metal silicon oxide film

───────────────────────────────────────────────────── ────────────────────────────────────────────────── ───

【手続補正書】 [Procedure amendment]

【提出日】平成6年9月2日 [Filing date] 1994 September 2

【手続補正1】 [Amendment 1]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】請求項3 [Correction target item name] claim 3

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【手続補正2】 [Amendment 2]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】0003 [Correction target item name] 0003

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【0003】また、基板に高周波バイアスを印加し、アルゴンなどのガスを添加して成膜と同時にアルゴンなどのイオンによるスパッタエッチングを起こさせることにより、段差被覆性を向上させたバイアスECRプラズマCVD法が提案されている。 [0003] The high frequency bias is applied to the substrate, by causing the ions by sputter etching such as gas simultaneously argon and deposited by adding such as argon, a bias ECR plasma CVD method with improved step coverage There has been proposed. バイアスECRプラズマC Bias ECR plasma C
VD法は基板に高周波バイアスを印加し、ECRプラズマによりイオン化された陽イオンを基板近傍に発生したイオンシースによる自己バイアス効果により引き寄せ、 VD method a high frequency bias is applied to the substrate, pulled by the self-bias effect by the ion sheath generated positive ions ionized in the vicinity of the substrate by the ECR plasma,
陽イオンによるスパッタエッチングの効果を利用する方法である。 A method of utilizing the effect of sputter etching by cations. スパッタエッチングは基板表面の傾斜部においてより顕著に現われることから、絶縁膜のオーバーエッチング部を優先的にエッチングし、金属配線間をボイド(本明細書では「空隙」の意味で使用している)なく埋め込む手法として注目されている。 Sputter etching from appearing more pronounced in the inclined portion of the substrate surface, the over-etching portions of the insulating film preferentially etched, voids between the metal wires (herein is used in the sense of "voids") It has been attracting attention as a method of embedding without.

【手続補正3】 [Amendment 3]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】0010 [Correction target item name] 0010

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【0010】好ましい態様では高周波バイアスの電力を50〜500Wに設定する。 [0010] In a preferred embodiment sets the power of the high frequency bias 50~500W. 本発明での好ましい条件は、第1の工程の成膜速度をA(Å/分)、その第1の工程の1回当りの成膜時間をt 1 (分)とし、第2の工程のエッチング速度をB(Å/分)、その第2の工程の1回当りのエッチング時間をt 2 (分)としたとき、次の関係式が成り立つように設定する。 Preferred conditions in the present invention, the deposition rate of the first step A (Å / min), and the deposition time per the first step t 1 and (minute), the second step the etch rate B (Å / min), when the etching time per the second step t 2 and (min) is set so that the following relationship is established. 0.4≦A・t 1 /B・t 22.0 0.4 ≦ A · t 1 / B · t 2 ≦ 2.0

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 6識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/768 ────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. 6 in identification symbol Agency Docket No. FI art display portion H01L 21/768

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 基板に高周波バイアスを印加できるEC 1. A capable of applying high frequency bias to the substrate EC
    RプラズマCVD法により基板上に絶縁膜を形成する工程を含む半導体装置の製造方法において、 絶縁膜を形成する前記工程では、基板に低出力の高周波バイアスを印加しつつ、成膜原料となるガスと、イオン化して陽イオンとなる元素を含むガスとを同時に導入し、成膜と陽イオンによるスパッタエッチングとを同時に行なわせる第1の工程と、 基板に低出力の高周波バイアスを印加しつつ、成膜原料となるガスを導入せず、イオン化して陽イオンとなる元素を含むガスのみを導入して陽イオンによるスパッタエッチングのみを行なわせる第2の工程とを繰り返すことを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device including a step of forming an insulating film on a substrate by R a plasma CVD method, in the step of forming an insulating film, while applying the high frequency bias of the low output to the substrate, the film-forming raw material gas If, at the same time introducing a gas containing an element serving as cations ionized, a first step of causing the sputter etching by film formation and cation simultaneously while applying the high frequency bias of the low output to the substrate, without the introduction of gas as a film forming material, wherein a repeating the second step of introducing only gas containing an element serving as cations ionized performed only sputter etching by cation the method of production.
  2. 【請求項2】 基板に印加する高周波バイアスの電力が50〜500Wの範囲内である請求項1に記載の半導体装置の製造方法。 2. A method of manufacturing a semiconductor device according to claim 1 electric power of the high frequency bias is in the range of 50~500W applied to the substrate.
  3. 【請求項3】 前記第1の工程の成膜速度をA(Å/ Wherein the deposition rate of the first step A (Å /
    分)、その第1の工程の1回当りの成膜時間をt Min), the first film formation time per step t
    1 (分)とし、前記第2の工程のエッチング速度をB 1 and (min), the etching rate of the second step B
    (Å/分)、その第2の工程の1回当りのエッチング時間をt 2 (分)としたとき、次の関係式が成り立つように条件を設定する請求項1又は2に記載の半導体装置の製造方法。 (Å / min), then the second etching time per step was t 2 (min), the semiconductor device according to claim 1 or 2 to set the conditions so that the following relational expression is established the method of production. 0.4≦A・t 1 /B・t 2 ≦20 0.4 ≦ A · t 1 / B · t 2 ≦ 20
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