KR100203896B1 - Manufacturing method of the gate electrode - Google Patents
Manufacturing method of the gate electrode Download PDFInfo
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- KR100203896B1 KR100203896B1 KR1019950050441A KR19950050441A KR100203896B1 KR 100203896 B1 KR100203896 B1 KR 100203896B1 KR 1019950050441 A KR1019950050441 A KR 1019950050441A KR 19950050441 A KR19950050441 A KR 19950050441A KR 100203896 B1 KR100203896 B1 KR 100203896B1
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- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 19
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 17
- 125000001153 fluoro group Chemical group F* 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000000470 constituent Substances 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 59
- 239000010408 film Substances 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 229920005591 polysilicon Polymers 0.000 description 19
- 239000007789 gas Substances 0.000 description 7
- 230000035515 penetration Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 게이트 절연막의 전기적 특성의 저하 및 두께의 증가를 방지할 수 있는 게이트 전극 및 그 형성방법을 공개한다. 이를 위하여, 본 발명은 게이트 절연막의 상부에 매우 큰 구성입자들을 갖는 실리콘층이 형성되도록 한다. 상기 큰 구성입자들을 갖는 상기 실리콘층은 상기 게이트 절연막쪽으로 침투되는 이물질의 경로를 최소화한다.The present invention discloses a gate electrode and a method for forming the gate electrode capable of preventing a decrease in electrical characteristics and an increase in thickness of the gate insulating film. To this end, the present invention allows a silicon layer having very large constituent particles to be formed on top of the gate insulating film. The silicon layer having the large constituent particles minimizes the path of foreign matter penetrating into the gate insulating film.
Description
제1도는 종래의 트랜지스터의 게이트 전극이 형성된 반도체 장치의 단면도.1 is a cross-sectional view of a semiconductor device in which a gate electrode of a conventional transistor is formed.
제2도는 본 발명의 실시예에 따른 트랜지스터의 게이트 전극이 형성된 반도체 장치의 단면도.2 is a cross-sectional view of a semiconductor device in which a gate electrode of a transistor according to an embodiment of the present invention is formed.
* 도면의 주요주분에 대한 부호의 설명* Explanation of symbols for main parts of drawing
10, 20 : 반도체 기판 12,22 : 게이트 절연막10, 20: semiconductor substrate 12, 22: gate insulating film
14 : 폴리실리콘층 16, 26 : 텅스텐-실리사이드층14 polysilicon layer 16, 26 tungsten-silicide layer
24 : 재결정 폴리실리콘층 28 : 불소 원자24: recrystallized polysilicon layer 28: fluorine atom
본 발명은 반도체 장치에 사용되는 트랜지스터의 게이트 전극 형성방법에 관한 것으로, 특히 게이트 절연막의 두께 증가 및 전기적 특성의 저하를 방지할 수 있는 게이트 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a transistor used in a semiconductor device, and more particularly to a method for forming a gate electrode capable of preventing an increase in thickness of a gate insulating film and a decrease in electrical characteristics.
게이트 전극은 통상적으로 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOSFET라 칭함)의 형성시 먼저 형성되는 것으로, 게이트 절연막이 형성된 반도체 기판의 상부에 위치한다. 그리고 상기 게이트전극은 폴리실리콘층 및 텅스텐-실리사이드층이 적층된 구조로 형성되기도 한다.The gate electrode is first formed during the formation of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET), and is positioned on the semiconductor substrate on which the gate insulating film is formed. The gate electrode may be formed in a structure in which a polysilicon layer and a tungsten-silicide layer are stacked.
그러나, 상기와 같은 종래의 게이트 전극은 상기 폴리실리콘층이 매우 작은 그레인(grain)크기를 갖도록 형성되어 상기 텅스텐-실리사이드층에 포함된 불소(Flourine)원자가 상기 폴리실리콘층의 그레인 경계면을 경유하여 상기 게이트 절연막에 침투된다. 상기 게이트 절연막에 침투된 불소 원자는 트랩영역을 형성하고 아울러 상기 게이트 절연막의 두께를 증가시킨다. 상기 트랩영역은 게이트 전압의 인가시, 게이트 절연막의 전기적 특성(즉, 절연특성)의 저하를 현격하게 야기시킨다.However, such a conventional gate electrode is formed such that the polysilicon layer has a very small grain size so that fluorine atoms contained in the tungsten-silicide layer pass through the grain boundary of the polysilicon layer. Penetrates into the gate insulating film. The fluorine atoms penetrated into the gate insulating film form a trap region and increase the thickness of the gate insulating film. The trap region causes a significant drop in the electrical characteristics (ie, the insulating characteristics) of the gate insulating film when the gate voltage is applied.
상기 종래의 게이트 전극의 문제점을 첨부한 도면을 참조하여 상세하게 살펴보기로 하자.The problem of the conventional gate electrode will be described in detail with reference to the accompanying drawings.
제1도를 참조하면, 반도체 기판(10)의 표면에 게이트 산화막(SiO2)(12)이 형성된 반도체 장치가 설명되어 있다. 상기 게이트 산화막(12)의 상부에는 폴리실리콘층(14) 및 텅스텐-실리사이드층(16) 패턴의 적층 구조로 형성되어 있다.Referring to FIG. 1, a semiconductor device in which a gate oxide film (SiO 2 ) 12 is formed on a surface of a semiconductor substrate 10 is described. The gate oxide layer 12 is formed on the stacked structure of the polysilicon layer 14 and the tungsten-silicide layer 16 pattern.
상기 폴리실리콘층(14)는 통상의 사이렌(SiH4) 가스를 이용한 증착공정에 의하여 그레인 크기가 0.2∼0.3㎛의 크기를 갖도록 형성된다. 그리고 상기 텅스텐-실리사이드층(16)은 상기 폴리실리콘층(14)가 형성된 반도체 기판(10)을 WF6및 SiH4가스가 혼합된 분위기에 노출시켜 상기 폴리실리콘층(14)의 표면에 텅스텐 실리사이드층(16)이 형성된다. 상기 텅스텐-실리사이드층(16)의 형성시, 상기 WR6에 포함된 불소 원자들이 상기 폴리실리콘층(14) 및 텅스텐-실리사이드층(16)의 계면에 축적되고, 상기의 축적된 불소 원자는 보통 10E19㎝-3dltkd의 농도를 갖는다.The polysilicon layer 14 is formed to have a grain size of 0.2 to 0.3 μm by a deposition process using a conventional siren (SiH 4 ) gas. The tungsten silicide layer 16 exposes the semiconductor substrate 10 on which the polysilicon layer 14 is formed to an atmosphere in which WF 6 and SiH 4 gases are mixed, thereby allowing tungsten silicide to be applied to the surface of the polysilicon layer 14. Layer 16 is formed. In the formation of the tungsten-silicide layer 16, the fluorine atoms contained in the WR 6 accumulate at the interface between the polysilicon layer 14 and the tungsten-silicide layer 16, and the accumulated fluorine atoms are usually 10E19 cm -3 dltkd.
상기 텅스텐-실리사이드층(16)과 계면에 포함된 상기 불소 원자들은 대부분, 후속 열처리 공정시, 상기 폴리실리콘층(14)를 경유하여 상기 게이트 산화막(12)에 침투하게 된다. 이는 상기 폴리실리콘층(14)을 구성하는 구성 입자들의 크기가 매우 작음으로 인하여 상기 불소원자들이 침투 경로를 많이 존재하는 것에 기인한다. 그 결과, 상기 게이트 산화막(12)의 두께가 증가되고 아울러 상기 게이트 산화막(12)의 전기적 특성이 현저하게 저하되는 문제점이 있다.Most of the fluorine atoms included in the interface with the tungsten-silicide layer 16 penetrate the gate oxide layer 12 through the polysilicon layer 14 during a subsequent heat treatment process. This is due to the fact that the fluorine atoms have many penetration paths due to the very small size of the constituent particles constituting the polysilicon layer 14. As a result, there is a problem in that the thickness of the gate oxide film 12 is increased and the electrical characteristics of the gate oxide film 12 are significantly reduced.
따라서, 본 발명의 목적은 게이트 절연막의 전기적 특성의 저하 및 두께의 증가를 방지할 수 있는 게이트 전극 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of forming a gate electrode which can prevent a decrease in electrical characteristics and an increase in thickness of a gate insulating film.
상기 목적을 달성하기 위하여, 본 발명의 게이트 전극은 게이트 절연막의 상부에 매우 큰 그레인 크기를 갖는 실리콘층이 형성되도록 한다. 상기 큰 그레인 크기를 실리콘층은 상기 게이트 절연막쪽으로 침투되는 이물질의 경로를 최소화한다.In order to achieve the above object, the gate electrode of the present invention is to form a silicon layer having a very large grain size on top of the gate insulating film. The large grain size silicon layer minimizes the path of foreign matter penetrating into the gate insulating layer.
이하, 본 발명의 실시예를 첨부한 제2도를 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying Figure 2 of the embodiment of the present invention will be described in detail.
제2도를 참조하면, 반도체 기판(20)의 상부에 게이트 절연막(22)이 형성된 반도체 장치가 설명되어 있다. 상기 게이트 절연막(22)의 상부에 비정질실리콘층(도시되지 않음) 및 미량의 불소 원자가 포함된 텅스텐-실리사이드층(26)을 순차적으로 적층한다. 여기서 상기 비정질 실리콘층은 후속 열공정에서 재결정화되어 재결정폴리실리콘층(24)으로 상전이 되고, 이때 그레인 크기는 대약 2∼3㎛의 크기로 종래 방법에 비해 약 10배 정도의 그레인 크기를 갖는다. 이로 인하여, 상기 잭려정폴리 실리콘층(24)은 종래의 게이트 전극에 사용되는 폴리실리콘층에 비하여 상기 게이트 절연막(22)쪽으로의 이물질의 침투경로들을 적어도 1/10 정도로 감소시킬 수 있다. 따라서 상기 텅스텐-실리사이드층(26)에 포함된 불소 원자들은 상기 재결정폴리실리콘층(24)의 그레인들에 의하여 상기 게이트 절연막(22)쪽으로의 침투경로가 제한됨으로 인하여 대부분 침투되지 못하게 된다. 그 결과, 상기 게이트 절연막(22)의 두께는 증가되지 않게 되고, 아울러 상기 게이트 절연막(22)의 전기적 특성도 크게 저하되지 않는다.Referring to FIG. 2, a semiconductor device in which the gate insulating layer 22 is formed on the semiconductor substrate 20 is described. An amorphous silicon layer (not shown) and a tungsten-silicide layer 26 containing a small amount of fluorine atoms are sequentially stacked on the gate insulating layer 22. In this case, the amorphous silicon layer is recrystallized in a subsequent thermal process to phase change into the recrystallized polysilicon layer 24, wherein the grain size is about 2 to 3 µm and has a grain size of about 10 times that of the conventional method. As a result, the jack rubbing polysilicon layer 24 may reduce the penetration paths of the foreign matter toward the gate insulating layer 22 by at least 1/10 of the polysilicon layer used in the conventional gate electrode. Therefore, the fluorine atoms included in the tungsten-silicide layer 26 are mostly prevented from penetrating due to the limited penetration path toward the gate insulating layer 22 by the grains of the recrystallized polysilicon layer 24. As a result, the thickness of the gate insulating film 22 does not increase, and also the electrical characteristics of the gate insulating film 22 do not significantly decrease.
상기 게이트 절연막(22)은 상기 반도체 기판(20)을 O2가스에 노출시켜 산화막(SiO2)이 상기 반도체 기판(2)의 표면으로 부터 성장되도록 함에 의하여 형성된다.The gate insulating layer 22 is formed by exposing the semiconductor substrate 20 to O 2 gas so that an oxide film SiO 2 is grown from the surface of the semiconductor substrate 2.
그리고 상기 비정질 실리콘층는 450 내지 580℃의 온도에서 상기 게이트 절연막(22)이 형성된 상기 반도체 기판(20)을 소정 압력의 디실렌(Si2H6) 가스에 노출시킴에 의하여 형성된다. 상기 디실렌 가스 반응시 압력은 대략 0.1 내지 수십 Torr정도로 설정된다.In addition, the amorphous silicon layer is formed by exposing the semiconductor substrate 20 on which the gate insulating layer 22 is formed at a predetermined pressure to disylene (Si 2 H 6 ) gas at a temperature of 450 to 580 ° C. The pressure in the disylene gas reaction is set to about 0.1 to several tens Torr.
이후 후속 열처리 공정에서 상기 비정질실리콘층은 재결정화되어 2∼3㎛의 그레인 크기를 갖는 재결정 폴리실리콘층(24)으로 상전이 된다.Thereafter, in the subsequent heat treatment process, the amorphous silicon layer is recrystallized to phase change into a recrystallized polysilicon layer 24 having a grain size of 2 to 3 μm.
마지막으로, 상기 텅스텐-실리사이드층(26)은 상기 비정질 실리콘층이 형성된 반도체 기판(20)을 WF6및 SiH4가스가 혼합된 분위기에 노출시켜 상기 비정질 실리콘층의 표면층에 형성된다. 상기 텅스텐-실리사이드층(26)의 형성시, 상기 WF6가스에 포함된 불소 원자들(28)이 상기 비정질 실리콘층 및 텅스텐-실리사이드층(26)의 계면에 축적된다. 이 결과, 상기 텅스텐-실리사이드층(26)에는 약간의 불소 원자가 존재하게 된다.Finally, the tungsten-silicide layer 26 is formed on the surface layer of the amorphous silicon layer by exposing the semiconductor substrate 20 on which the amorphous silicon layer is formed to an atmosphere in which WF 6 and SiH 4 gas are mixed. In the formation of the tungsten-silicide layer 26, fluorine atoms 28 included in the WF 6 gas are accumulated at the interface between the amorphous silicon layer and the tungsten-silicide layer 26. As a result, some fluorine atoms are present in the tungsten-silicide layer 26.
상기 계면과 텅스텐-실리사이드층(26)에 포함된 상기 불소 원자들(28)은, 후속 열처리시, 상기 비정질 실리콘층이나 재결정 폴리실리콘층(24)을 경유하여 상기 게이트 절연막(22)쪽으로 침투되지 못한다. 이는 상기 비정질 실리콘층의 경우 그레인 경계가 없기 때문이고, 재결정 폴리실리콘층(24)은 그레인이 매우 크게 형성되므로 상기 게이트 절연막(220쪽으로의 침투 경로들이 감소된 것에 기인한다.The fluorine atoms 28 included in the interface and the tungsten-silicide layer 26 do not penetrate into the gate insulating film 22 through the amorphous silicon layer or the recrystallized polysilicon layer 24 during subsequent heat treatment. can not do it. This is because there is no grain boundary in the amorphous silicon layer, and the recrystallized polysilicon layer 24 has very large grains, and thus, penetration paths toward the gate insulating layer 220 are reduced.
그 결과, 상기 게이트 절연막(22)의 두께의 증가가 최소화되고 아울러 상기 게이트 절연막(22)의 전기적 특성의 저하가 최소화된다. 상기 게이트 절연막(22)의 증가는 5 내지 10 A이하로 억제되어 종래의 게이트 전극에 비하여 200% 정도 개선된다. 그리고 상기 게이트 절연막(22)의 전기적의 특성도, 일정한 전류를 인가한 시험 결과에 따르면, 종래의 게이트 전극의 경우에 비하여 200% 정도 향상될 수 있었다.As a result, an increase in the thickness of the gate insulating film 22 is minimized, and a decrease in electrical characteristics of the gate insulating film 22 is minimized. The increase in the gate insulating film 22 is suppressed to 5 to 10 A or less, which is about 200% improvement over the conventional gate electrode. In addition, according to a test result of applying a constant current, the electrical characteristics of the gate insulating film 22 can be improved by about 200% compared to the case of the conventional gate electrode.
상술한 바와 같이, 본 발명은 게이트 절연막 및 텅스텐-실리사이드층의 사이에 위치하는 실리콘층이 큰 크기의 그레인들에 의하여 구성되도록 하여 상기 텅스텐-실리사이드층에 포함된 불소 원자가 상기 게이트 절연막쪽으로 침투되는 것을 최소화한다. 이로 인하여, 본 발명은 상기 게이트 절연막의 두께의 증가를 최소화할 수 있고, 또한 상기 게이트 절연막의 전기적 특성의 저하를 최소화 할 수 있는 장점을 제공한다. 더 나아가, 본 발명은 제작자로 하여금 게이트 전극의 형성시의 박막의 제어를 용이하게 할 수 있도록 하는 장점도 제공한다.As described above, the present invention allows the silicon layer located between the gate insulating film and the tungsten-silicide layer to be composed of grains of large size so that fluorine atoms contained in the tungsten-silicide layer penetrate toward the gate insulating film. Minimize. Thus, the present invention can minimize the increase in the thickness of the gate insulating film, and also provides an advantage that can minimize the degradation of the electrical characteristics of the gate insulating film. Furthermore, the present invention also provides an advantage that enables the manufacturer to easily control the thin film in forming the gate electrode.
Claims (2)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050441A KR100203896B1 (en) | 1995-12-15 | 1995-12-15 | Manufacturing method of the gate electrode |
| DE19652070A DE19652070C2 (en) | 1995-12-15 | 1996-12-13 | Gate electrode and method of making the same |
| CNB961214740A CN1172378C (en) | 1995-12-15 | 1996-12-15 | Gate electrode and forming method thereof |
| JP8352537A JPH1032334A (en) | 1995-12-15 | 1996-12-16 | Gate electrode and its forming method |
| GB9626113A GB2308233B (en) | 1995-12-15 | 1996-12-16 | Gate electrode and method for the formation thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050441A KR100203896B1 (en) | 1995-12-15 | 1995-12-15 | Manufacturing method of the gate electrode |
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| Publication Number | Publication Date |
|---|---|
| KR970053905A KR970053905A (en) | 1997-07-31 |
| KR100203896B1 true KR100203896B1 (en) | 1999-06-15 |
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| KR1019950050441A KR100203896B1 (en) | 1995-12-15 | 1995-12-15 | Manufacturing method of the gate electrode |
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| JP (1) | JPH1032334A (en) |
| KR (1) | KR100203896B1 (en) |
| CN (1) | CN1172378C (en) |
| DE (1) | DE19652070C2 (en) |
| GB (1) | GB2308233B (en) |
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| GB9802940D0 (en) * | 1998-02-11 | 1998-04-08 | Cbl Ceramics Ltd | Gas sensor |
| KR100710645B1 (en) * | 2001-05-18 | 2007-04-24 | 매그나칩 반도체 유한회사 | Method for forming the metal line in semiconductor device |
| CN101572228B (en) * | 2008-04-28 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Methods for forming polysilicon thin film and gate |
| SG11202100359SA (en) * | 2018-08-11 | 2021-02-25 | Applied Materials Inc | Graphene diffusion barrier |
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| EP0459770B1 (en) * | 1990-05-31 | 1995-05-03 | Canon Kabushiki Kaisha | Method for producing a semiconductor device with gate structure |
| JP2901423B2 (en) * | 1992-08-04 | 1999-06-07 | 三菱電機株式会社 | Method for manufacturing field effect transistor |
| US5364803A (en) * | 1993-06-24 | 1994-11-15 | United Microelectronics Corporation | Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure |
| JP2560993B2 (en) * | 1993-09-07 | 1996-12-04 | 日本電気株式会社 | Method for manufacturing compound semiconductor device |
| US5441904A (en) * | 1993-11-16 | 1995-08-15 | Hyundai Electronics Industries, Co., Ltd. | Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries |
-
1995
- 1995-12-15 KR KR1019950050441A patent/KR100203896B1/en not_active IP Right Cessation
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1996
- 1996-12-13 DE DE19652070A patent/DE19652070C2/en not_active Expired - Fee Related
- 1996-12-15 CN CNB961214740A patent/CN1172378C/en not_active Expired - Fee Related
- 1996-12-16 GB GB9626113A patent/GB2308233B/en not_active Expired - Fee Related
- 1996-12-16 JP JP8352537A patent/JPH1032334A/en active Pending
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| Publication number | Publication date |
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| CN1172378C (en) | 2004-10-20 |
| CN1155159A (en) | 1997-07-23 |
| JPH1032334A (en) | 1998-02-03 |
| GB2308233A (en) | 1997-06-18 |
| KR970053905A (en) | 1997-07-31 |
| DE19652070C2 (en) | 2003-02-20 |
| DE19652070A1 (en) | 1997-06-19 |
| GB9626113D0 (en) | 1997-02-05 |
| GB2308233B (en) | 2000-11-15 |
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