CN1172378C - Gate electrode and forming method thereof - Google Patents
Gate electrode and forming method thereof Download PDFInfo
- Publication number
- CN1172378C CN1172378C CNB961214740A CN96121474A CN1172378C CN 1172378 C CN1172378 C CN 1172378C CN B961214740 A CNB961214740 A CN B961214740A CN 96121474 A CN96121474 A CN 96121474A CN 1172378 C CN1172378 C CN 1172378C
- Authority
- CN
- China
- Prior art keywords
- amorphous silicon
- silicon layer
- gate electrode
- tungsten silicide
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 125000001153 fluoro group Chemical group F* 0.000 claims description 13
- 229910052731 fluorine Inorganic materials 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 10
- 238000001764 infiltration Methods 0.000 claims description 10
- 230000008595 infiltration Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 23
- 229920005591 polysilicon Polymers 0.000 description 23
- 235000019580 granularity Nutrition 0.000 description 7
- 238000005755 formation reaction Methods 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A gate electrode which has a structure in which a tungsten silicide layer is formed on an amorphous silicon layer is disclosed. A gate insulation film is formed on a semiconductor substrate, an amorphous silicon layer is formed on the gate insulation film by using disilane gas, and a tungsten silicide layer is formed on the amorphous silicon layer containing trace amounts of foreign matter. The grain size of the amorphous silicon layer is such that the foreign matter cannot enter the gate insulation film.
Description
Technical field
The present invention relates to the used transistor gate of semiconductor device, especially relate to gate electrode in the folded tungsten silicide structure of upper amorphous silicon layer.
Background technology
Usually, the gate electrode of MOS transistor is prior to source electrode and drain electrode, at first forms to form on the Semiconductor substrate of gate insulating film.Described gate electrode is formed by polysilicon, for improving its performance, perhaps replaces with amorphous polysilicon, perhaps stacked tungsten silicide layer on polysilicon.
Fig. 2 is existing embodiment, is the partial sectional view with semiconductor element of the structure of stacked tungsten silicide on polysilicon layer.
Referring to Fig. 2, existing grid structure is to form gate oxidation films (SiO on the surface of Semiconductor substrate 10
2) 12, stack gradually polysilicon layer 14 and tungsten silicide layer 16 on gate oxidation films top.
Polysilicon is to have a crystalline material, by the little crystal region formations of being separated by crystal boundary etc. such as (granularities).During deposit, can obtain to have amorphism and crystalline polysilicon film etc.; After the deposit,, represent crystal structure by high-temperature process.
Mainly be to form polysilicon layer 14 by chemical vapor deposition (CVD) method.At this moment, for polysilicon, adopt silane (SiH
4) gas is as source gas.As the application result of chemical vapor deposition method, the granularity of the polysilicon of formation is 0.2～0.3 μ m size.
Tungsten silicide layer 16 can form selectively by chemical vapor deposition method or physical deposition method.When adopting chemical vapor deposition method, have the object layer of the polysilicon layer 14 that is used to form tungsten silicide on the Semiconductor substrate 10, and containing WF
6In the atmosphere of gas.At this moment, described WF
6The contained small amount of fluorine atom of gas infiltrates the superficial layer of described polysilicon layer 14.As a result, in silicon tungsten layer 16, there is a spot of fluorine atom.
Contained described fluorine atom in the described tungsten silicide layer 16, most of via described polysilicon layer 14 in the subsequent heat treatment operation, infiltrate described gate oxidation films 12.This is because the size of the structure granularity of the described polysilicon layer 14 of formation is very little, has the permeation pathway of a lot of described fluorine atoms.Its result, the thickness of described gate oxidation films 12 increases, and the electrical characteristics of described gate oxidation films 12 significantly become bad.
On the other hand, when on amorphous silicon, forming tungsten silicide, want big during the amorphous silicon fineness ratio polysilicon of formation, but because the little degree of size of these granularities, so the problem of fluorine atom infiltration still takes place when forming tungsten silicide to 0.5 μ m.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of gate electrode that forms by the stromatolithic structure of polysilicon and tungsten silicide, can prevent to cause gate electrode that the electrical characteristics of gate oxidation films become bad and thickness increases and forming method thereof because of the infiltration of fluorine atom.
For achieving the above object, the invention provides a kind of gate electrode, has the gate insulating film that forms on Semiconductor substrate top, the amorphous silicon layer that is formed by b silane gas on described gate insulating film top and at described amorphous silicon layer top tungsten silicide layer that form, that contain trace impurity, its feature are that described amorphous silicon layer has and can prevent the size of described impurity to the infiltration of gate insulating film side.
According to the present invention, gate electrode has amorphous polysilicon layer that form, that contain very big structure particles on gate oxidation films top.The described amorphous polysilicon layer that contains the macrostructure particle can make impurity diminish to the path of described gate oxidation films side infiltration.
Specifically, one aspect of the present invention provides a kind of gate electrode to comprise: the gate oxidation films that forms on Semiconductor substrate; The amorphous silicon layer that on described gate oxidation films, forms by chemical vapour deposition (CVD) by b silane gas; Tungsten silicide layer that form, that contain trace impurity on described amorphous silicon layer, wherein said amorphous silicon layer has the size of 2～3 μ m, thereby, in follow-up Technology for Heating Processing, reduce of the infiltration of described impurity to gate oxidation films.
Preferably, described impurity is fluorine element.
The present invention provides a kind of formation method of gate electrode on the other hand, comprises following operation: the Semiconductor substrate that is formed with gate oxidation films thereon is provided; Semiconductor substrate is placed in the used reative cell of chemical vapour deposition (CVD), has disilane atmosphere in the reative cell, Semiconductor substrate is heat-treated, so that on described gate oxidation films, form amorphous silicon layer, the pressure of described reative cell is 0.1～dozens of Torr, and the temperature of described reative cell is 450～580 ℃; On described amorphous silicon layer, form tungsten silicide.
Preferably, described tungsten silicide is WSi
2
Brief description of drawings
Fig. 1 is the embodiment that the present invention relates to, and is the gate electrode cutaway view with stacked tungsten silicide structure on polysilicon layer.
Fig. 2 is existing embodiment, is the gate electrode cutaway view with stacked tungsten silicide structure on polysilicon layer.
Embodiment
Below, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
With reference to Fig. 1, form gate insulating film 22 on the top of Semiconductor substrate 20, on the top of described gate insulating film 22, the stacked tungsten silicide layer 26 that contains the amorphous silicon layer 24 of big structure particles and contain the fluorine atom of trace.
With disilane (Si
2H
6) be source gas, by chemical vapor deposition method, form described amorphous silicon layer 24, its structure granularity size is about 2～3 μ m, compares with the existing structure that silicon metal is stacked, and its granularity is greatly to 10 times degree.Therefore, described amorphous silicon layer 24 is compared with the employed polysilicon layer of existing gate electrode, and impurity can reduce to 1/10 degree at least to the infiltration path of described gate insulating film 22 sides.As a result, the thickness of described gate insulating film 22 need not to increase, and the electrical characteristics of described gate insulating film 22 can not take place to descend significantly yet.The tungsten silicide that the present invention is suitable for is with WSi
2For good.
Below, the forming process of the gate electrode of described structure is described.
At O
2Expose described Semiconductor substrate 20 in the gas, at described Semiconductor substrate 20 superficial growth oxide (SiO
2), form described gate insulating film 24 thus.
Thus, with 450～580 ℃ temperature, make the described Semiconductor substrate 20 that is formed with described gate insulating film 22 be exposed to the disilane (Si of predetermined pressure
2H
6) gas, formation contains the described amorphous silicon layer 24 of the structure particles of 2～3 μ m sizes thus.Pressure when described b silane gas reacts generally is set at the degree of 0.1～dozens of Torr.
At last, make the Semiconductor substrate 20 that is formed with amorphous silicon layer 24 be exposed to WF
6Gas, described WF
6Contained tungsten atom of gas and 14 reactions of described polysilicon layer form described tungsten silicide layer 26 thus.When described tungsten silicide layer 26 forms, described WF
6The contained small amount of fluorine atom 28 of gas infiltrates the superficial layer of described amorphous silicon layer 24.As a result, there is a spot of fluorine atom in the described tungsten silicide layer 26.
Contained described fluorine atom 28 in the described tungsten silicide layer 26 when subsequent heat treatment, obviously reduces via the amount of described amorphous silicon layer 24 to described gate insulating film 22 sides infiltration.This is because the structure particles that constitutes described amorphous silicon layer 24 is very big, the cause that reduces to the infiltration path of described gate insulating film 22 sides.
As a result, the increase of the thickness of described gate insulating film 22 is minimized, and make the reduced minimum of the electrical characteristics of described gate insulating film 22.The increase of described gate insulating film 22 is suppressed in below 5～10 , compares with existing gate electrode, can improve 200% the degree that reaches.And, according to the result of the test that applies certain electric current, to compare with existing gate electrode, the electrical characteristics of described gate insulating film 22 also can improve 200% degree.
As mentioned above, the present invention is for stacking gradually silicon metal and tungsten silicide layer on gate oxidation films, form the gate electrode of polygon structure, by using b silane gas, the polysilicon that replaces described crystalline with amorphous silicon, constitute big as far as possible structure granularity size, the contained fluorine atom of described tungsten silicide layer is minimized to the infiltration of described gate insulating film side.In view of the above, advantage of the present invention is that the increase of described thick gate insulating film is minimized, and also can make the electrical characteristics reduced minimum of described gate insulating film.
Here, although in conjunction with the accompanying drawings specific embodiment of the present invention is illustrated, those skilled in the art can make this and revising and distortion.Therefore, the scope of following claims is interpreted as comprising whole variations and the reproduction that belongs to spirit of the present invention and scope.
Claims (4)
1, a kind of gate electrode comprises:
The gate oxidation films that on Semiconductor substrate, forms;
The amorphous silicon layer that on described gate oxidation films, forms by chemical vapour deposition (CVD) by b silane gas;
Tungsten silicide layer that form, that contain trace impurity on described amorphous silicon layer, wherein said amorphous silicon layer has the size of 2～3 μ m, thereby, in follow-up Technology for Heating Processing, reduce of the infiltration of described impurity to gate oxidation films.
2, gate electrode according to claim 1, wherein, described impurity is fluorine element.
3, a kind of formation method of gate electrode comprises following operation:
The Semiconductor substrate that is formed with gate oxidation films thereon is provided;
Semiconductor substrate is placed in the used reative cell of chemical vapour deposition (CVD), has disilane atmosphere in the reative cell, Semiconductor substrate is heat-treated, so that on described gate oxidation films, form amorphous silicon layer, the pressure of described reative cell is 0.1～dozens of Torr, and the temperature of described reative cell is 450～580 ℃;
On described amorphous silicon layer, form tungsten silicide.
4, gate electrode formation method according to claim 3, wherein, described tungsten silicide is WSi
2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR50441/1995 | 1995-12-15 | ||
| KR1019950050441A KR100203896B1 (en) | 1995-12-15 | 1995-12-15 | Manufacturing method of the gate electrode |
| KR50441/95 | 1995-12-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1155159A CN1155159A (en) | 1997-07-23 |
| CN1172378C true CN1172378C (en) | 2004-10-20 |
Family
ID=19440439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB961214740A Expired - Fee Related CN1172378C (en) | 1995-12-15 | 1996-12-15 | Gate electrode and forming method thereof |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH1032334A (en) |
| KR (1) | KR100203896B1 (en) |
| CN (1) | CN1172378C (en) |
| DE (1) | DE19652070C2 (en) |
| GB (1) | GB2308233B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9802940D0 (en) * | 1998-02-11 | 1998-04-08 | Cbl Ceramics Ltd | Gas sensor |
| KR100710645B1 (en) * | 2001-05-18 | 2007-04-24 | 매그나칩 반도체 유한회사 | Method for forming the metal line in semiconductor device |
| CN101572228B (en) * | 2008-04-28 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Methods for forming polysilicon thin film and gate |
| WO2020036819A1 (en) * | 2018-08-11 | 2020-02-20 | Applied Materials, Inc. | Graphene diffusion barrier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0459770B1 (en) * | 1990-05-31 | 1995-05-03 | Canon Kabushiki Kaisha | Method for producing a semiconductor device with gate structure |
| JP2901423B2 (en) * | 1992-08-04 | 1999-06-07 | 三菱電機株式会社 | Method for manufacturing field effect transistor |
| US5364803A (en) * | 1993-06-24 | 1994-11-15 | United Microelectronics Corporation | Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure |
| JP2560993B2 (en) * | 1993-09-07 | 1996-12-04 | 日本電気株式会社 | Method for manufacturing compound semiconductor device |
| DE4440857C2 (en) * | 1993-11-16 | 2002-10-24 | Hyundai Electronics Ind | Method of manufacturing a gate electrode of a semiconductor device |
-
1995
- 1995-12-15 KR KR1019950050441A patent/KR100203896B1/en not_active IP Right Cessation
-
1996
- 1996-12-13 DE DE19652070A patent/DE19652070C2/en not_active Expired - Fee Related
- 1996-12-15 CN CNB961214740A patent/CN1172378C/en not_active Expired - Fee Related
- 1996-12-16 GB GB9626113A patent/GB2308233B/en not_active Expired - Fee Related
- 1996-12-16 JP JP8352537A patent/JPH1032334A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB2308233A (en) | 1997-06-18 |
| JPH1032334A (en) | 1998-02-03 |
| DE19652070A1 (en) | 1997-06-19 |
| CN1155159A (en) | 1997-07-23 |
| GB9626113D0 (en) | 1997-02-05 |
| DE19652070C2 (en) | 2003-02-20 |
| KR970053905A (en) | 1997-07-31 |
| KR100203896B1 (en) | 1999-06-15 |
| GB2308233B (en) | 2000-11-15 |
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| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20041020 Termination date: 20100115 |