JPH0683696A - Two-dimensional array type memory system - Google Patents

Abstract

PURPOSE:To provide a two-dimensional array type memory system at low cost for which the numbers of instructions and overheads for memory management are less and high-speed access is enabled. CONSTITUTION:Memory arrays 1001 and 1002 are used as storage parts and addresses in the directions of the rows and columns of the respective arrays are managed by a pair of two pointers. The respective pointers are generated by respective controllers 1009 and 1010 and the respective controllers receive the leading addresses of the arrays and pointer update information from a CPU and mutually generate access pointers to arrayed data independently from the CPU corresponding to the information to be outputted. Thus, the memory system for handling the arrayed data can be accelerated and economized and CPU overheads can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional array type memory system suitable for a processing device that handles large-scale data in real time.

[0002]

2. Description of the Related Art The capacity of memory systems used in computer systems has been increasing rapidly in recent years. At present, it is becoming an indispensable condition for architecture construction to have a large-capacity memory system which has a main memory of 8 Mbytes to 128 Mbytes at the workstation level and is linearly accessible. That is, the OS, its work area, a general-purpose file system, and a table consume a large amount of memory, and effective processing cannot be performed unless a linear memory system having a sufficient capacity is provided. As an example of a memory interface configuration based on the conventional linear memory space, reference document number 231732J-0 of Intel Corporation is used.
03 (8036 Hardware Reference Manual), P43 to P62.

[0003]

It is true that the memory system architecture of the current computer system is highly versatile, but conversely, access operations and their management (memory management) are performed.
CPU load and OS load are very high, resulting in a large over head. Also, because it is assumed that you have a large capacity memory system,
There is no choice but to increase the cost. The problem is described in detail below. (1) requires a relatively large linear memory system,
All the operations are based on the idea of relying on the addressing process of the CPU and the access command to configure the processing unit.
Therefore, it is necessary to describe the management and access operations of the memory space in the OS or software, which is versatile, but it is not possible
The head is large. (2) Since the number of instructions required to access the memory increases with the above (1), a large amount of memory is required to hold those instruction codes. An average of 10 to 12 bytes (32 bit processor) is required as an instruction code for a series of operations for reading and writing 1 data (Read and Write). That much code memory is consumed, and the cost per memory access is large. (3) When designing a cost-oriented industrial computer from the above (1) and (2), the cost occupied by the memory tends to become too large. (4) Command code sequence, array data sequence (file system, numerical processing data, table, model data, etc.)
The system is designed on the assumption that all areas are randomly accessed, although data that can be processed in a vector occupy most of the memory system. Therefore, the access operation becomes redundant and the addressing process requires more overhead than necessary. (5) For the computer system, the maximum critical path in memory access is how fast the specified memory data (operand data) can be taken into the CPU and the processing can be added to the data. Is.
If the necessary data is not input to the CPU, the CPU will be in a waiting state, which directly causes a decrease in processing efficiency.
In a conventional system, operand data addressing is performed in the access instruction being executed in the CPU. Then, the result is output to the memory, and after waiting until the access target data is read from the memory, the data is fetched and necessary processing is added. Therefore, an access waiting overhead is always required.

Considering the above problems of the prior art,
It is very difficult to cover various performance requirements from cost-oriented computer systems to large-scale high-performance systems, and to design in the future under a unified architecture. , And the cost performance is taken into consideration, the problem becomes more serious. From this point, a closer look at the problem is as follows; (6) When trying to support a large address space,
Many address lines, multi-bit addressing processing devices (counters and adders), and address registers must be provided in the CPU, which inevitably requires an expensive CPU (32bitC
An address space that can be handled by an 8-bit CPU such as PU is small). (7) In order to reduce the hardware cost, an inexpensive CPU (8bit CPU, 16bit CPU, etc.) will be used, but the addressing processing capacity will also decrease at the same time,
Not only the memory capacity that can be handled decreases, but also the processing capacity itself has to be low. (8) Even if a completely cost-oriented design is required at the present time, if higher performance requirements are required in terms of memory capacity and numerical processing capability in the future, the architecture and software property of Considering this, we have no choice but to design to some extent from the present time. (9) Considering the property and inheritance of software,
It becomes necessary to write a program using a high-level language. Therefore, not only the execution speed of the program is lowered, but also a large memory capacity is required, so that the cost performance becomes very bad. If the performance is to be improved under this condition, it is necessary to change the CPU to a higher level one, and the hardware cost is absolutely increased. (10) Even if the memory system has a small capacity, if high numerical processing capability is required, most of the performance depends on the access efficiency to the memory system. Therefore, it becomes necessary to enhance the addressing ability of the memory system by using a high-level CPU, and accordingly, the memory system also has to be relatively large-scaled. (11) A program built on a high-performance machine and a large-capacity memory system has a very high dependency on the OS and system software, and tends to have a large code size and data size. In other words, because it is manufactured without concern for machine performance and memory capacity, cost performance is improved.
Very poor monthly performance. Therefore, if you try to port it to a cost-oriented machine, it will require a great deal of tuning (almost like rebuilding), or if you consider the asset property, you will eventually need a high-end machine, which will greatly increase your target cost. It is likely to be far from one another.

An object of the present invention is to provide an OS for memory management.
A two-dimensional array memory system that has less overhead of software and software, reduces the total memory capacity by reducing the number of instructions for graduation management, and therefore costs, and can speed up large-capacity memory access. To provide.

[0006]

The above objects are achieved by the following. 1) A memory array configured to perform addressing with a set of a page pointer and a column pointer, a page address controller that generates the page pointer in response to an access from a central processing unit, and an access from the central processing unit And a column address controller for generating the column pointer according to the above. 2) The column address controller comprises a column address register file composed of a plurality of column address registers, an offset address for a column separately given, and an address set by the central processing unit in the column address register. The page address controller comprises a column address counter for generating a pointer, and the page address controller includes a page address register file including a plurality of page address registers, an offset address for a page separately given, and the page address register from the central processing unit. It comprises a page address counter for generating the page pointer from the set address. 3) The column address controller matches the timing of the two pointers from the latch for temporarily storing the column pointer generated by the column address counter and the page pointer generated by the page address counter. Control means for outputting to the memory array. 4) The column address register file includes a plurality of column address register sets including a plurality of column address registers, and an offset register corresponding to each column address register set,
A selection circuit for selecting the column address register set and the offset register and the column address register in the selected column address register set is provided, and the column address register selected by the circuit and the corresponding offset register are provided. The column address counter generates a column pointer from the contents. 5) The page address register file includes a plurality of page address register sets including a plurality of the page address registers, and an offset register corresponding to each page address register set,
A selection circuit for selecting the page address register set and the offset register and the page address register in the selected page address register set is provided, and the page address register selected by the circuit and the corresponding offset register The page address counter generates a page pointer from the contents. 6) A mode register is provided for each offset register, and the contents of the offset register are updated according to the mode set in the mode register by access from the central processing unit. 7) A selector for selecting the output of the offset register and the direct address data from the central processing unit is provided, and the selector allows selection by the output of the mode register. 9) The page address controller is provided with a temporary register for the first page address that can transfer data to and from the page address register. 10) The column address controller is provided with a second temporary register and a multiplexer that can be directly addressed by the central processing unit, and the address read from the column address register file and the second temporary register are set by the multiplexer. Address and are selected and output. 11) The page address controller is provided with a second temporary register and a multiplexer that can be directly addressed by the central processing unit, and the address read from the page address register file and the second temporary register are set by the multiplexer. Address and are selected and output.

[0007]

When the upper central processing unit makes a memory access for array data processing, management information on how the page pointer and column pointer should be updated and the value of the head pointer of the array data are stored. , The page address controller and the column address controller are set in the mode register, the page address register, and the column address register. Here, as the management information when accessing the memory array, whether or not the pointer should be updated to the next value as the addressing processing, the value to be updated is the current pointer plus the offset, or the increment or decrement. It is information such as whether the address has been set. By doing so, the address processing in the page address controller and the column address controller can be independently executed in parallel, and these processing and the data transfer between the memory array and the central processing unit can also be executed in parallel. Therefore, a large linear memory system is not required for processing array data composed of a large amount of data, and memory access processing can be performed without depending on the central processing unit. It is not necessary to write it in or software, and the overhead of the central processing unit can be greatly reduced. At the same time, less memory is needed to hold the instruction code, as the number of instructions required to access the memory is reduced. Therefore, if it is applied to an industrial computer or the like, the cost occupied by the memory can be greatly reduced. In addition, since it has a function that allows the physical address itself from the central processing unit to be transmitted and output, it is possible to easily process data that does not have a high degree of regularity, such as array data, and that requires random access, making it a general-purpose system. Can retain sex.

[0008]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 1 is a block diagram showing an embodiment of a two-dimensional array memory system of the present invention.
Two access control units 100 for 1013
3, 1004 and two memory arrays 100 controlled by these
1, 1002 are provided. In this embodiment, the memory array 1
One of 001 and 1002 is used as a memory system for instruction code data (CDRAM), and the other is used as a memory system for operand data (DDRAM) (which may be used for any purpose). As shown in Japanese Patent Application No. 63-7145 and Japanese Patent Application No. 1-71723, each memory array is managed by a paging interleave access method using a dynamic memory device. Each access control unit has a page address controller (PACL,
It consists of two access control units, a PA controller (hereinafter referred to as PA controller) 1009 and a column address controller (CACTL, hereinafter referred to as CA controller) 1010. Control the address of.
This address is a set of a page pointer that gives a page address (address in the row direction) and a column pointer that gives a column address (address in the column direction) corresponding to the two-dimensional array of each memory array.

FIG. 2 shows a structure for one memory array. It consists of banks 0 to n, and each bank has 2048 column pointers and 4096 page pointers for a total of 2048 x 40 when 32 bits of data is 1 data.
It is a two-dimensional array memory having 96 addresses. This is a capacity of 32 Mbytes. In this memory array,
Vector data is stored as a set of adjacent data in the direction of the column pointer or page pointer, such as X0VEC0, Yj + 2VEC0 in the figure, and the matrix data is X1MA in the figure.
It is stored in a rectangular area in both directions of the column pointer and page pointer, such as T0. In this way, the vector (XmVECn) and matrix (XmMATn) are defined on the memory data matrix. And these vectors, page pointer m indicating the beginning of the matrix,
The attribute (corresponding to the array name) of those multidimensional variables is expressed by a set (m, n) of column pointers n. Here, the vector in the horizontal direction that is the pointer of the head data is X
The vector in the vertical direction is represented by YmVECn, and the matrix is represented by XmMATn.

The operation of the access control unit 10
Next, 03 will be described as an example. In FIG. 1, the main CPU
The section 1013 supplies the loop management information to the PA controller 1009 and the CA controller 1010 in the access control section in advance when the array data is processed, for example, when the vector operation processing loop is executed. That is, when the main CPU unit accesses the memory array,
Information on how the pointers m and n should be updated and the value of the first pointer of the array data are stored in the data bus (DATA) 1014 or the address bus (ADDR) 1015.
PA controller 1009 and CA controller 10 via
Set within 10. Also, as the addressing process when accessing the memory array, whether or not the pointer should be updated to the next value, whether the value to be updated is the current pointer plus the offset, or the incremented or decremented data, It is possible to preprogram information such as, for example, to execute it as default addressing, or to directly instruct the main CPU unit 1013 at the time of data access using an access instruction to execute addressing processing in parallel with the access operation. I can. These addressing processes are performed by a page address counter (PACNT, hereinafter referred to as PA counter) 1016 in the PA controller 1009 and a column address counter (CACNT, hereinafter referred to as CA counter) 1016 in the CA controller 1010.
By 18, the pointers m and n are processed independently and in parallel. With this, the two pointers are automatically controlled, and the complicated addressing processing conventionally executed in the CPU is executed in parallel with the access operation of the CPU, thereby improving the access efficiency.

The page address data (OPA) 1017 generated by the PA controller 1009 is once used as the upper address of the memory array system 1001 by the CA controller 1010.
After being sent to the address register (AL) 1019 together with the column address data (OCA) 1025 corresponding to the lower address generated here, the entire address data is generated. Although it is possible to directly provide the page address data 1017 directly to the memory array system 1001, a mode for transmitting and outputting the physical address itself from the main CPU unit 1013 is also provided in the access control unit 1003. Therefore, in order to make the property of the address information and the output timing seen from the memory array system 1001 equal under each condition, the page address data is once input to the CA controller 1010 as described above and the timing is adjusted. ing. CA controller 1010 is the main CPU
The page pointer 1005 and the column pointer 10 are directly connected to the access operation to the memory array 1001 of the section 1013.
07 and control information 1020, 1021 (read information, write information, address strobe, etc.)
Output to 01. The memory array system 1001 outputs necessary data to the main CPU unit 1013 in response to the access information.

As described above, in the present embodiment, the complicated addressing processing conventionally executed by the CPU is executed by the access control unit independently of the CPU, thereby speeding up the access operation and reducing the overhead of the CPU. I am trying to In the two-dimensional array memory system shown in FIG. 1, it is possible to integrate a portion corresponding to the access control unit in the CPU as one of the functions of the CPU in the future (one chip if the integration degree of the LSI is improved. It will be possible to integrate the function in the CPU). However, it may be necessary to provide a separate bus system for accessing other subsystems and resources that require normal linear access. In that case, the number of input / output pins increases in an LSI CPU. However, it is possible to design the CPU so that access to the array memory system and access to other subsystems and resources can be performed in parallel, and there is a possibility that higher speed can be achieved.

Next, the configuration and operation of each part of this embodiment will be described in detail. First, as shown in FIG. 1, the PA controller 1009 which is the management control unit of the page pointer is
A decoder (DEC) 1022 which decodes an instruction and access operation information from the unit 1013 and analyzes whether or not a command to itself is generated, and is used internally in response to the access operation of the CPU. A machine state controller (MSC) 1023 that generates various control signals (commands, latch triggers, etc.) and clock signals, and eight page address registers (PAREG, hereinafter referred to as PA registers) as one set, for a total of eight sets. Page address register file (PAREGF) 1011 and PA register addressing operation (addition increment, decrement)
And a page counter (PACNT, hereinafter referred to as PA counter) 1016 for executing processing and updating the value to an appropriate value. Address bus A is used to set the value in the PA register.
In response to the setting command sent by the DDR1015 control bus (CTL) 1024, the machine state controller 1023 transfers data from the main CPU unit 1013 to the data bus 10.
This is done by writing the page data sent by 14.

PA register file (PAREGF) 10
The structure of 11 and the structure of the PA counter (PACNT) 1016 are the column address register file (CAREG, hereinafter referred to as CA register file) shown in FIG. 3 described later.
And the column address counter (CACN shown in FIG.
T, hereinafter referred to as CA counter), and has almost the same structure except a part. Therefore, a detailed description will be given later in the CA controller, and a brief description will be given here. The PA register file 1011 is composed of eight page address registers (PAREG, hereinafter referred to as PA registers) as a set of banks, and eight sets of the banks are provided. The value that determines which of the eight PA registers is selected is called the stack address, and the value that determines which of the eight sets of banks is selected is called the bank address. These two address values are respectively generated by the stack address counter and the bank address counter. One PA register to be used is selected by stack address and bank address,
The page pointer is determined based on the value of the PA register.

The PA counter (PACNT) 1016 has a function of performing a specified addressing process on the selected PA register. For basic addressing processing,

[Equation 1] PAREG ← PAREG + OFFSET, PA
There are four types: REG ← PAREG + 1, PAREG ← PAREG-1, and no change in PAREG. As the OFFSET value, the value of the offset register provided one by one corresponding to each PA register bank set is usually used, but it can also be directly given from the main CPU section 1013 as an immediate value (immediate data).

In the configuration of the PA controller as described above, by operating the bank address counter,
It realizes management of loop nest during vector processing and management of complicated loop processing that requires a plurality of page pointer variables in the same level loop. Increment Stack Point (Increment Stack Point)
Point), Decrement Stack Point
ACK Point), the main CPU unit 1013 can manage a plurality of pointer variables by switching the page pointer using these instructions in the loop processing. There is also prepared an instruction to execute a combination of the stack counter operation instruction and the data load or data store operation from the main CPU unit 1013 to the PA register at the same time.

FIG. 5 shows basic instructions prepared in the PA controller 1009. WTCD0, 1, 3, 6 and RDCD0, 1, 3, 6 are the PA registers (PARE
G) command for changing data load, store and stack address to WTCD 5, 7 and RDCD
References 5 and 7 are instructions relating to changing the bank address. The implementation method of the instruction shown in FIG. 5 in the assembly language and the description method of the application software using the assembly language will be described in detail later.

On the other hand, the CA pointer management control unit (CA controller) 1010 is similar to the PA controller 1009.
It operates in response to a command from the CPU unit 1013, access operation information, and the access operation itself. A machine circuit controller (DEC) 1026 that decodes the information and a machine state controller that generates various control signals (commands, latch triggers, etc.) and clock signals used internally in response to the access operation of the CPU. MSC) 1027 and column address register (CAREG, hereafter referred to as CA register) are set as a set of 8 registers, and a total of 8 sets of column address register files (CAREG,
Hereinafter, the CA register file 1012 and the CA register addressing operation (addition, increment, decrement) are executed to set the CA register value to an appropriate C value.
CA counter (CACN) for updating to A point data value
T) 1018 and page point data sent from the PA controller 1009 and CA point data generated in the CA controller 1010 are combined to generate address data to be given to the memory array system. The address latch (AL) 1019 is provided.

Although the basic operation of the CA controller 1010 is the same as that of the PA controller 1009 in many parts, the main CPU 1013 sends an address bus (ADDR) 1015 and a control signal ( CT
L) 1024 is used. This is done by using the data bus (DATA) 1014 of the main CPU unit 1013 as actual data (main CPU
In order to reduce the access overhead as much as possible, the instruction command processing to the CA controller 1010 and the access processing to the memory array are operated in parallel by assigning the transfer processing of the processing target data of the unit 1013). Is. Further, the column pointer 1007 is likely to be randomly accessed from the main CPU unit 1013, and it is necessary to make the addressing process highly efficient. Especially the main CPU
When the unit 1013 accesses the memory data, the function of simultaneously designating the addressing mode is important, and the instructions for realizing those are accessed by the access instruction (Access).
(Instruction). If the access operation is performed by using the access instruction, the data of the memory address pointed to by the pointer at that point can be accessed by the normal access overhead, and at the same time, the address value to be accessed next can be set. The corresponding pointer to C
The CA counter 1018 in the A controller 1010 has calculated and immediately updates the contents of the currently specified CA register 1012 to the value when the access is completed.

FIG. 3 shows a CA register file (CARE
2 shows the structure of GF) 1012. The above-mentioned PA register file 1011 has almost the same structure as this. If the column address (CA) is replaced with the page address (PA) in the description here, the corresponding portion can be directly described as the PA register file. In FIG. 3, the CA register file 1012 has eight CA register (CAREG) sets 2003 to 2010 and eight offset register sets (OFFSETREG) 2022 to 2029, and the corresponding CA registers (positioned on the left and right in FIG. 3). One set consisting of one set and one offset register is collectively called a register bank (register banks 0 to 7). Further, one CA register set is composed of eight CA registers (REG0 to REG7) 2012 to 2019. The CA pointer is obtained by adding the column address (CADDDR) 10201 and the offset (OFFSET ADDR) 10202 output from the CA register set and offset register that form one register bank, by the CA counter 1018 in FIG. Then, as a normal usage, one CA register set is assigned to one operation loop or one operation task (or job). The individual loop processes constituting the plurality of loops or the multiple loops executed therein are managed by using one or several CA registers in the CA register set. The eight registers in each CA register set are selected by the stack address counter (STACKADDRCOU) in the register selection circuit (REGSELCTL) 2037.
Stack address (SA) output from NTER) 2036
DDR) 10203 is performed by the decoder circuit (DEC) 2011 in each CA register set. In addition, the register banks 0 to 7 are selected by the bank address counter (BANKADDRC) of the register selection circuit 2037.
Bank address (B
ADDR) 10204. Eight stack addresses corresponding to the register bank are built in the stack address counter 2036.
When 204 is switched, the stack address 10203 is also switched to the one corresponding to that register bank. The stack address counter 2036 increments or decrements the stack pointer currently selected to select the CA register (PUSH, PSH) in the register bank currently selected.
The processing (corresponding to the OP function) is instructed via the SADDR10203 signal.

Selection of the register banks 0 to 7 requires selection of CA register sets 2003 to 2010 and selection of offset registers. Among them, the CA register set is selected by the write processing decoder (DEC for WT) 2001 when writing to the register set.
Decode 10204 to specify the CA register set to be written, and when reading from the CA register set, bank the select input S of the multiplexer (MUX) 2021 for selecting the column address (CA) 10205 to 10212. This is done by giving an instruction at address 10204. On the other hand, the offset register set is selected by the offset data (OFFS
ET) 10213-10220 and mode data (MD) 10221-1
Multiplexer (MUX) 20 for instructing to read 0228
The selection input S of 35 is performed by commanding the bank address 10204.

Each of the offset registers 2022-2029 is
Two temporary offset registers (TOFFSET
H) 2030 and TOFFSET LRG 2031 and mode register (MODERG) 2032. The offset data consists of the offset field value (OFFSETL) 10229 in the data of the selected CA register in the corresponding CA register set and the temporary offset register (TOFFSETH) 2030.

## EQU00002 ## Configured as OFFSET = TOFFSETH: OFFSETL, or with two temporary offset registers

[Formula 3] OFFSET = TOFFSETH: TOFFS
Configured as ETLRG, multiplexer (MUX) 2034
You can select with. The offset data constructed in this way
One of the data 10213 to 10220 is defined as the output value of the offset register, which is selected by the multiplexer 2035 to become the offset address 10237.
DDR) 10202 to the CA counter 1018. The offset address 10202 can be directly designated by the address input (IADDR) 10230 from the main CPU section. That is, machine state controller
When the external designation mode is commanded by the control signal (ICTL) 10231 from the 1027, the register selection circuit 2037 operates the selection input S of the multiplexer (MUX) 2052, and the IAD
Directly set the value of DR10230 as offset address 10202 to C
Send to A counter 1018. One mode register (MODERG) 2032 provided in each offset register
Is used to define various operation modes (access mode, addressing mode, etc.) when the CA register is used, as will be described later. The data of this register 2032 is the multiplexer (MUX) 2035,
Based on the information, the register selection circuit (RGSELC
The TL) 2037 generates an appropriate state in response to the access operation of the main CPU unit 1013.

In addition to the above bank registers, the main CP
A temporary address register (TADDR) is used so that temporary data instructed from the U unit 1013 via the IADDR 10230 can be used as the column address 10201.
REG) 2051 is provided. Further, when it is desired to temporarily use the current value of the column address 10201, that is, the currently selected CA register or temporary address register for another purpose, the value is temporarily copied and copied later. − Eight temporary registers (TRE) for temporary storage so that the stored data can be restored and processing can proceed.
G0 to TREG7) 2041 to 2048 are provided. As an operation instruction of this temporary register, a load / load between an arbitrary temporary register and the currently selected CA register is performed.
Store command or arbitrary TREG and currently selected CA
An EXCHANGE command for exchanging the contents of REG is provided. These commands related to the operation of the temporary register are also instructed by the main CPU unit 1013, and the register selection circuit 2037 generates and executes the necessary states.

All states of the CA register are managed by the register selection circuit 2037. The register selection 2037 is a control signal (I) from the machine state controller 1027 which monitors the operation of the main CPU unit 1013.
CTL) 10231, address input (IADDR) 10230 from the main CPU 1013, and M from the mode register.
The state of the CA register file 1012 is determined by combining with the ODE information. In addition, in response to the access operation of the main CPU unit 1013 to the memory array, a necessary sequence including addressing processing operation is generated. The functions of the register selection circuit 2037 are summarized below. (1) Based on the information of the machine state controller (MSC) 1027 and the information of the address input IADDR10230 from the CPU, the access operation to the memory array of the main CPU section 1013 is monitored and in response to the access operation. It outputs each switch signal (select signal of MUX), write signal WT to register file, and address signal to each decoder. (2) The decoding of the instruction from the main CPU unit 1013 is performed by the decode circuit of the register selection 2037 using the address input (IADDR) 10230 and the control signal (ICTL) 10231 from the machine state controller 1027, The command is identified and the corresponding process is executed. (3) The stack address counter 2036 and the bank address counter 2039 are managed, and the stack address 10203 for selecting the register (REGn) in the CA register set and the bank address 10204 for selecting the CA register set and offset register to be used are generated. (4) Temporary register (TREG) file selection signal S, data (ID) write signal WT to selected TREGn, and TREG selection signal S to be read
Is output. The above two selection signals can be generated at the same time (used for the EXCHANGE command or the like).
These signal outputs are used to execute the load store, EXCHANGE command for any TREG. (5) Regarding the control of the multiplexer (MUX) for controlling the flow of data, the following functions are specified. (A) Input of data to the CA register set (ID)
The external address data (IADDR) 10230 is used, the data from the temporary registers 2041 to 2048 is used, or the data IRADDR10232 after the addressing calculation processing is added by the CA counter is used. . (B) Select which CA register set and offset register set to use. (C) As the column address 10201, it is selected whether to use the value of the CA register 10235 currently used or the value of the temporary address register 10236. (D) As the offset address 10202, it is selected whether to use the value of the output 10237 of the currently selected offset register or to use the external address data (IADDR) 10230. (6) A control signal and a selection signal (collectively referred to as OCTL10234) to the CA counter 1018 are output. (7) Stack address counter 2036 increases / decreases (INC /
The stack address to be subjected to DEC) processing is set to the bank address 10204 from the bank address counter 2039.
Is used to determine to correspond to the corresponding bank register set. (8) The return address data (IRA) 10232 after the addressing calculation processing from the CA counter 1018 is CA
Multiplexer (MUX) for mode input to register
2002 is set, the main CPU unit 1013 to the memory array 10
Immediately after the current access operation to 01 ends,
Write 10232 to the selected CA register. As a result, vector type addressing processing (CAREG = CA) accompanied by offset addition by the CA counter 1018
REG + OFFSET).

Next, FIG. 4 shows a CA counter (CACNT).
A block diagram within 1018 is shown. This counter is basically the column address 10304 sent from the CA register file 1012.
And offset address 10306 are added, or +1 (INCREMENT) or -1 is added to column address 10304.
(DECREMENT) is added to generate the column access address (CADDDR). As the control signal, the register selection circuit 20 in the CA register file 1012 is used.
The ICTLA control signal 10305 which received the OCTL 10234 output from the 37 and the machine state controller (MS
C) ICTLB control signal bus 10 directly output from 1027
Use 308 and. Mainly, ICTLA10305 is a CA counter
The 1018 state (which defines the selection state of multiplex and the selection state of addressing mode) is defined, and the ICT
The LB 10308 defines the timing at which the CA counter 1018 operates. The operation is as follows.

First, the adder (ADDER) 3002 adds the data to be added (ADAT) 10304 input to A and the address offset value input to B, and the result 10313 is obtained.
Is output (OUT). Address offset value 10312
Is the BDAT 10306 that has received the offset address from the CA register file 1012 and the INC / DEC circuit 3003.
Data (1 for INC, -1 for DEC) are switched by a multiplexer (MUX) 3001 and used. Output 10313 from adder 3002 and column address itself value from CA register file 1012 (ADAT)
10304 and direct address data (ADDR) 103 from the outside
One of 01 is selected by the multiplexer 3004, and the final column access address (CAADDR) 10314 value is determined. This determined value is the CA register file.
It returns to the IRADDR (IRA) 10314 input of 1012 and is latched by the address latch (AL) 1019. The address latch 1019 also CAADs the page address data (IPA) 10310 sent from the PA controller 1009.
Overall address OPAD that is latched at the same timing as DR10314 and given to the memory array
DR10316: Generate OCADDR10315. The latch timing to the address latch 1019 is the latch control (CTL) 10 from the machine state controller 1027.
Appropriate at 309. As a result, when seen from the external memory system, a series of memory address signals are observed like the address signals directly sent from the main CPU unit 1013. When the address signal from the main CPU unit 1013 is directly used as the OCADDDR 10315, the selection signal S may be set so that the multiplexer 3004 selects the external address (ADDR) 10301.

As described above, the INC / DEC 3003 circuit commands the adder 3002 to perform increment addressing or decrementing addressing by giving 1 or -1 to the address offset value. INC / DE
The command to the C circuit 3003 is sent by the selection signal 10305 from the register selection circuit 2037 in the CA register file 1012.
Mode switching (deciding between INC mode and DEC mode)
And a timing signal 10308 from the machine state controller 1027.

To specify the mode of the addressing process by these CA counters, the addressing mode is selected in advance by the mode register in the CA register file 1012, and the memory is used when the access instruction is issued. Addressing mode at the same time as access to the array
There is a method to select the mode. The timing for latching the processed address in the address latch 1019 is the main CP.
This is immediately after the access operation to the memory array 1001 is executed by the U unit 1013.

FIG. 11 shows a basic instruction set prepared for the CA controller 1010. It has almost the same configuration as the PA controller 1009, but it has temporary register operation instructions and data PUSH / PO to the CA register.
An instruction, etc., which combines the P instruction and the addressing process and is executed at once, is added. Further, it also has a direct access instruction for executing one instruction by combining the data access and the addressing processing including the mode selection as shown in FIG. A detailed description of the CA controller 1010 instruction, an implementation method in assembly language, and a description method of application software will be described below.

The two-dimensional array memory system is a main CP
The main CPU is issued by a command from the U section to the access control section.
Supports both various vector-type access functions from the part to the memory array and normal scalar-type random access functions. Of these, as described above, the hardware function of the access control unit is effectively utilized when the vector type access is executed. The instruction set embodying these functions is incorporated in a part of its own instruction set when viewed from the main CPU section, and can be used in a program together with the instructions of the normal main CPU section. All the two-dimensional array memory system operation instructions are replaced with data transfer instructions (MOV instructions, etc.) between the main CPU section and a specific address area, and integrated with other instruction sets of the main CPU section. ing. Therefore, unlike the normal data transfer instruction, which only realizes the data movement between the resource and the register as a function, in this system, in addition to that, the command is given by the address line or the data line. A specific function (function of a two-dimensional array memory system) is realized.

Two instruction sets are provided in one access control unit, one for the PA controller and one for the CA controller. In addition, the instruction sets are provided independently by the number of units of the access control units existing in the system. In the case of this system, it is possible to issue a command independently to the access control units 1003 and 1004. The details will be described below using an instruction set table.

First, the instruction set for the PA controller and the implementation to the assembly language will be described. The PA controller is a two-dimensional array A (m,
n) The column direction parameter m (page pointer) is controlled. The configuration of PA register set and offset register set, and the number of bank register sets are CA
Like the controller, but does not currently have a temporary register file. The hardware function is C
Compared to the row direction parameter n (column pointer) by the CA controller, the column direction parameter generally has a smaller outer loop (loop on the shallow side of the nest) than the A controller. This is because the overhead is considered to be sufficiently smaller than the overhead for controlling the parameters in the row direction for the purpose of management. Therefore, the instruction set is also smaller than the instruction set of the CA controller, which will be described later, and is more compact. Further, the PA controller also does not include a direct access instruction that realizes addressing processing including selection of an addressing mode in parallel with the access operation by the main CPU unit. The access operation from the main CPU section to the memory array is first performed by C
It is managed by the A controller side, and the PA controller is instructed to perform the addressing process of the column direction parameter by a signal (OPGCAS) for activating the PA controller as necessary. Therefore, the access control to the basic memory array is basically performed on the CA controller side, and the PA controller operates as the slave unit.

FIG. 5 shows the basic instruction set of the PA controller described above. The basic command is designated by the decoding information CS of the address to which the PA controller is assigned.
N, byte access enable BE1N to BE3N, write / read designation signal W / R. The functions are classified as follows. (PA1) PA register (PAREG) operation instruction WTCD1 ---- Data (D) from the outside to the PA register
T) Load WTCD0 ---- After incrementing the stack pointer of PA register, data (DT) load to the PA register from outside RDCD1 ---- After decrementing the stack pointer of PA register, Data from the PA register to the outside (D
T) Store (PA2) Offset register (OFFSETREG)
Operation instruction WTCD4 ---- External data to offset register (DT) load RDCD4 ---- External data from offset register (DT) store (PA3) Stack pointer (stack address counter Value) Operation instruction WTCD3 ---- Data from outside to stack pointer (DT) load RDCD3 ---- Data from stack pointer to outside (DT) Store (PA4) Bank pointer (Bank address Counter value) or mode register operation instruction (D22, D2 here)
3 will be described in FIG. 6). WTCD5 ---- Data from outside to the bank pointer (D
T) load <D22 = 0, D23 = 0> RDCD5 ---- Data from bank pointer to outside (D
T) Store MODE --- Mode set <D22 = 1, D23 = 0>,
(The function of the mode bit set by this mode set instruction is as shown in FIGS. 7 and 8.) (WTCD5) External address set <D22 = 0, D23
= 1>, software reset <D22 = 1, D23 = 1> (PA5) Stack pointer increment (PUS
H), decrement (POP) command WTCD6 ---- STACK POINT (SP) = SP
+1 (PAREG PUSH, INCrement) RDCD6 ---- STACK POINT (SP) = SP
-1 (PAREG POP, DECrement) (PA6) Bank pointer increment (PUS
H), decrement (POP) command WTCD7 ---- BANK POINT (BP) = BP +
1 (BANK PUSH, INCrement) RDCD7 ---- BANK POINT (BP) = BP-
1 (BANK POP, DECrement)

FIG. 6 shows the mode selection for the instructions WTCD5 and RDCD5. Data bus (D
It is possible to select four kinds of write commands WTCD5 by using D22 and D23 bits in (ATA). Read command RD
When CD5 is issued, the current value of the bank address can always be read. Above command (PA1)
In (PA6), an instruction that needs to exchange data (DT) with the outside is a necessary data (DT) communication with the main CPU unit via the data bus (DATA). I do. At this time, the byte enable / BEn indicating a valid byte on the data bus (4 bytes of byte enable / BE0 / BE3 exist because this system assumes a 32-bit bus) is active ( The byte 0) holds valid data at the data input / output with the PA controller. However, as described above, in the mode selection shown in FIG. 6, since the data bits D22 and D23 are used as the function selection signals, the effective data bits are 5 bits of D16 to D21. Set D16 to bit0 and D21 to bit5, and set the mode register instruction (Set Operation Mode D22 = 1,
FIG. 7 shows the functions defined when D23 = 0) issuance. This instruction defines various addressing modes and functions, and when the main CPU unit accesses the memory array, the designated function is executed in response to the PGCAS signal from the CA controller.

In FIG. 8, how the addressing process using the PA register as the destination register is executed in response to the access of the main CPU by designating each mode bit of the mode register 2032 (FIG. 3). Was shown. When the specified addressing process is executed and the value of the PA register is updated when the main CPU unit accesses the memory array and the CA controller activates the PGCAS signal (Acces
s and PG Change) and the value of PA register is not updated under the same condition (Access and PG no Change).
It is roughly classified into two conditions, e).

Next is the implementation of the instruction set for the PA controller into the assembly language. This can be replaced by data transfer instructions (for example, MOV instructions) regardless of the form of the main CPU. it can.
The data transfer instruction is a common instruction that exists in the instruction set regardless of which CPU is used, regardless of the generation or type of the CPU. Therefore, it can be said that the PA controller instruction set (also the CA controller instruction set is common) has very high portability and property.

An example of specific instruction registration in the assembly language is shown in FIGS. The CPU is Intel i8
It is assumed that 086 CPU or i80X86 CPU is used. The instructions of these PA controllers can be expressed by matching the parameter (address label) name expressing the address value to which the instruction is assigned with the instruction mnemonic (Inst.). FIG. 9 shows an instruction set model (Instruction) in the assembly language of basic instructions.
Set Model). The description method when actually used in a program is as follows. PACTLx ES: [Inst. ], AX (or AL) for WRITE PACTLx AX (or AL), ES: [Inst. ] For READ where x is a parameter for distinguishing a plurality of PA controllers, and in this system, the access control unit 1003
Is assigned to x = 0, and the access control unit 1004 is assigned to x = 1. On the other hand, FIG. 10 shows a bank point operation command,
3 shows a parameter setting model in an assembly language of a bit set instruction and an access instruction.
The command expression is as follows. PACTLx ES: [MDSET], Parameter + Data (DT) for WRITE PACTLx ES: [BPSET], Parameter + Data (DT) for WRITE PACTLx AL, ES: [BPRD] for READ Address label MDSET, BPSET and BPRD
Is the same as the value of SETMD in FIG. 9, but is used for convenience as an easy-to-understand mnemonic. MDSET represents a mode bit set instruction, BPSET represents a base pointer set, and BPRD represents a base pointer read.

Next, the instruction set for the CA controller and the implementation to the assembly language will be described. The CA controller is a two-dimensional array A (m,
n) The row direction parameter n (column pointer) is controlled. Unlike the PA controller, a special address area for assigning an instruction is not provided, but instead, an instruction is generated by overlapping the address space assigned to the memory array as seen from the main CPU section. The address space for is assigned. The specific method is as follows. a) Access from the main CPU to the memory array
Doubleword (32bit) for specific address area
Limited to two types of access and word (16bit) access. That is, byte access to the memory array in that area, double word access across double word boundaries, and word access across word boundaries are invalidated, and those access modes are used as instructions to the CA controller. Assign. b) In this system, the specific address area described in a) is used for byte access and double word access (0
(000000000000) ₂ to (1111111111111) ₂ , that is, the entire area, and during word access (1110000000000) ₂ to (11111111)
11111) ₂ .

Parameters are set in the internal registers using the address bus (ADDR), and the value of the written data or the state of the internal registers cannot be directly read like the PA controller. Not possible (of course, it is possible by devising the circuit, but I think that there is little merit because it has a temporary register file inside). The merits of using such an instruction assign method are as follows. 1) Since it is not necessary to use the data bus (DATA) for instructing an instruction, the transfer processing of the target data using the data bus between the memory array and the main CPU unit and the C
The instruction generation process for the A controller can be executed concurrently. 2) Does not consume extra memory space for instruction assignment. Since one CA controller instruction set always corresponds to one memory array, this advantage is always effective even when a larger number of memory arrays are provided.

FIG. 11 shows the basic instruction set for the CA controller. The instruction is specified by address bits A2 to A12,
The write / read designation signal W / R and the byte access enable signals BE0N to BE3N are used. It becomes possible to specify an instruction to the CA controller during the period of accessing the assigned address space of the corresponding memory array (equivalent to the role of the CSN signal when instructing the instruction to the PA controller). The functions of instructions are classified as follows. (CA1) CA register (CAREG) operation instruction WTCD0 ---- Data (D) from the outside to the CA register
T) Load WTCD1 ---- After incrementing the stack pointer to the CA register, data from the outside to the CA register (DT) load RDCD0 ---- Decrement the stack pointer to the CA register After that, data from outside (CA) to CA register (DT) load RDCD1 ---- Direct data from outside (Imm.Data)
Is added to the current CA register and the result is returned to that CA register. (CA2) Offset register (OFFSETREG)
Operation instruction WTCD2 ---- Data from outside to offset register (DT) load RDCD2 ---- Direct data from outside (Imm.Data)
Is added to the current offset register and the result is returned to that offset register. (CA3) Stack pointer (stack address counter value) and bank pointer (bank address counter value) operation instruction WTCD3 ---- Data from outside to stack pointer (DT) load RDCD3 ---- external From the bank pointer to the bank pointer (D
T) load (CA4) stack pointer increment (PUS)
H), decrement (POP) command WTCD12 ---- STACKPOINT (SP) = SP +
1 RDCD12 ---- STACKPOINT (SP) = SP-
1 (CA5) Bank pointer increment (PUS
H), decrement (POP) instruction WTCD13 ---- BANKPOINT (BP) = BP + 1 RDCD13 ---- BANKPOINT (BP) = BP-1 (CA6) mode register, addressing mode setting instruction WTCD4 ---- Mode register setting (see Fig. 12) RDCD8 ---- Address bus equivalent mode setting (external address is directly output to memory array) RDCD9 ---- Adding address mode setting (CAREG =
CAREG + OFFSETREG) RDCD10 ---- Increment address mode setting (C
AREG = CAREG + 1) RDCD11 ---- decrement address mode setting (CA
REG = CAREG-1) (CA7) System mode setting command WTCD14 ---- Temporary address register mode setting (select temporary address register instead of CA register) RDCD14 ---- Partial reset (set stack pointer Initialize and set the default value to the mode register. WTCD15 ---- Mode that does not change the CA register (N
o Change Mode) RDCD15 ---- CA controller software reset (function equivalent to hard reset) (CA8) Temporary register operation instruction WTCD16 ---- Stores CA register contents in temporary register n WTCD17- --- Load the contents of temporary register n to CA register WTCD18 ---- Exchange the contents of CA register and the contents of temporary register n (CA9) PA controller start instruction, addressing execution instruction with stack operation WTCD19-- --Active PGCAS signal output to PA controller (PA controller startup) RDCD16 ---- SP = SP-1, CAREG = CARE
G + 1 (CAREG POP and CAREG INC) RDCD17 ---- SP = SP-1, CAREG = CARE
G-1 (CAREG POP and CAREG DEC) RDCD18 ---- SP = SP-1, CAREG = CAREG + OFFSETREG (CAREG POP and CAREG ADD) RDCD19 ---- SP = SP-1, CAREG = CARE
G + I mm. (CAREG POP and CAREG Imm. ADD)

FIG. 12 shows the mode register setting instruction WTCD.
4 shows the function of the right bit of the mode register set in 4. Almost the same function as the mode register of the PA controller is assigned. The data set in the mode register is the address bits A2 to A7 (total of 5 bits).
Specify with t).

Unlike the PA controller, the access instruction in the CA controller can simultaneously execute the addressing process and the input / output of target data in real time when accessing the memory array. In addition, P that is the activation trigger signal of the PA controller
Whether to activate the GCAS signal can also be designated at the same time. That is, by the access instruction of the CA controller, the pointers m and n (page pointer and column pointer) in the two-dimensional array A (m, n) on the memory array can be simultaneously controlled in conjunction with the PA controller, and the data can be concurrently deserialized. -I / O can be executed.

FIG. 13 shows the access instruction set supported by the CA controller. There are double word (32 bit) access and word (16 bit) (upper word, lower word) access as access modes, and addition (CAREG ADDition) and increment (CAREG INCrement) as addressing modes. , Decrement (CAREG DECrement) and zero addition (No
Change). Whether or not to interlock the PA controller is specified by address bit A4 (PGA when A4 = 0)
S active, PGCAS noactive when A4 = 1)
Then, whether to read or write the data is specified by the W / R signal (reading when W / R = 0, writing when W / R = 1).

The implementation of the instruction set for the CA controller into the assembly language is very easy as in the case of the PA controller. In the case of the PA controller, "PGCTL" was used as the representative mnemonic, and the mnemonic "Inst." Expressing the function of the instruction could be expressed using the operand address designation value (address label) itself. However, in the CA controller, since the operand address designation value includes the data field, the mnemonic expressing the function is implemented so as to match the representative mnemonic. As a result, a general operant addressing value can be expressed by the sum of the specific address value expressing the instruction and the data value to be instructed to the CA controller.

FIG. 14 shows a basic instruction set model of assembly language expression in the CA controller.
As with the PA controller, the Intel i8086, i
This is an example of expressing the assembly language of 80X86 CPU. In order to distinguish a plurality of CA controllers, the value of the start address of the memory array is set to the reference address value (CACT
LADDRx), and the offset address value for expressing each instruction is added to the specified data value n * 4 or n * 16 depending on the case to determine the overall operant address value. Here, the value of n corresponds to the original data (DT) that should be specified, and the value that is multiplied by 4 or 16 (shifted) is the actually specified value (n * 4,
n * 16). In this system, since there are two memory arrays, the reference address value CACTLADDRx
Corresponds to the access control unit 1003, CACTLA
Corresponding to DDR0 and access control unit 1004, CAC
It is set to TLADDR1. In actual operation, the specified data
If the data (DT) does not exist, it is not necessary to specify the operant part, and even if the specified data exists, it is not necessary to specify the operant address other than the specified data. The following is an actual description example in assembly language. (Ex1) When operand data exists INST. <ES: CACTLx> [n * 4] INST. <ES: CACTLx> [n * 16] The above two cases are for specifying constant data. INST. <ES: CACTLx> [BX (or SI or
DI)] This is the case of specifying variable data. (Ex2) When operand data does not exist INST. <ES: CACTLx>

FIG. 15 shows a parameter model in setting data (DT) in the mode register of the CA controller. Data to the mode register in assembly language
The data setting command expression is as follows. SETMD <ES: CACTLx,> AX Register data SETMD <ES: CACTLx,> Imm. Direct data

FIG. 16 shows an access instruction set model expressed in assembly language in the CA controller. An actual description example in assembly language is as follows. (Ex3) In case of write access INST. <ES: CACTLx,> ERX (or RX
or Imm. ) (Ex2) Read access INST. ERX (or RX or Imm.) <, ES: C
ACTLx> * ERX Double word register RX word register

[0048]

The present invention has the following effects. 1. A large linear memory system is not required, and addressing processing and access instruction processing can be performed without relying on the CPU for all the operations. Therefore, it is not necessary to describe the management and access operation of the memory space by the OS or software, and the overhead can be made small while being highly versatile. 2. By reducing the number of instructions needed to access the memory, it does not require much memory to hold the instruction code. Since a series of operations for reading and writing one data can be performed with a small number of instruction codes, the cost per memory access can be reduced. 3. Above 1. 2. Therefore, when designing a cost-oriented industrial computer, the cost occupied by the memory can be minimized. 4. Instruction code sequence and array data sequence (file system,
Since it is designed on the assumption that the data that can be processed in a vector manner, such as numerical processing data, tables, model data, etc., occupies the majority of the memory system, addressing processing, etc. are executed in advance. Therefore, it is possible to avoid unnecessary operations at the time of access, and it is possible to access at high speed in a short access time. 5. Since the addressing process in the CPU is not required, the overhead of waiting for access is reduced, and the designated (addressed) data (operand data)
Can be quickly taken into the CPU and processing can be added to the data. From the above, the access efficiency on the CPU side is further improved, and the CPU
This has the effect of contributing to the speedup of itself.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a two-dimensional array memory system of the present invention.

FIG. 2 is a diagram illustrating the configuration of one unit of a memory array.

FIG. 3 is a column address register file (CAREG
It is a block diagram which shows the structural example of F).

FIG. 4 is a block diagram showing a configuration example of a column address counter (CACNT).

FIG. 5 is a list of basic instruction sets of the PA controller.

FIG. 6 PA controller instructions WTCD5 and RDC
It is a figure which shows the mode selection code of D5.

FIG. 7 is a list of functions when a mode register set instruction is issued.

FIG. 8 is a diagram showing an addressing process corresponding to the contents of a mode register.

FIG. 9 is a diagram showing an instruction set model in an assembly language of a PA controller basic instruction.

FIG. 10 is a diagram showing a parameter setting model in an assembly language of a bank point operation command, a mode bit set command and an access command.

FIG. 11 is a list of basic instruction sets of the CA controller.

FIG. 12 is a diagram showing a function of a right bit of a mode register.

FIG. 13 is a diagram showing an access instruction set supported by a CA controller.

FIG. 14 is a diagram showing an instruction set model in an assembly language of CA controller basic instructions.

FIG. 15 is a data setting parameter model for the mode register of the CA controller.

FIG. 16 is an access instruction set model in assembly language representation in a CA controller.

[Explanation of symbols]

 1001 memory array 1002 memory array 1003 access control unit 1004 access control unit 1009 page controller 1010 column address controller 1011 page address register file 1012 column address register file 1013 main CPU unit 1018 column address counter 1019 address latch 1023 machine state Controller 1027 Machine state controller

Claims (16)

[Claims] 1. A memory array configured for addressing with a set of a page pointer and a column pointer,
Two-dimensional, characterized by comprising a page address controller for generating the page pointer in response to access from the central processing unit, and a column address controller for generating the column pointer in response to access from the central processing unit Array type memory system. 2. The column address controller comprises a column address register file consisting of a plurality of column address registers, an offset address for a column given separately, and an address set by the central processing unit in the column address register. And a column address counter that generates the column pointer from the page address controller, the page address controller includes a page address register file including a plurality of page address registers, an offset address for a separately given page, and a central processing in the page address register. 2. The two-dimensional array type memory system according to claim 1, comprising a page address counter for generating the page pointer from an address set by a device. 3. The two-dimensional array type memory system according to claim 2, wherein the column address register and the page address register can set arbitrary values. 4. The column address controller, a latch for temporarily storing a column pointer generated by the column address counter and a page pointer generated by the page address counter, and timing of the two pointers from the latch. And a control means for outputting the same to the memory array.
The two-dimensional array type memory system described. 5. The column address register file includes a plurality of column address register sets including a plurality of the column address registers, an offset register corresponding to each column address register set, the column address register set, and the column address register set. A selection circuit for selecting the offset register and the column address register in the selected column address register set is provided, and the column address counter is selected from the contents of the column address register and the corresponding offset register selected by the circuit. Generates a column pointer according to claim 2, wherein the two-dimensional array type memory system according to claim 2 or 4. 6. The page address register file includes a plurality of page address register sets including a plurality of the page address registers, an offset register corresponding to each page address register set, the page address register set, and A selection circuit for selecting an offset register and a page address register in the selected page address register set is provided, and the page address counter is selected from the contents of the page address register selected by the circuit and the corresponding offset register. The two-dimensional array type memory system according to claim 2 or 4, wherein the page pointer is generated. 7. A mode register is provided for each of the offset registers, and the contents of the offset register are updated according to the mode set in the mode register by access from the central processing unit. The two-dimensional array type memory system according to item 6. 8. A structure is provided in which a selector for selecting the output of the offset register and the direct address data from the central processing unit is provided, and the selection by the selector can be made by the output of the mode register. Item 2. A two-dimensional array type memory system according to item 7. 9. The two-dimensional array type memory system according to claim 2, wherein the column address controller is provided with a temporary register for a first column address capable of transferring data to and from the column address register. 10. The two-dimensional array type memory system according to claim 2, wherein the page address controller is provided with a temporary register for a first page address that can transfer data to and from the page address register. 11. The column address controller is provided with a second temporary register and a multiplexer that can be directly addressed by a central processing unit, and the multiplexer reads out the address read from the column address register file and the second temporary register. The two-dimensional array type memory system according to claim 2, wherein the set address is selected and output. 12. The page address controller is provided with a second temporary register and a multiplexer that can be directly addressed from a central processing unit, and the address read from the page address register file by the multiplexer and the second temporary register are provided. The two-dimensional array type memory system according to claim 2, wherein the set address is selected and output. 13. Two-dimensional array data whose elements are defined one by one for a set of row number and column number, the row number can be designated by the page pointer and the column number can be designated by the column pointer. 2. The two-dimensional array type memory system according to claim 1, wherein the two-dimensional array data is stored in the memory array as much as possible, and the two-dimensional array data is accessed by operating the page pointer and the column pointer from a central processing unit. 14. A two-dimensional array memory system, wherein a portion corresponding to an access control unit is integrated in the CPU as one of the functions of the CPU. The two-dimensional array type memory system according to claim 1. 15. The CPU according to claim 14, wherein the CPU is provided with another bus system for performing access to other subsystems and resources that require normal linear access. Two-dimensional array type memory system. 16. The CPU according to claim 15, wherein the CPU has a function of executing access to the two-dimensional array memory system and access to another subsystem or resource in parallel. Dimensional array type memory system.