JPH0683518B2 - Data transfer method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transfer system implemented when digitally processing a voice signal or the like.

BACKGROUND ART A typical prior art is shown in FIG. In this prior art, stereo audio signals of two left and right channels are
For surround processing, it is converted into a 4-channel signal and digitally processed. Left and right two audio signals are input terminal 1
From the line 3 to the analog / digital conversion circuit 2 and converted into left and right two-channel digital signals. The digital signal processing circuit 4 converts a digital audio signal of 2 channels into 4
It is converted into a channel audio signal, is led to the line 5, and is applied to another digital signal processing circuit 6. The digital signal processing circuit 6 digitally processes the 4-channel audio signal and derives the 4-channel audio signal to the line 7. The 4-channel signal means that speakers are arranged on the front left side FL, the front right side FR, the rear left side RL, and the rear right side FR, respectively, in order to increase the sense of presence and the like. It is possible to individually give audio signals to the speakers and drive them.

The register 8 included in the digital signal processing circuit 6 is provided with a digitized register 4 in the mode shown in FIG.
Audio signals for channels are stored. The audio signals given to the positions of the speakers are the same as the reference numeral F.
L, FR; RL, RR respectively. The signals FL, FR; RL, RR for each of these channels each consist of 16 bits.
The 4-channel audio signal derived from the line 7 is applied from the switching circuit 9 to the two digital / analog conversion circuits 10 and 11, respectively. One of the digital / analog conversion circuits 10 derives the audio signals of the front left and right FL, FR, respectively, and the other digital / analog conversion circuit 11 derives the audio signals of the rear right RL, RR.

Problems to be Solved by the Invention In such a prior art, the switching circuit 9 supplies the digital audio signals of the front left and right FL, FR in the register 8 to one digital / analog conversion circuit 10, and then the rear left and right. It is necessary to switch the audio signals so that the digital audio signals of the side RL, RR are applied to the other digital / analog conversion circuit 11 and then sent. Therefore, the switching circuit 9
Is (a) a counter that counts the clock signal in synchronization with the clock signal for transmitting each bit of data from the register 8, and (b) a digital value of the front left and right FL, FR calculated by this counter. Number of audio signal bits (= 16
Until counting a total of 32 bits which is +16), one of the stable states is maintained. We need a flip-flop that is in another stable state. Also, based on the output of this flip-flop, a digital / analog conversion circuit
It is necessary to switch between 10 and 11 to activate them. Therefore, there is a problem that the switching circuit 9 has a relatively complicated structure. Furthermore, since the 4-channel system and the 2-channel system have completely different configurations, there is a problem in compatibility.

It is an object of the present invention to provide a data transfer system capable of switching and supplying a serial digital signal from a digital signal processing circuit at a preceding stage to two digital signal processing circuits at a subsequent stage with a simple configuration. is there.

The present invention relates to a first digital signal processing circuit, comprising two registers for respectively storing data to be transmitted and deriving in series in response to a clock signal, and the clock. Such a first digital signal processing circuit including switching means for alternately and sequentially deriving outputs from the two registers in response to a signal; and in response to a change in the clock signal, the first digital signal processing circuit Two second digital signal processing circuits for receiving data from the switching means, wherein the clock signal is applied to one of the second digital signal processing circuits, and the clock signal is inverted to the other second digital signal processing circuit. It is a data transfer system characterized by being applied to a signal processing circuit.

Operation According to the present invention, the first digital signal processing circuit in the preceding stage has two registers, and the signals from the respective registers are alternately and sequentially synchronized by the switching means in synchronization with the clock signal. Of the two second digital signal processing circuits in the subsequent stage, one of the two second digital signal processing circuits in the latter stage receives and receives the second digital signal of the other in response to the change of the clock signal, that is, the rising edge of the clock signal or the falling edge of the clock signal. The processing circuit receives in response to the change in the clock signal obtained by inverting the clock signal. Therefore, it suffices to provide a configuration in which the clock signal is inverted and provided between the first and second digital signal processing circuits, and the counter and flip-flop as described in connection with the above-mentioned prior art are provided. The present invention does not require a switching circuit, which simplifies the configuration.

Further, in the first digital signal processing circuit, each of the two channels of the digital signal converted into four channels can be easily separated, so that the four-channel output method and the two-channel output method, which are difficult in the prior art, are used. Full compatibility of is obtained.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. The analog left / right two-channel audio signal input to the input terminal 13 is converted into a two-channel digital audio signal in the analog / digital conversion circuit 14, and is supplied from the line 15 to the digital signal processing circuit DSP1. The digital signal processing circuit DSP1 digitally processes the two-channel audio signal input via the line 15 to improve the presence like a surround system. The front left FL, the front right FR, and the rear FR. The four-channel audio signals to be given to the speakers arranged on the left side RL and the rear right side RR, respectively,
It is led to a line 16 and supplied to the first digital signal processing circuit DSP2 according to the present invention.

In this digital signal processing circuit DSP2, the 4-channel audio signal given from the line 16 is further digitally processed, and the 16-bit audio signal of each of the front left and right FL, FR is stored in the shift register 17 in series. Rear left and right side RL, R
The R audio signals are stored in the other shift registers 18, respectively. In the shift registers 17 and 18, the arrangement of speakers and the corresponding digital audio signal are indicated by the same reference numerals FL, FR; RL and RR, respectively.

From the clock signal generation circuit 19, a clock signal having a predetermined example frequency shown in FIG. 2 (1) is led to the line 20 and given to the input terminal 21 of the digital signal processing circuit DSP2. The clock signal is given to the control circuit 22 provided in the digital signal processing circuit DSP2. In response to the clock signal applied to the input terminal 21, this control circuit 22 derives the signal shown in FIG. 2 (2) on the line 23, and also the inverted waveform of the signal from the line 23 on the line 24. The signal shown in FIG. 2 (3) is derived. The other control circuit 25 receives the signals from the lines 23 and 24, derives the signal shown in FIG. 2 (4) on the line 26, and the signal shown on FIG. 2 (5) on the line 27. Derive. The signals derived from the lines 26 and 27 are synchronized with the clock signal applied to the input terminal 21,
The signals derived from 26 and 27 have waveforms of opposite polarities.

The signal derived from the line 26 is given to the shift register 17 and the AND gate G1. The signal derived from the line 27 is supplied to the shift register 18 and the other AND gate G2. In response to the signal from the line 26, the shift register 17 outputs an audio signal consisting of 16 bits each of the front left and right FL, FR stored therein, as shown in FIG. 2 (6). It derives sequentially one by one. Similarly,
The shift register 18 responds to the signal on line 27 by
An audio signal consisting of 16 bits on each of the rear left and right sides RL and RR is derived bit by bit as shown in FIG. 2 (7). In FIG. 2 (6), FL1 to FL6 represent the 1st to 6th bit data of the audio signal of the front left FL, and similarly, in FIG. 2 (7), RL1
.. to RL5 represent the first to fifth bit data of the rear left RL audio signal, respectively.

The audio signals for each bit from the shift registers 17, 18 are given to the AND gates G1, G2, respectively. AND gate G
The audio signals from 1 and G2 are given from the OR gate G3 via the output terminal 28 and the line 29 to the digital / analog conversion circuits 30 and 31 which are two second digital signal processing circuits, respectively. The digital signal derived from the output terminal 28 is as shown in FIG. In this way, in response to the clock signal applied to the input terminal 21, the audio signals stored in the shift registers 17 and 18 are sequentially and serially derived from the output terminal 28 by one bit at a time. . A switching unit is configured to include the NAD gates G1 and G2.

The clock signal from the clock signal generation circuit 19 is also directly applied to the digital / analog conversion circuit 30 from the line 20 and is also applied to another digital / analog conversion circuit 31 via the inverting circuit N1. The digital / analog conversion circuits 30 and 31 have the same configuration. The digital / analog conversion circuit 30 is connected to the second circuit via the line 20.
In response to the rising edge of the clock signal shown in FIG. 1A, the audio signal on line 29 is received and stored bit by bit. Therefore, digital / analog conversion circuit
Among the digital audio signals on the line 29 shown in FIG. 2 (8), the numeral 30 bit-sequentially outputs only the audio signals stored in the shift register 17 shown by reference characters FL1, FL2, FL3, .... It is received and converted into an analog audio signal of two channels in total of the front left and right FL, FR and is derived.

The other digital-analog conversion circuit 31 responds to the rising edge of the clock signal via the inverting circuit N1, which causes RL1, RL2, RL3, among the audio signals shown in FIG.
Only the audio signals stored in the shift register 18 are bit-sequentially received as shown in FIG.
It is derived by converting it into an analog audio signal of a total of 2 channels of R.

In this way, the output terminal of the digital signal processing circuit DSP2
The audio signal from 28 is commonly given to the following two digital / analog conversion circuits 30 and 31 from the line 29, and the clock signal from the clock signal generation circuit 19 is directly supplied to these circuits DSP2; 30 and 31. And via the inverting circuit N1 for control. Therefore, the structure can be simplified.

The invention can be implemented not only for processing audio signals, but also widely in other technical fields. Digital / analog conversion circuit 30,31
Instead of this, a circuit having a configuration for performing other digital signal processing may be used.

Effect As described above, according to the present invention, the output data of the first digital signal processing circuit can be alternately transferred to the two second digital signal processing circuits with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 3, FIG. 3 is a block diagram of the prior art, and FIG. 4 shows data stored in the register 8 of the prior art shown in FIG. It is a figure which shows a mode. 17,18 …… Shift register, 19 …… Clock signal generation circuit, 22,25 …… Control circuit, 30,31 …… Digital / analog conversion circuit, DSP1, DSP2 …… Digital signal processing circuit, G1, G2
…… AND gate, G3 …… OR gate, N1 …… Inversion circuit

Claims (1)

[Claims] 1. A first digital signal processing circuit, comprising two registers for respectively storing data to be transmitted and serially deriving in response to a clock signal, and in response to said clock signal, said register Such first digital signal processing circuit including switching means for alternately and sequentially deriving outputs from the two registers, and receiving data from the switching means in response to a change in the clock signal. And a second second digital signal processing circuit for providing the clock signal to one of the second digital signal processing circuits and inverting the clock signal to provide the other second digital signal processing circuit. Data transfer method characterized by.