JPH0683291B2 - Serial communication method - Google Patents

Description

The present invention relates to a serial communication system, and more particularly to a serial communication system for exchanging data between ICs.

[Conventional technology]

Conventionally, in this kind of serial communication, the acknowledge signal (hereinafter, ACK signal) for returning from the receiving side to the transmitting side with respect to the data sent from the transmitting side to the receiving side shares the data line or uses a dedicated line. It was common to send them back.

For example, as shown in FIG. 2, the same data line 20 is used for the data sent from the transmitting side to the receiving side on the data line 202.
In step 3, the active side ACK signal 203a is returned from the receiving side to the transmitting side. Here, 202 and 203 are on the same line, and the line driver circuit has an open drain structure. Therefore, the data line can be connected by wired OR.

[Problems to be Solved by the Invention]

However, in the above-described conventional serial communication method, the data line is shared, so that the structure of the transmission or reception IC that drives the data line cannot have the push-pull structure, and has to be the open drain structure. It was Therefore, when trying to transfer high-speed data, the waveform becomes blunt, and there is a problem in high-speed transfer. Also, the bus switching must be done in a short time,
From this aspect, there is a drawback that it is not suitable for high-speed transfer.

[Means for Solving the Problems]

The serial communication system of the present invention controls a data line for transferring data between at least two communication circuits, a clock line for sending a clock synchronized with a bit sequence of the data, and a start and stop of transmission. And a busy line fixed to the first logic level by a pull-up resistor (or pull-down resistor).
The busy line is set to the second logic level for a certain period for the receiving side to confirm the ACK when the data is received, and when the transmitting side confirms this, the output is released at a timing shorter than the above timing, and the state of this line Is configured to receive the ACK confirmation of the receiving side.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a communication network which is an embodiment of the present invention. As shown in FIG. 1, the communication circuits IC ₁ and IC ₂ are connected in parallel to a clock line 1, a data line 2 and a busy line 3. The busy line 3 is connected to the power supply V _DD via the pull-up resistor R ₁ . Each communication circuit IC ₁ and
The IC ₂ includes an output drive circuit 4 and an input circuit 5 connected to the busy line 3, and a transmission / reception control unit 6.

When IC ₁ is the transmitting side and IC ₂ is the receiving side, the transmission / reception control unit 6 of the IC ₁ first lowers the busy line 3 through the output drive circuit 4 to start the transmission. Next, clock line 1 and data line 2 are driven, and the clock and data are
Send to IC ₂ . The IC ₂ receives this clock and data, decodes it by the transmission / reception control unit 6, and at the end of 1-byte data, outputs the busy line 3 which is pulled to low level by the output drive circuit 4 of IC _{1 by} the output drive circuit 4 of IC _2. ACK
Further pulls to low level as output. Sender IC ₁
In order to confirm the ACK output of the receiving side IC ₂ , the output drive circuit of the IC ₁ can be made high impedance (Hi-Z state) and confirmed by the input circuit 5.

FIG. 3 is a timing chart of the logic level of each line for explaining the operation of the communication network of FIG.

The operation of the communication network shown in FIG. 1 will be described below with reference to FIG. In FIG. 3, the start 34 is performed by the transmitting IC ₁ pulling the busy line 34 to the low level. After that, the clock and the data are transmitted on the clock line 31 and the data line 32. When the receiving IC ₂ receives the data D _{1 to} D ₀ sent from the transmitting side, it outputs the ACK output 37 indicating that the data is received to the same busy line 33 at the timing of A _{1 to} A ₄ . Since this busy line 33 has a wired OR structure with an open drain structure, if the busy line drive 4 on the transmission side during this period
Even if is turned off, the bus line should be fixed at low level. For this reason, the busy line drive 4 on the transmitting side is turned off at the timing of A _{2 to} A ₃ , which is shorter than A _{1 to} A _4, and ACK confirmation 38
Perform.

In this way, by placing the ACK output on the busy line, it is not necessary to use the data line bidirectionally, and even if capacity is added by driving the clock line and data line in the push-pull format on the transmission side. Since the driving impedance can be lowered, high-speed data transfer becomes possible.

As an example, even if the driving impedance is 300Ω and the wiring capacitance is 1000 pF, only a waveform delay of 0.2 μs occurs.
Also, set 1 for ACK confirmation 38 to transfer at very high speed.
If you always pull it to a low level when you want to interrupt the time, you will have confirmed the ACK for the bus, and you can also support high-speed transfer. In addition, the sender tries to confirm the ACK, Hi-
If the ACK output is not output when the Z state is set, the busy line becomes high level. This is the same as a stop and can automatically suspend the bus.

〔The invention's effect〕

As described above, according to the serial communication method of the present invention, the ACK confirmation output from the receiving IC to the transmitting IC, which has been placed on the conventional data line, is multiplexed with the busy line for controlling the start and stop of the data line at high speed. There is an effect that it can be controlled and extremely high speed communication can be enabled.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a communication network using an embodiment of the present invention, FIG. 2 is an explanatory view of data transfer of a conventional communication network, and FIG. 3 is a description of data transfer operation of the communication network of the present invention. FIG. 6 is a timing diagram of logic levels of each line for the purpose of explanation. 1 ... Clock run-in, 2 ... Data line, 3 ...
Busy line, 4 ... Output drive circuit, 5 ... Input circuit,
6 ... Transmission / reception control unit, 31 ... Clock line (transmission side), 32 ... Data line (transmission side), 33 ... Busy line (transmission side), 34 ... Busy line (reception side), 35 ...
… Start, 36 …… Stop, 37 …… ACK output, 38 …… A
CK confirmation.

Claims (1)

[Claims] 1. A data line for transferring data between at least two communication stations, a clock line for transmitting a clock synchronized with a bit sequence of the data, and a busy line for controlling start and stop of transmission. Connected, the data receiving station side outputs an acknowledge signal indicating that data has been received to the data transmitting station side on the busy line, and the transmitting station side outputs the acknowledge signal for a period shorter than the output period of the acknowledge signal. A serial communication system characterized by receiving the acknowledge signal by detecting the level of a busy line.