CN112087241A - Method for realizing single-wire communication of elevator bus button - Google Patents
Method for realizing single-wire communication of elevator bus button Download PDFInfo
- Publication number
- CN112087241A CN112087241A CN202010818356.1A CN202010818356A CN112087241A CN 112087241 A CN112087241 A CN 112087241A CN 202010818356 A CN202010818356 A CN 202010818356A CN 112087241 A CN112087241 A CN 112087241A
- Authority
- CN
- China
- Prior art keywords
- bus
- slave
- master
- communication
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B66—HOISTING; LIFTING; HAULING
- B66B—ELEVATORS; ESCALATORS OR MOVING WALKWAYS
- B66B1/00—Control systems of elevators in general
- B66B1/34—Details, e.g. call counting devices, data transmission from car to control system, devices giving information to the control system
- B66B1/3415—Control system configuration and the data transmission or communication within the control system
Landscapes
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Indicating And Signalling Devices For Elevators (AREA)
Abstract
The invention discloses a method for realizing single-wire communication of an elevator bus button, which comprises the following steps: the method adopts a 4-wire bus connection mode on the basis of a traditional universal asynchronous receiving and transmitting transmitter, and achieves synchronous real-Time communication of a single bus by adding a Multiplexing mechanism of simultaneous in and simultaneous out on software and hardware.
Description
The technical field is as follows:
the invention relates to the field of elevator control, in particular to a method for realizing single-wire communication of an elevator bus button.
Background art:
at present, a pair of signal wires and three power wires are generally arranged on a bus button of an elevator, and the bus button has the defects of large communication load, slow speed in the communication acquisition process, more communication lines and low real-time property in response, transmission and query.
The invention content is as follows:
the invention provides a method for realizing single-wire communication of elevator bus buttons, which aims to overcome the defects of the existing elevator bus button communication, increase the communication reliability, reduce the line link and accelerate the acquisition speed of a slave machine.
The technical solution of the invention is as follows:
a method for realizing single-wire communication of elevator bus buttons is characterized in that single-wire communication of elevator master and slave devices is realized by adopting a 4-wire bus connection mode, and the method comprises the following steps:
(A) the master device and the slave device are connected with a 4-wire bus;
(B) a conversion circuit is added on the basis of the original asynchronous transceiver;
(C) synchronous communication is realized by transmitting a synchronous signal, a write signal and a read signal through signals of a master device and a slave device.
Preferably, the step (a) means that all the master-slave devices are connected in parallel to the 4-wire bus, each master-slave device has two ports, each port can be linked with the next button or master device without any sequence, and only one master device can be provided in a single bus link.
Preferably, the conversion circuit added in step (B) is that the device (host or slave) is connected to the data bus through an open-drain or tri-state port, so as to allow the device to release the bus when not sending data and allow other devices to use the bus.
Preferably, the master device in step (C) sends the synchronization signal, the write signal, and the read signal to be transmitted through the bus under the software condition of the same frequency, the same space, and the same orthogonal code, the slave device calculates corresponding time after receiving the synchronization signal, the corresponding ID position of the slave device is corresponded by the calculated time, and the corresponding byte position is set and reset on the byte information of the read signal sent by the master device to implement synchronous real-time communication.
Preferably, the 4-wire bus connection is adopted, the wire sequence is that 3 power lines are respectively used as a slave device power supply, 1 data line is used as a communication bus to link a master device and a slave device, the master device and the slave device can be provided with power supplies independently, but the ground ends of the master device and the slave device are required to be linked into a whole.
Preferably, the control circuit disconnects the bus link and protects the master and slave if an overcurrent condition such as a short circuit occurs during the transmission of the bus.
The invention has the beneficial effects that:
1. the invention relates to a method for realizing single-wire communication of an elevator bus button, wherein link wires of a master machine and a slave machine are respectively 1 DC24V, 1 logic power supply (+3.3V/+5V), 1 ground wire and 1 data wire, lines among all devices are connected in parallel on a 4-wire bus, and meanwhile, the devices (the master machine or the slave machine) are connected to the data bus through an open-drain or three-state port so as to allow the devices to release the bus when not sending data, and other devices use the bus.
2. The invention discloses a method for realizing single-wire communication of an elevator bus button, wherein a host is responsible for providing a data transmission period, the host is used for outputting slave data in a write period and simultaneously reading back all slave data, the data transmission between the master and the slave is transmitted in a frame mode, and one frame of data is formed by the write period and the read period. Compared with the traditional two-wire communication mode, the single-wire communication method has the advantages that the slave machine responds only after the host machine scans the slave machine, the slave machine responds in the byte amount, the response steps are reduced in the communication mode, the byte is converted into the bit address in the communication transmission efficiency, the query efficiency is improved, and the bus communication load is reduced.
3. The invention relates to a method for realizing single-wire communication of an elevator bus button, which is characterized in that the baud rate of the existing double-wire control is determined by a clock wire in the communication, and data is transmitted by a data wire.
Description of the drawings:
FIG. 1 is a block diagram of an elevator single bus push button wire communication system of the present invention;
FIG. 2 is an elevator single bus button bus switching circuit of the present invention;
fig. 3 is a schematic elevator bussing wiring of the present invention;
fig. 4 is a waveform diagram of a single bus communication of the elevator of the present invention;
fig. 5 is a waveform diagram of dual bus communication of the elevator of the present invention.
In the drawings: 1. a single bus button front; 2. the back of the single bus button; 3. controlling an elevator; 4. a bus button host; 5. a power source; 6. a power line; 7. a bus button slave; 8. communication bus
The specific implementation mode is as follows:
the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in the figure I, a 4-wire bus connection mode is adopted, on the basis of a traditional universal asynchronous receiver-transmitter, a conversion circuit is added on hardware, single-bus synchronous real-time communication is realized, a single bus (1-wire) is adopted, namely, only one data line is used for data exchange and control, and equipment (a host or a slave) is connected to the data line through an open-drain or three-state port, so that the equipment can release the bus when not sending data, and other equipment uses the bus.
Specifically, two 4-wire ports 1# are arranged on the back of the key and are respectively connected with the input and output of the key and the input and output of the controller, and the 2# port and the 1# port play the same expanding role.
Specifically, the master is responsible for providing a data transmission cycle, and is used for outputting slave data in a write cycle and simultaneously reading back all slave data.
Specifically, the data transmission between the master device and the slave device is transmitted in the form of frames, a write cycle and a read cycle constitute a frame of data, and an idle time is inserted between the frames as a synchronization frame, which is also called a frame interval.
The communication process of the master and the slave is briefly described as follows:
1. and (3) synchronization: after the host finishes the communication of one frame of data each time, the communication bus is released, the release bus maintains a high level state, and the duration is more than 41.6ms so as to facilitate the synchronization and the state confirmation of the slave.
2. The write cycle is composed of 1 byte command data, 9 bytes slave panel status data (key indicator), and 1 byte check data. The maximum write cycle time is 22.88 ms.
3. The read cycle consists of a 9byte key unique ID and the slave responds after transmission by padding 0 or 1 in the corresponding bit of the nine bytes. The maximum read cycle time is 18.72 ms.
4. And the host sends synchronization and repeats the steps.
The total time of the master-slave communication is T1, and the read-write period is (T1-
The synchronous duration T2) is equal to (22.88+18.72) ms, the universal asynchronous bus transceiving mode is set as 1-bit start bit, 8-bit data bit and 1-bit stop bit, and the corresponding single-bit time is converted as follows:
(22.88+18.72)÷(1+9+1+9)/(1+8+1)＝208us/bit
the same frequency 208us/bit is adopted for the communication of the master and the slave machines to be converted into asynchronous receiving and transmitting bit rate:
1s÷208us/bit＝4807.69bit/s
the asynchronous receiving and transmitting bit rate is 4800bps after conversion because the master and the slave adopt asynchronous receiving and transmitting.
The total time length of the communication between the master and the slave is not more than 100ms, which is calculated from the communication time between the master and the slave, i.e. the frame interval and the total time length of the data frame, assuming that the number of the slaves is (9byte × 8 bits) ═ 72, the longest query period is 100ms, and the time required for a single query of the slave is:
100ms÷72＝1.39ms
i.e. the slave can answer once in 1.39 ms.
Specifically, as shown in fig. one, the power supply provides one DC24V and 1 ground wire to the bus button master, the bus button master provides 1 DC24V wire, 1 ground wire, and 1 logic power supply (+3.3V/+5V) to the bus button slave, and the power supplies form a loop.
Specifically, as shown in the first figure, the bus button master is responsible for reading and writing of the bus button slave and response of the elevator master.
Specifically, as shown in fig. one, the bus button slave is responsible for submitting the physical feedback processing of the button to the bus button master.
Specifically, as shown in fig. two, the link lines of the master and slave are respectively 1 DC24V, 1 logic power supply (+3.3V/+5V), 1 ground line, and 1 data line, and the lines between all the devices are connected in parallel to the 4-line bus.
Specifically, as shown in the second embodiment of the single bus switching circuit, a device (master or slave) is connected to the data line through an open-drain or tri-state port, which allows the device to release the bus when it is not sending data, and allows other devices to use the bus.
Specifically, as shown in fig. two, the transceiving principle of the working single bus B _ DAT is as follows:
1. when the asynchronous transceiver transmitting end control triode Q22 works in the intercept region, the bus B _ DAT voltage is obtained by dividing three resistors R86R 87R 88, and the calculation formula is as follows:
Ua＝DC24V-DC24V×(R86÷(R86+R87+R88))
the default bus level voltage is calculated to be 21.53V, and B _ DAT pulls the bus low after the transistor is operating in saturation via R86. At this time, the bus voltage is close to 0V, and thus the bus high-low level voltage is high level 21.53V, and the bus low level voltage is 0V.
2. The level voltage of the receiving end of the asynchronous transceiver is determined by a U4 single-circuit Schmitt inverter, the input voltage Vi of No. 2 pin of U4 is determined by a resistor R86R 87R 88, and the voltage calculation formula is as follows:
Ub＝DC24V-DC24V×((R86+R87)÷(R86+R87+R88))
when the voltage of B _ DAT is high level, Vi is calculated to be about 6V, and when the voltage of B _ DAT is low level, the Vi voltage is close to 0V, and then the voltage is clamped to be 5V at high level through a D6 clamp protection diode, and the low level is 0V to be used as the input voltage Vi of U4.
3. As shown in fig. two, the receiving and transmitting of the asynchronous transceiver are both connected to the single bus B _ DAT, so that when the asynchronous transceiver transmits a high level, the bus voltage is a low level, and at this time, the voltage obtained at the receiving end of the asynchronous transceiver is a high level, which concludes that the asynchronous transceiver also receives the transmitted level signal while transmitting, and the single bus key communication physical link is based on this.
Specifically, as shown in the second drawing, the transmitting end of the master and slave machines is connected with the B _ DAT bus through an open-drain circuit, the receiving end of the master and slave machines is connected with the B _ DAT bus through an inverse schmitt trigger, and the master machine is connected through the above circuit, the slave level signal is opposite to the B _ DAT signal, so that the asynchronous transceiver can receive the B _ DAT signal through the inverse level signal of the bus while transmitting the signal, and the physical layer connection of the circuit is completed.
Specifically, as shown in fig. two, the voltage at the top end of the capacitor C23 is protected by a diode when the bus voltage is normal, and when the voltage of the single bus B _ DAT is too high, the voltage is released to the positive power supply, and the signal with negative voltage is released to the ground.
Specifically, as shown in fig. three, one less signal synchronization line is used compared to a dual bus. Part 1 refers to the front side of the slave button and part 2 is the north side of the slave button.
Specifically, as shown in the fourth diagram, the B _ DAT bus transmit-receive waveform includes a bus high level voltage of 24V, a bus low level voltage of 0V, and a sampling period of 480 MS. The waveform of the method is that sending and reading are carried out twice, wherein the upper half 1 refers to a synchronous signal between reading and writing frames of a host, the synchronous signal is used for carrying out data synchronization and state confirmation on a button slave, and the first bit from low level to high level represents the beginning of reading and writing.
Specifically, as shown in fig. four, the lower part 2 is that a total of 11 bytes of write data sent by the master are used for ID setting of the slave, and the panel light indication signal, and the part 3 is that a total of 9 bytes of null data sent by the master are used for setting corresponding bits in the 9 bytes by the bus button slave according to the own ID value.
Specifically, as shown in fig. five, it is a schematic diagram of a timing sequence of the two-wire bus communication. The sampling period is the same as that of the fourth graph, the high level voltage of the bus is 3.3V, and the low level voltage of the bus is 0V. Where the upper part 1 refers to the data signal and the lower part 2 represents the signal for data transmission.
Specifically, as is shown by comparing the four diagrams and the five diagrams, the voltage of a transmission level is increased to 24V for the purpose 1, the anti-interference capability of data transmission is improved, the attenuation of a remote transmission signal is reduced, and the purpose 2 can effectively reduce the system load by reducing one clock line under the software condition of the same frequency, the same space and the same orthogonal code, and can remove the phenomena of signal dislocation, packet loss and the like of the data line caused by the interference of the clock line.
The working principle of the invention is as follows: the master machine, the slave machine level signal and the B _ DAT signal are opposite through the circuit linkage, so that the asynchronous transceiver can receive the signal through the reverse level signal of the bus while sending the signal, after the circuit physical layer linkage is completed, the slave machine determines the corresponding ID position of the slave machine according to a synchronous frame after the master machine releases the communication bus, so as to complete the synchronization and the state confirmation with the master machine, and a write cycle comprises command data, slave machine panel state data and verification data, wherein the command data is used for the ID positioning of the slave machine, the slave machine panel state data is used for a panel indicator lamp, and the verification data is used for asynchronous verification, the method comprises the steps of preventing error codes, when a reading cycle is started, sending 9 bytes of null data by a host, filling 1 or 0 in a corresponding position in a reading signal by each slave according to a previously obtained ID, feeding back a physical state of a slave button, finishing one scanning, starting a next synchronous frame, synchronizing all the slaves with the host and starting the next scanning, and distributing 9 bytes of all the slaves to 72 bit addresses in total, namely realizing single-line real-time communication through division of each time period in frequency.
The above description is only a preferred embodiment of the present invention, and all other embodiments obtained by those skilled in the art without any inventive work shall fall within the scope of the present invention.
Claims (5)
1. A method for realizing single-wire communication of an elevator bus button is characterized by comprising the following steps: the single bus communication of the master and the slave devices of the elevator is realized by adopting a 4-wire bus connection mode, and the method comprises the following steps:
(A) the master device and the slave device are connected by adopting a 4-wire bus;
(B) a conversion circuit is added on the basis of the original asynchronous transceiver;
(C) synchronous communication is realized by transmitting a synchronous signal, a write signal and a read signal through signals of a master device and a slave device.
2. The method for realizing single-wire communication of the elevator bus button according to claim 1, is characterized in that: the step (A) means that all the master and slave devices are connected in parallel on a 4-wire bus, the master and slave devices are provided with two paths of ports, each port can be linked with the next button or master device without the sequence, and only one master device can be arranged in a single bus link.
3. The method for realizing single-wire communication of the elevator bus button according to claim 1, characterized in that: the conversion circuit added in the step (B) is that the device (host or slave) is connected to the data bus through an open drain or three-state port, so as to allow the device to release the bus when not sending data and allow other devices to use the bus.
4. The method for realizing single-wire communication of the elevator bus button according to claim 1, characterized in that: and (C) the master device in the step (C) sends a synchronous signal, a write signal and a read signal to be transmitted through a bus under the software conditions of the same frequency, the same space and the same orthogonal code, the slave device calculates corresponding time after receiving the synchronous signal, the corresponding ID position of the slave device is corresponded through the calculated time, and the corresponding byte position is set and reset on the byte information of the read signal sent by the master device to realize synchronous real-time communication.
5. The method for realizing single-wire communication of the elevator bus button according to claim 1, characterized in that: the line sequence adopting 4-line bus connection is that 3 power lines are used as slave equipment power supplies respectively, 1 data line is used as a communication bus to link master and slave equipment, the master and slave equipment can also be independently provided with power supplies, but the ground ends of the master and slave equipment are connected into a whole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010818356.1A CN112087241A (en) | 2020-08-14 | 2020-08-14 | Method for realizing single-wire communication of elevator bus button |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010818356.1A CN112087241A (en) | 2020-08-14 | 2020-08-14 | Method for realizing single-wire communication of elevator bus button |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112087241A true CN112087241A (en) | 2020-12-15 |
Family
ID=73729136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010818356.1A Pending CN112087241A (en) | 2020-08-14 | 2020-08-14 | Method for realizing single-wire communication of elevator bus button |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112087241A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115834282A (en) * | 2022-11-07 | 2023-03-21 | 交控科技股份有限公司 | CAN bus communication method, device, equipment and readable storage medium |
| WO2023072373A1 (en) * | 2021-10-26 | 2023-05-04 | Kone Corporation | Elevator communication system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1662008A (en) * | 2004-10-20 | 2005-08-31 | 天津市英克瑞电子技术有限公司 | Communication method of half duplex serial bus with clock singal and communication system |
| CN103823776A (en) * | 2014-02-28 | 2014-05-28 | 上海晟矽微电子股份有限公司 | Unibus in communication with master equipment and slave equipment and communication method |
| CN104657303A (en) * | 2014-10-13 | 2015-05-27 | 江苏瑞微电子有限公司 | Unibus data communication method |
| CN104811273A (en) * | 2015-04-02 | 2015-07-29 | 福州大学 | Implement method for high speed single bus communication |
| CN106506725A (en) * | 2016-11-25 | 2017-03-15 | 阳光电源股份有限公司 | Subordinate communication system, main frame, slave and slave ID distribution methods |
-
2020
- 2020-08-14 CN CN202010818356.1A patent/CN112087241A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1662008A (en) * | 2004-10-20 | 2005-08-31 | 天津市英克瑞电子技术有限公司 | Communication method of half duplex serial bus with clock singal and communication system |
| CN103823776A (en) * | 2014-02-28 | 2014-05-28 | 上海晟矽微电子股份有限公司 | Unibus in communication with master equipment and slave equipment and communication method |
| CN104657303A (en) * | 2014-10-13 | 2015-05-27 | 江苏瑞微电子有限公司 | Unibus data communication method |
| CN104811273A (en) * | 2015-04-02 | 2015-07-29 | 福州大学 | Implement method for high speed single bus communication |
| CN106506725A (en) * | 2016-11-25 | 2017-03-15 | 阳光电源股份有限公司 | Subordinate communication system, main frame, slave and slave ID distribution methods |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023072373A1 (en) * | 2021-10-26 | 2023-05-04 | Kone Corporation | Elevator communication system |
| CN115834282A (en) * | 2022-11-07 | 2023-03-21 | 交控科技股份有限公司 | CAN bus communication method, device, equipment and readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8694710B2 (en) | Conversion of a two-wire bus into a single-wire bus | |
| EP0183273B1 (en) | Serial interface system flexibly applicable to a one-to-plurality connection | |
| CN100573382C (en) | Based on I 2The communication system of C and communication means | |
| CN112087241A (en) | Method for realizing single-wire communication of elevator bus button | |
| CN102023954A (en) | Device with multiple I2C buses, processor, system main board and industrial controlled computer | |
| JP2851879B2 (en) | Data communication device | |
| WO2008145011A1 (en) | Parallel signal transmitting method of uninterrupted power supply | |
| CN210624840U (en) | Two-wire power supply communication circuit | |
| CN113242168B (en) | Single bus communication method | |
| US4989203A (en) | Apparatus for providing multiple controller interfaces to a standard digital modem and including separate contention resolution | |
| CN101281510B (en) | Double-I2C bus setting method and double I2C bus system | |
| CN112506839B (en) | One-to-many SPI bus switching method and device | |
| CN115442178B (en) | Multi-axis servo bus control circuit and multi-axis servo system | |
| US6871241B2 (en) | Interface apparatus, communication device including same, and communication method using same | |
| CN217467655U (en) | Single IO mouth two-way communication structure of singlechip | |
| CN100383773C (en) | Method and device for solving transmission interface bi-directional signal conflict | |
| CN215067812U (en) | CAN network based on CAN controller and gate circuit are constituteed | |
| CN218416404U (en) | Adopt two SPI to realize SSI's slave computer equipment | |
| CN112559424A (en) | Three-wire SPI communication system and method | |
| CN214311734U (en) | Communication device based on SPI communication interface | |
| CN221543743U (en) | Distributed elevator key control device with super-strong anti-interference capability | |
| JP2501450B2 (en) | Gateway | |
| JPS6121656A (en) | Communication control system | |
| CN115277872A (en) | Forward and reverse-based high-reliability data transmission method | |
| JPH0326582B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201215 |
|
| RJ01 | Rejection of invention patent application after publication |