CN108536629B - Communication method of single-bus multi-AND or logic transceiving circuit - Google Patents
Communication method of single-bus multi-AND or logic transceiving circuit Download PDFInfo
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- CN108536629B CN108536629B CN201810171880.7A CN201810171880A CN108536629B CN 108536629 B CN108536629 B CN 108536629B CN 201810171880 A CN201810171880 A CN 201810171880A CN 108536629 B CN108536629 B CN 108536629B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Abstract
The invention relates to a communication system of a single-bus multi-AND or logic transceiving circuit, which comprises a first communicator in equipment 1, a second communicator in equipment 2, a first amplifier A1, a second amplifier A2, a third amplifier A3, a fourth amplifier A4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first triode Q1 and a second triode Q2; the invention also relates to a communication method of the single-bus multi-AND or logic transceiving circuit, which comprises setting the baud rate and the clock signal, outputting the clock signal, performing logic operation on the clock signal and returning the input of the clock signal. The invention combines a plurality of communication lines of logic and or logic or operation into one communication line, thereby reducing the communication lines among the devices and improving the reliability of the communication among the devices.
Description
Technical Field
The invention relates to the technical field of wired data transmission, in particular to a communication method of a single-bus multi-AND or logic transceiving circuit.
Background
The communication between devices commonly used today is usually performed through serial (232/485), parallel, CAN or ethernet ports. However, these communication methods are not suitable for some applications in which a single device transmits a small amount of data but requires high-speed exchange of data among a plurality of devices. For example: when tens of inverters are connected in parallel, each inverter is required to send its own state (generally, 2 to 3 bytes of data) to other inverters, and to receive the state sent by other inverters and logically combine the received state with its own state. And each data exchange is finished within dozens of microseconds, and the traditional CAN or 485 CAN not reach the requirement.
In the current application, each state generally uses a transmission line, the local machine sends out the state of the local machine through an IO port, and reads in the state by another IO port after carrying out logical AND or logical OR operation with the state sent by other machines. The defects are as follows: how many lines there are states to be combined. For example, 2 states S1 and S2 between device 1 and device 2 require logical operations, and 2 communication lines are used.
Disclosure of Invention
The invention aims to provide a communication method of a single-bus multi-AND or logic transceiving circuit, which can combine a plurality of communication lines of logic AND or logic OR operation into one, aiming at the defects in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a communication system of a single-bus multi-AND or logic transceiving circuit comprises a first communicator in a device 1, a second communicator in a device 2, a first amplifier A1, a second amplifier A2, a third amplifier A3, a fourth amplifier A4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first triode Q1 and a second triode Q2;
the input end of the first amplifier A1 is connected with the output end of the first communicator, the output end of the first amplifier A1 is connected with one end of the second resistor R2, the other end of the second resistor R2 is connected with the base electrode of the first triode Q1, the emitting electrode of the first triode Q1 is grounded, and the collector electrode of the first triode Q1 is connected with a power supply through the first resistor R1; the output end of the second amplifier A2 is connected with the input end of the first communicator, and the input end of the second amplifier A2 is connected with the collector electrode of the first triode Q1;
the input end of the third amplifier A3 is connected with the output end of the second communication machine, the output end of the third amplifier A3 is connected with one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with the base electrode of the second triode Q2, the emitting electrode of the second triode Q2 is grounded, and the collector electrode of the second triode Q2 is connected with a power supply through the third resistor R3; the output end of the fourth amplifier A4 is connected with the input end of the second communication machine, and the input end of the fourth amplifier A4 is connected with the collector electrode of the second triode Q2;
the collector of the first triode Q1 is connected with the collector of the second triode Q2.
More specifically, the first communicator and the second communicator are both CPLDs.
A communication method of a single-bus multi-AND or logic transceiving circuit comprises the following steps:
the method comprises the following steps: defining and determining the baud rate of communication, setting the transmission time of each bit of data as t, and setting a high level 1 as recessive and a low level 0 as dominant in a clock signal; the sending end updates and outputs at the integral t moment, and the receiving end reads and inputs between two adjacent integral t moments;
step two: the first signal communication state machine scans the state of the communication bus; if the time that the input end detects that the communication bus presents the continuous recessive level exceeds 10t, the identification bus is idle; when the time exceeds 11t, the output end of the one-signal communication state machine sends a clock signal;
when the current time does not reach 11t, the input end receives dominant level, which means that the second communication state machine starts data transmission first, and the first communication state machine starts data transmission immediately and synchronously and performs clock synchronization;
step three: the bus carries out logical AND and OR operation and returns the operation result to the input end of the one-number communication state machine; the second communication machine communicates in the same way.
More specifically, the clock signal transmitted in step two includes a start bit, a data bit, and an end bit, where the start bit S is fixed to 0, the end bit E is fixed to 1, and a fixed low level is inserted into every 4 bits of the data bit to reduce the length of the previous idle time.
The invention has the beneficial effects that: a plurality of communication lines of logic and or logic or operation are combined into one, so that communication lines among equipment are reduced, and the reliability of communication among the equipment is improved.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a schematic overall structure of one embodiment of the present invention;
FIG. 2 is a schematic diagram of a transmission bit of one embodiment of the present invention;
FIG. 3 is a schematic diagram of a transmit clock signal of one embodiment of the present invention;
FIG. 4 is a schematic diagram of a synchronous clock signal of one embodiment of the present invention;
fig. 5 is a schematic diagram of a logic operation performed on a transmission signal according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
As shown in fig. 1-5, a communication system of a single-bus multi-and-or logic transceiver circuit includes a first communicator 01, a second communicator 02, a first amplifier a1, a second amplifier a2, a third amplifier A3, a fourth amplifier a4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, and a second transistor Q2;
the input end of the first amplifier A1 is connected with the output end of the first communicator 01, the output end of the first amplifier A1 is connected with one end of the second resistor R2, the other end of the second resistor R2 is connected with the base electrode of the first triode Q1, the emitting electrode of the first triode Q1 is grounded, and the collector electrode of the first triode Q1 is connected with a power supply through the first resistor R1; the output end of the second amplifier A2 is connected with the input end of the first communicator 01, and the input end of the second amplifier A2 is connected with the collector electrode of the first triode Q1;
the input end of the third amplifier A3 is connected with the output end of the second communication machine 02, the output end of the third amplifier A3 is connected with one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with the base electrode of the second triode Q2, the emitter electrode of the second triode Q2 is grounded, and the collector electrode of the second triode Q2 is connected with a power supply through the third resistor R3; the output end of the fourth amplifier A4 is connected with the input end of the second communication machine 02, and the input end of the fourth amplifier A4 is connected with the collector electrode of the second triode Q2;
the collector of the first triode Q1 is connected with the collector of the second triode Q2.
To be further explained, the first communicator 01 and the second communicator 02 are both CPLDs.
A communication method of a single-bus multi-AND or logic transceiving circuit comprises the following steps:
the method comprises the following steps: defining and determining the baud rate of communication, setting the transmission time of each bit of data as t, and setting a high level 1 as recessive and a low level 0 as dominant in a clock signal; the sending end updates and outputs at the integral t moment, and the receiving end reads and inputs between two adjacent integral t moments;
step two: the one-number communication state machine 01 scans the state of a communication bus; if the time that the input end detects that the communication bus presents the continuous recessive level exceeds 10t, the identification bus is idle; when the time exceeds 11t, the output end of the one-signal communication state machine 01 sends a clock signal;
when the current time does not reach 11t, the input end receives dominant level, which means that the second communication state machine 02 starts data transmission first, and the first communication state machine 01 starts data transmission immediately and synchronously and performs clock synchronization; as shown in fig. 4, the device 1 first reaches 11t and starts to start transmission; while device 2 has not reached 11t but has received the activation signal of device 1, device 2 immediately initiates transmission with the clock synchronized to 11 t.
Step three: the bus carries out logical AND and OR operation and returns the operation result to the input end of the one-number communication state machine 01; the second communicator 02 communicates in the same manner.
Fig. 5 shows that the CPLD of device 1 sends out 10101010 data, the CPLD of device 2 sends out 00101110 data, and the bus synthesized data is 00101010.
More specifically, the clock signal transmitted in step two includes a start bit, a data bit, and an end bit, where the start bit S is fixed to 0, the end bit E is fixed to 1, and a fixed low level is inserted into every 4 bits of the data bit to reduce the length of the previous idle time.
The above description is only a preferred embodiment of the present invention, and for those skilled in the art, the present invention should not be limited by the description of the present invention, which should be interpreted as a limitation.
Claims (2)
1. A communication method of a single-bus multi-AND or logic transceiving circuit is characterized by comprising a first communicator in a device 1, a second communicator in a device 2, a first amplifier A1, a second amplifier A2, a third amplifier A3, a fourth amplifier A4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first triode Q1 and a second triode Q2;
the input end of the first amplifier A1 is connected with the output end of the first communicator, the output end of the first amplifier A1 is connected with one end of the second resistor R2, the other end of the second resistor R2 is connected with the base electrode of the first triode Q1, the emitting electrode of the first triode Q1 is grounded, and the collector electrode of the first triode Q1 is connected with a power supply through the first resistor R1; the output end of the second amplifier A2 is connected with the input end of the first communicator, and the input end of the second amplifier A2 is connected with the collector electrode of the first triode Q1;
the input end of the third amplifier A3 is connected with the output end of the second communication machine, the output end of the third amplifier A3 is connected with one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with the base electrode of the second triode Q2, the emitting electrode of the second triode Q2 is grounded, and the collector electrode of the second triode Q2 is connected with a power supply through the third resistor R3; the output end of the fourth amplifier A4 is connected with the input end of the second communication machine, and the input end of the fourth amplifier A4 is connected with the collector electrode of the second triode Q2;
the collector of the triode I Q1 and the collector of the triode II Q2 are connected with the communicator I and the communicator II, and the communicators are CPLD;
the method comprises the following steps:
the method comprises the following steps: defining and determining the baud rate of communication, setting the transmission time of each bit of data as t, and setting a high level 1 as recessive and a low level 0 as dominant in a clock signal; the sending end updates and outputs at the integral t moment, and the receiving end reads and inputs between two adjacent integral t moments;
step two: the first signal communication state machine scans the state of the communication bus; if the time that the input end detects that the communication bus presents the continuous recessive level exceeds 10t, the identification bus is idle; when the time exceeds 11t, the output end of the one-signal communication state machine sends a clock signal;
when the current time does not reach 11t, the input end receives dominant level, which means that the second communication state machine starts data transmission first, and the first communication state machine starts data transmission immediately and synchronously and performs clock synchronization;
step three: the bus carries out logical AND and OR operation and returns the operation result to the input end of the one-number communication state machine; the second communication machine communicates in the same way.
2. The method of claim 1, wherein the logic transceiver circuit comprises: the clock signal sent in the second step comprises a start bit, a data bit and an end bit, the start bit S is fixed to be 0, the end bit E is fixed to be 1, and a fixed low level is inserted into the data bit every 4 bits to reduce the length of the previous idle time.
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| CN201810171880.7A CN108536629B (en) | 2018-03-01 | 2018-03-01 | Communication method of single-bus multi-AND or logic transceiving circuit |
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| CN108536629B true CN108536629B (en) | 2021-02-02 |
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Citations (7)
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| US4805137A (en) * | 1987-01-08 | 1989-02-14 | United Technologies Corporation | Bus controller command block processing system |
| CN101373968A (en) * | 2007-08-21 | 2009-02-25 | 艾默龙电子科技（嘉兴）有限公司 | Uni-bus interactive synchronization technology as well as application for integrated circuit thereof |
| CN101404556A (en) * | 2008-10-24 | 2009-04-08 | 伊玛精密电子（苏州）有限公司 | One-wire bus communication method |
| CN101727422A (en) * | 2008-10-29 | 2010-06-09 | 大唐移动通信设备有限公司 | Method and system for controlling unibus equipment |
| CN102681962A (en) * | 2012-04-18 | 2012-09-19 | 华为技术有限公司 | Connecting device and anti-jamming system between node devices |
| CN202773029U (en) * | 2012-09-19 | 2013-03-06 | 广东安居宝数码科技股份有限公司 | Single data bus transmitting and receiving circuit |
| CN103823776A (en) * | 2014-02-28 | 2014-05-28 | 上海晟矽微电子股份有限公司 | Unibus in communication with master equipment and slave equipment and communication method |
-
2018
- 2018-03-01 CN CN201810171880.7A patent/CN108536629B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4805137A (en) * | 1987-01-08 | 1989-02-14 | United Technologies Corporation | Bus controller command block processing system |
| CN101373968A (en) * | 2007-08-21 | 2009-02-25 | 艾默龙电子科技（嘉兴）有限公司 | Uni-bus interactive synchronization technology as well as application for integrated circuit thereof |
| CN101404556A (en) * | 2008-10-24 | 2009-04-08 | 伊玛精密电子（苏州）有限公司 | One-wire bus communication method |
| CN101727422A (en) * | 2008-10-29 | 2010-06-09 | 大唐移动通信设备有限公司 | Method and system for controlling unibus equipment |
| CN102681962A (en) * | 2012-04-18 | 2012-09-19 | 华为技术有限公司 | Connecting device and anti-jamming system between node devices |
| CN202773029U (en) * | 2012-09-19 | 2013-03-06 | 广东安居宝数码科技股份有限公司 | Single data bus transmitting and receiving circuit |
| CN103823776A (en) * | 2014-02-28 | 2014-05-28 | 上海晟矽微电子股份有限公司 | Unibus in communication with master equipment and slave equipment and communication method |
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Denomination of invention: A communication method of single bus multiple and or logic transceiver circuit Effective date of registration: 20220712 Granted publication date: 20210202 Pledgee: Industrial and Commercial Bank of China Limited Foshan Shiwan sub branch Pledgor: AEROSPACE BAYKEE (GUANGDONG) TECHNOLOGY Co.,Ltd. Registration number: Y2022980010313 |
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