CN101373968A - Uni-bus interactive synchronization technology as well as application for integrated circuit thereof - Google Patents
Uni-bus interactive synchronization technology as well as application for integrated circuit thereof Download PDFInfo
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- CN101373968A CN101373968A CNA200710045093XA CN200710045093A CN101373968A CN 101373968 A CN101373968 A CN 101373968A CN A200710045093X A CNA200710045093X A CN A200710045093XA CN 200710045093 A CN200710045093 A CN 200710045093A CN 101373968 A CN101373968 A CN 101373968A
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Abstract
The invention provides a single-wire interactive synchronization technology and a design proposal of applying the technology in integrated circuit design. The invention provides a unique signal transmission method and a signal synchronous circuit design proposal realized by using the method. The signal transmission method can transmit both output signals and input signals by using one transmission line, so as to use one synchronization port in the multiple circuit signal synchronous design. An interactive synchronous operation is realized, and a master-slave mode synchronous control can also be easily realized by using the same single-terminal connecting manner. In particular, during being used in the integrated circuit design, the proposal can realize excellent operating performance of the synchronous circuit by using the minimal pins. Except being used in design of the signal synchronous circuit, the inventive proposal also has a certain use value in other circuit designs.
Description
Background introduction
Field that the present invention belongs to
[0001]
The invention belongs to an innovation in electronic technology field.It provides a kind of Frequency Synchronization and phase locked notion of uniqueness.Make a plurality of electronic circuits can use same monobus.Both can be used as the receiving terminal of synchronizing signal, also can be used as the output of synchronizing signal, thereby realized both simple economies, reliable and practical again simultaneous operation.This technology can not only realize that signal frequency is synchronous, also can realize the synchronous of phase place.Can be widely used in multiple fields such as electronic signal process, control and Power Conversion.
Relevant field is described
[0002]
In numerous different application of electronic technology fields, electronic circuit often need be worked under certain frequency.And in many cases, this operating frequency needs and a certain specific Frequency Synchronization is got up.Especially when a plurality of electronic circuits need co-ordination, the operating frequency of each electronic circuit, sometimes even comprise that signal phase all needs synchronously.So signal Synchronization is very important technology in the electronic technology field.
[0003]
Because its importance, people are just carrying out deep research to simultaneous techniques a long time ago.Also produced simultaneously the simultaneous techniques of some comparative maturities.These typical technology such as Fig. 1, Fig. 2 and shown in Figure 3.
[0004]
Figure 1 shows that a kind of PHASE-LOCKED LOOP PLL TECHNIQUE of classics.As shown in the figure, synchronizing signal VA and generally need be the square-wave signal of 50% duty ratio by synchronizing signal VB.The sequence Vo of formed output pulse has comprised this two phase difference between signals after two comparisons of signal by XOR gate U1.When two signal phase differences are big more, the high level duty ratio of output signal is just big more.This signal becomes the direct current signal that is directly proportional with signal phase difference after passing through the low pass filter filtering of being made up of R and C1.This gives voltage-controlled oscillator circuit VC0 after amplifier U2 handles control input end.The frequency of oscillation of voltage-controlled oscillator circuit is changed by the adjusting of input control voltage.Therefore controlled frequency signal VB and synchronizing signal VA are compared, go to regulate the controlled signal frequency with comparison error signal then and make it to follow synchronizing signal, just formed a frequency closed-loop control system.Thereby realized the signal Synchronization operation.Usually because the gain of VC0 is limited, need utilize U2 to form an integral element.Make two phase difference between signals approach zero like this and acquisition high precision synchronous effect.The used electronic devices and components of this technology are more, and when being applied in this technology in the integrated circuit circuit design, need three pins to finish this function at least.These three pins are respectively signal end A, the terminals of signal end B and low-pass filtering capacitor C 1.Because the C1 capacitance is bigger usually, can not be made in the integrated circuit the inside.
[0005]
Circuit shown in Figure 2 comes forced oscillator to follow synchronous signal frequency by the control that directly discharges and recharges to oscillating capacitance.When not having synchronizing signal VA, switch Q2 turn-offs.The oscillator of being made up of current source I, capacitor C, Q1, U1, U2, U3 is in free operating state.When C was charged to V2, U1 output was uprised by low, and trigger U3 is resetted.Its anti-phase output/Q makes discharge switch Q1 conducting by after hanging down high jump, and capacitor C is discharged rapidly.When capacitor C was discharged to V1, U2 output was uprised by low.Allow U3 set./ Q is by high level rebound low level state, and Q1 turn-offs thereupon, and capacitor C is recovered charging process.Go round and begin again like this and just formed continuous sawtooth waveforms vibration.When the input of external synchronizing signal, in Fig. 2 (a), the derivative action of the rising edge of synchronizing signal A by capacitor C 1 and resistance R produces a rising pulse B and makes discharge switch Q3 moment conducting, and C discharges to oscillating capacitance.After differentiated pulse disappeared, C recovered charging again.The discharging time of capacitor C is subjected to the direct control of synchronizing signal VA like this, thereby realizes synchronously.Such way exists following shortcoming:
(1), synchronizing signal will be higher than the frequency of free oscillation device, before capacitor C is charged to V2, it is discharged guaranteeing.Otherwise can't realize synchronously.
(2), the width of differentiated pulse need control suitably, if the too narrow C that can not make fully discharges, then may lose synchronous effect.
(3), U3 can not get reset operation.If there is subsequent conditioning circuit need use the Q of U3 ,/Q exports as clock or phase signal, has problem.
(4), during designing integrated circuit, need at least two pins.Control output pin as synchronizing signal.Input pin as synchronizing signal.Could realize between two chips like this or the simultaneous operation between the multicore sheet.Circuit shown in Fig. 2 (b) is slightly different with circuit shown in Fig. 2 (a).The trailing edge that this circuit utilizes synchronizing signal A makes P type M0S pipe Q2 moment conducting by the derivative action of RC1, the voltage of capacitor C is forced move the V2 level to.Can make U1 output forward high level to and allow U3 reset like this, the Q1 conducting, thus make oscillating circuit when following synchronizing signal, finish the overall process of vibration.The advantage of this scheme is (3) the individual problem that does not have Fig. 2 a listed.But the width of differentiated pulse B needs stricter control.Too wide meeting causes Q1 and Q2 that conducting simultaneously moment is arranged, thereby causes excess loss.
[0006]
Synchrolock shown in Figure 3 improves to some extent than Fig. 2.Synchronizing signal VA directly controls the U3 reset operation, and arriving at the rising edge of VA is, U3 resets, and/Q is uprised by low, Q1 conducting, capacitor C discharge.When capacitor C was discharged to V1, U2 exported with regard to high jump, makes U3 set, so electric capacity recovers charging.The operation of this method can, need not consider the problem of differential pulse width control.But require the free oscillation frequency of controlled circuit to be lower than synchronizing frequency equally.When integrated circuit (IC) design, each chip needs at least two pins simultaneously.One gives as synchronizing signal output, and another is imported as synchronizing signal, realizes the simultaneous operation between two chips or the multicore sheet.
Description of drawings
[0007]
Shown in Figure 1ly be one and typically utilize phase-locked loop to realize synchronous circuit arrangement.Explanation of symbols is among the figure:
The external synchronous signal input end of A-
B-is by the synchronizing signal end
The external synchronizing signal of VA-
VB-is by synchronizing signal
Vo-XOR gate output signal
[0008]
Fig. 2 (a) is depicted as another kind of synchronous circuit.This circuit utilization realizes the oscillating capacitance forced discharge by C1, R and Q2 at the rising edge of the synchronizing signal of A end input synchronously.
[0009]
Fig. 2 (b) is depicted as and the similar another kind of synchronous circuit of Fig. 2 (a).This circuit utilizes the synchronizing signal trailing edge of A end input to draw high the voltage of oscillating capacitance C and forces trigger U3 upset and realize synchronously.
[0010]
Fig. 3 is another kind of synchronous circuit.Synchronizing signal is directly carried out reset operation to U3 and is realized synchronous by the input of A end among the figure.The A end is synchronous signal input end among the figure, and the B end is synchronous signal output end.
[0011]
Fig. 4 is a typical conceptual schematic view of the present invention.Node A holds synchronously among the figure, has both made the synchronizing signal receiving terminal, also as synchronous signal output end.Thereby realize that the multiple output circuit uni-bus interactive is synchronous.
[0012]
Fig. 5 has described and has utilized this notion to realize that circuit synchronous between two circuit connects and work wave.Situation shown in the figure is the operating frequency that the free operating frequency of left side circuit is higher than the right circuit.
[0013]
Figure 6 shows that the mutation that utilizes notion of the present invention to realize synchronous several different circuit.
[0014]
Figure 7 shows that the wiring when oscillating circuit and extraneous signal are synchronous.
The detailed description of invention
[0015]
In analysis, the present invention proposes a kind of synchronization concept of uni-bus interactive to above-mentioned various synchrolocks.Figure 4 shows that a typical concept principle figure.U3 is the part of oscillating circuit among the figure.Node B is the output of oscillator.Node A both had been single-ended synchronous port.In use, when two or more such circuit need when synchronous, can realize simultaneous operation as long as this port of all each circuit linked together.Its principle is as follows:
[0016]
Q2, Q3 and R form the signal port of a low electric Logic Priority.This specific character is to be realized by the resistance R of being connected between Q2 and Q3.When port A did not have outer signal, the state of this port also was the state variation of Node B with the gate pole input of Q2, Q3.Also promptly when B is high level, A is a low level.Otherwise when B was low level, A was a high level.Notice that at this moment the high level of port A is to draw on carrying out by the conducting of Q2 and by resistance R to realize.In this case, if the impedance of resistance R is enough high, when A end had an external low level signal, its level was promptly dragged down by extraneous signal.The value of resistance R is decided by the current strength of extraneous signal.In principle as long as the pull-down current of extraneous signal is enough to and can produces the voltage drop that is equal to Vcc by resistance R.Under this principle, resistance R is can value big, to lower power consumption.
[0017]
As shown in Figure 4, the input that the A point is received NOR gate U4, another input of U4 is received Node B, also is the Q output of trigger U3.The output of U4 is then received the set input of U3.Like this when A point and B point current potential simultaneously when low, NOR gate U4 will export a high level signal.Make U3 set.
[0018]
If two identical circuit, such as two same A ends of the integrated circuit of foregoing circuit that adopt couple together.As shown in Figure 5, the frequency of oscillation of these two circuit will be got up automatically synchronously.Its operation principle is as follows:
Under the situation that A holds and A ' termination is logical, no matter be that B point or B ' point are in high level, common port A-A ' can be drawn to be low level.To the right circuit, if at this moment the B dotted state is a high level, then the low level state of A-A ' end is produced by B.And U3 at this moment has been in SM set mode. at this moment the B that is input as of NOR gate U4 blocks.Otherwise no asserts signal is input to the set input of U3., if the B point is a low level, then the low level state of A-A ' end is caused by the electric high potential state of B '.Also promptly at this moment U3 ' entered SM set mode.To the right circuit, the B point is an electronegative potential, and U3 is in reset mode.Because B point and A point are all electronegative potential, U4 will export a high potential signal and make U3 set like this.The general effect of whole process draws common port A-A ' to be low level exactly when U3 ' is SM set mode by reset mode upset.If at this moment the right circuit U 3 is in reset mode, then U4 can produce a set pulse and makes U3 follow U3 ' to enter SM set mode.Vice versa, if U3 is introduced into SM set mode, then also can makes U3 ' follow U3 by same process and enter SM set mode.After U3 and U3 ' almost entered SM set mode simultaneously, two oscillating circuits in left and right both sides began next cycle of oscillation simultaneously like this.That higher circuit of frequency of oscillation will be introduced into SM set mode again, and the signal that passes through A-A ' end connects and makes that lower circuit of frequency follow it to enter SM set mode simultaneously.Reach synchronous effect thereby go round and begin again.
Waveform shown in Fig. 5 is that the free operating frequency of left side circuit is higher than the right circuit.
[0019]
Here should be noted that in above-mentioned synchronizing process two circuit are not only frequency and have been reached synchronously, it is synchronous that its phase place has also reached.Strictly say owing to have a little phase difference between two circuit of propagation time delay of signal circuit.This phase difference that propagation time delay caused by signal circuit is not under operating frequency is very high situation, and for example the hundreds of kilohertz can be ignored basically.
[0020]
Above-mentioned principle also can extend to the simultaneous operation of a plurality of circuit.When need equally also can to link together the A of all each circuit end when synchronous more than two circuit.At this moment that the highest circuit of free frequency can become main circuit automatically.Make every other circuit all follow it frequency and synchronously.What at this moment should be noted that a bit is the fan out capability of circuit.The ability that also is the pull-down current of Q3 will be enough to bear the total current that a plurality of resistance R parallel connections are produced.And A end moved to low level.
[0021]
Resistance R also can replace with current source in foregoing circuit.Physical circuit is shown in Fig. 6 (a), and asserts signal also can realize with different logical circuits.Fig. 6 (b) is depicted as another kind of logical circuit.Port A also can be designed as and draws priority circuit.Shown in Fig. 6 (c).Q2, Q3 also can adopt the device and the circuit of other kind.Fig. 6 (d) is depicted as the circuit that adopts bipolar transistor.The core of this invention is the synchronous circuit interface that single-point is in parallel and have the certain logic priority.The sort circuit interface is both as signal output part, also as signal input part.Thereby realize the multicircuit simultaneous operation that monobus connects.Here it may be noted that also that sort circuit can not only realize the simultaneous operation between the multicircuit, also can accept external synchronizing signal and realize and the simultaneous operation of extraneous signal.Shown in Figure 7ly be two circuit and accept the synchronous example of same extraneous signal simultaneously.The frequency that it should be noted that extraneous signal also needs to be higher than the free operating frequency of accepting circuit synchronously.
Summary of the present invention
[0021]
The present invention proposes a kind of synchronous circuit design of uniqueness.This scheme is only used a Synchronization Control end, both as synchronous signal output end, also as synchronous signal input end.When organizing circuit simultaneous operation, only need link together the Synchronization Control end of each circuit more, promptly form a synchronous bus, the operating frequency of each circuit can automatically be synchronized with the highest circuit of free operating frequency.This scheme also has the Phase synchronization function except can synchronous working the frequency, for synchronous circuit design provide one simple, reliably and the scheme of function admirable.Especially in integrated circuit was used, this scheme can make integrated circuit (IC) design use single pin, realizes the Synchronization Control of perfect in shape and function.Thereby for the Synchronization Design of integrated circuit provides a low cost, high performance solution.
Claims (1)
1. 1), the single-ended Synchronization Control of use proposed by the invention is brought in and is realized multicircuit simultaneous operation.This single-ended Synchronization Control end also can be used as synchronous signal output end both as synchronous signal input end.In use, as long as the Synchronization Control end of each circuit is linked together, form a single synchronous bus, the operating frequency of each circuit will be coordinated mutually by this root synchronous bus, automatically gets up synchronously.
2), the single-ended connected mode with Logic Priority right to choose of synchronizing signal.This mode can be that positive logic is preferential, also can be that negative logic is preferential.During use, as long as all holding wires are linked together.If positive logic is preferential, high level signal Control Node state then.If negative logic is preferential, low level signal Control Node state then.This scheme also can be applied to other signal application field except being used for synchronizing signal.
3), signal under single node connects automatic principal and subordinate and follow function automatically.Under this function, in any moment, when its signal that has Logic Priority to weigh occurred, other signal that is in non-priority logic state can automatically be followed the priority logic conversion of signals that occurs at first by the control circuit of self and be arrived the priority logic state.Also promptly follow the priority logic state that self occurs early than it automatically.
4), having 2) and 3) point described function signal directly link together.As long as there is a signal to enter the logic state with priority, other signal can be followed automatically and be entered same logic state together.If these signals are the alternating signals with free oscillation function, these signals will be followed the highest signal Synchronization vibration of free oscillation frequency.Thereby realized utilizing the signal frequency simultaneous operation of the interactive signal method of attachment of this single node.
5), 1), 2), 3) and 4) signal frequency synchronization concept described in the point, also can be used for the phase place of synchronizing signal.
6), 2) described in the signal end with priority logic right to choose, the output of each signal can be shown in Fig. 4 to Fig. 7 by Q2, Q3 and resistance R, or the circuit of forming by Q2, Q3 and current source.Q2 and Q3 can be MOSFET, also can be bipolar transistors, or the controllable electronic switch of other type.Q2 and the Q3 connection in circuit is except drain electrode (or collector electrode) be together in series with resistance R (or current source I), the mode that also can adopt source electrode (or emitter) and resistance R (or current source I) to be together in series.When adopting this connected mode, the gate pole of Q2, Q3 (or base stage) control signal correspondingly adopts opposite polarity.Above-mentioned pair transistor output circuit also can change the single-transistor circuit form into.When adopting single-transistor, if negative logic is preferential, transistor adopts N type MOSFET or bipolar npn transistor npn npn and its source electrode (or emitter) and working power negative terminal or ground is held and is connected.Its drain electrode (or collector electrode) then is connected to the working power anode by resistance (or current source).Signal is from drain electrode (or collector electrode) output.If positive logic is preferential, transistor is placed on the upside of circuit, adopts P type MOSFET or bipolar npn transistor npn npn, and its source electrode (or emitter) connects the working power positive pole.Drain electrode (or collector electrode) is received working power negative pole or ground end by resistance or current source, and signal is still from drain electrode (or collector electrode) output.Various circuit connecting modes described above all can be realized same simultaneous operation effect.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710045093XA CN101373968A (en) | 2007-08-21 | 2007-08-21 | Uni-bus interactive synchronization technology as well as application for integrated circuit thereof |
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| CNA200710045093XA CN101373968A (en) | 2007-08-21 | 2007-08-21 | Uni-bus interactive synchronization technology as well as application for integrated circuit thereof |
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| CN101373968A true CN101373968A (en) | 2009-02-25 |
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| CNA200710045093XA Pending CN101373968A (en) | 2007-08-21 | 2007-08-21 | Uni-bus interactive synchronization technology as well as application for integrated circuit thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108536629A (en) * | 2018-03-01 | 2018-09-14 | 航天柏克(广东)科技有限公司 | A kind of monobus mostly with or logic transmission circuit communication system and method |
-
2007
- 2007-08-21 CN CNA200710045093XA patent/CN101373968A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108536629A (en) * | 2018-03-01 | 2018-09-14 | 航天柏克(广东)科技有限公司 | A kind of monobus mostly with or logic transmission circuit communication system and method |
| CN108536629B (en) * | 2018-03-01 | 2021-02-02 | 航天柏克(广东)科技有限公司 | Communication method of single-bus multi-AND or logic transceiving circuit |
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Open date: 20090225 |