CN108170617B - I3C equipment and communication method - Google Patents

I3C equipment and communication method Download PDF

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Publication number
CN108170617B
CN108170617B CN201711250185.1A CN201711250185A CN108170617B CN 108170617 B CN108170617 B CN 108170617B CN 201711250185 A CN201711250185 A CN 201711250185A CN 108170617 B CN108170617 B CN 108170617B
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slave
address
bus
master device
master
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CN108170617A (en
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王常慧
贾瑞华
赵方亮
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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Guangdong High Cloud Semiconductor Technologies Ltd Co
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention relates to the technical field of integrated circuit IP core design, and provides I3C equipment and a communication method; an I3C device comprising: at the user end, the user terminal, the I3C master device and the slave device, the slave device comprises an I2C slave device and/or an I3C slave device, the I3C master device is connected with the I2C slave device through an I3C bus, the I3C slave device is connected with the I3C master device through an I3C bus, a user end is used for sending a control command stream to the I3C master device and receiving a feedback signal fed back by the I3C master device, the I3C master device is used for receiving the control command stream and resolving the control command stream into a bus control signal to be sent to the I3C bus, the I2C slave device is used for receiving the bus control signal corresponding to an I2C special address on the I3C bus and receiving data sent by the I843 master device, and the I3C slave device is used for receiving the bus control signal corresponding to an I3 867 address on the I3C bus and receiving data sent by the I3C master device, and the I3C device and the method provided by the invention can make the I3C slave device and the slave device maintain the advantage of high I3C rate C and I3 slave device C compatible.

Description

I3C equipment and communication method
Technical Field
the invention belongs to the technical field of integrated circuit IP core design, and particularly relates to I3C equipment and a communication method.
Background
An Intellectual Property Core (IP Core for short) refers to a chip design module provided by a certain party. Designers can design the logic of an application specific integrated circuit or a Field Programmable Gate Array (FPGA for short) based on an IP core to shorten the design period and improve the design quality and efficiency.
According to the new standard specification of I3C of the Mobile Industry Processor port (MIPI) alliance, I3C is a new Interface standard for improving the characteristics of I2C, and supports backward compatibility, allowing the I2C slave device to coexist with a new device supporting the I3C specification of the MIPI alliance, and the I3C master device can communicate with the I2C slave device in the Fast Mode (FM) and the fast mode + (FM +) rate. However, if the I3C master device is to communicate with the I2C slave device, if the pure legacy mode is adopted to operate as the I2C bus, it will not be able to utilize any advantages of the I3C specification characteristics, and at the same time, the logic complexity and power consumption of the I3C interface will become large.
in summary, the conventional I3C apparatus and method cannot achieve the advantages of the I3C specification when the I3C master is compatible with the I2C slave and communicate with the I3C slave at high data rates.
disclosure of Invention
The present invention provides an I3C device and a method thereof, so as to solve the problem that when an I3C device and an I2C device coexist in the prior art, the I3C device cannot retain the advantages of high data rate, and the like.
the invention is realized by the following steps:
The invention provides an I3C device, wherein the I3C device comprises a user end, an I3C master device and a slave device, and the slave device comprises an I2C slave device and/or an I3C slave device; the I3C master device is connected with the I2C slave device through an I3C bus, and the I3C slave device is connected with the I3C master device through an I3C bus;
specifically, the user side is configured to send a control command stream to an I3C master device, and receive a feedback signal fed back by the I3C master device; the I3C master device is used for receiving the control command stream, resolving the control command stream into a bus control signal and sending the bus control signal to an I3C bus; the control command stream comprises slave addresses which are I3C addresses and/or I2C private addresses; the I2C slave device is configured to receive a bus control signal corresponding to the I2C private address on the I3C bus, and receive data sent by the I3C master device according to the bus control signal of the I2C private address, or send data to the I3C master device according to the bus control signal of the I2C private address; the I3C slave device is configured to receive a bus control signal corresponding to the I3C address on the I3C bus, and receive data sent by the I3C master device according to the bus control signal of the I3C address, or send data to the I3C master device according to the bus control signal of the I3C address.
The I3C device provided in the embodiment of the present invention implements communication between an I2C slave device or an I3C slave device and an I3C master device through an I3C bus, configures an I2C slave device-specific address on an I3C bus, and the I3C master device receives a control command stream transmitted by a user side and parses a slave address in the control command stream, and the I3C master device distinguishes whether a communication object is an I3C slave device or an I2C slave device through the slave address, and adjusts a clock frequency according to different requirements of the user, thereby meeting different functional requirements, so that when the I3C master device is compatible with the I2C slave device, the advantage of the I3C specification can be retained to communicate with the I3C slave device at a high data rate.
A second aspect of the present invention provides a communication method for an I3C device, the method comprising the steps of:
Step S10: the user side sends a control command stream to an I3C master device and receives a feedback signal fed back by the I3C master device;
Step S20: the I3C master device receives the control command stream, resolves the control command stream into bus control signals and sends the bus control signals to an I3C bus; the control command stream comprises slave addresses which are I3C addresses and/or I2C private addresses;
step S30: the I3C master device judges whether the slave address is the address special for the I2C slave device, if yes, the step S40 is executed, and if not, the step S50 is executed;
step S40: the I2C slave device receives a bus control signal corresponding to the I2C special address on the I3C bus, and receives data sent by the I3C master device according to the bus control signal of the I2C special address, or sends data to the I3C master device according to the bus control signal of the I2C special address;
Step S50: the I3C slave device receives a bus control signal corresponding to the I3C address on the I3C bus, and receives data sent by the I3C master device according to the bus control signal of the I3C address, or sends data to the I3C master device according to the bus control signal of the I3C address.
according to the communication method of the I3C device, a user side sends a control command stream to an I3C master device, the I3C master device receives the control command stream sent by the user side and analyzes a slave address in the control command stream, whether the slave address belongs to an I2C slave device special address is judged, if yes, the I3C master device adjusts a clock frequency corresponding to the I2C slave device and performs read-write operation on the I2C slave device according to an I2C protocol, otherwise, the I3C master device adjusts the clock frequency corresponding to the I3C slave device and performs read-write operation on the I3C slave device according to an I3C protocol, so that the I3C master device can keep the advantages of an I3C specification and simultaneously communicates with the I3C slave device at a high data rate when being compatible with the I2C slave device.
drawings
in order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an I3C device according to an embodiment of the present invention;
Fig. 2 is a communication flow diagram of a communication method of the I3C device according to an embodiment of the present invention;
fig. 3 is a flowchart of an I2C slave device receiving data transmitted by an I3C master device of a communication method of an I3C device according to an embodiment of the present invention;
Fig. 4 is a flowchart of an I2C slave device transmitting data to an I3C master device according to a communication method of an I3C device provided in an embodiment of the present invention;
fig. 5 is a flowchart of an I3C slave device receiving data transmitted by an I3C master device of a communication method of an I3C device according to an embodiment of the present invention;
Fig. 6 is a flowchart of an I3C slave device transmitting data to an I3C master device according to a communication method of an I3C device provided in an embodiment of the present invention.
wherein, 100-user terminal; 200-I3C master device; 300-a slave device; 301-I2C slave devices; 302-I3C slave device.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 shows a schematic structural diagram of an I3C device provided in an embodiment of the present invention, and for convenience of description, only the parts related to this embodiment are shown, and detailed descriptions are as follows:
the I3C device includes a user end 100, an I3C master device 200, and a slave device 300, and the slave device 300 includes an I2C slave device 301 and/or an I3C slave device 302.
the I3C master device 200 is connected to the I2C slave device 301 through an I3C bus, and the I3C slave device 302 is connected to the I3C master device 200 through an I3C bus.
Specifically, the user end 100 is configured to send a control command stream to the I3C master device 200, and receive a feedback signal fed back by the I3C master device 200.
specifically, the I3C master device 200 is configured to receive a control command stream, parse the control command stream into bus control signals, and send the bus control signals to the I3C bus; the control command stream comprises slave addresses, wherein the slave addresses are I3C addresses and/or I2C private addresses.
specifically, the I2C slave device 301 is configured to receive a bus control signal corresponding to the I2C specific address on the I3C bus, and receive data sent by the I3C master device 200 according to the bus control signal corresponding to the I2C specific address, or send data to the I3C master device 200 according to the bus control signal corresponding to the I2C specific address;
Specifically, the I3C slave device 302 is configured to receive a bus control signal corresponding to an I3C address on the I3C bus, and receive data sent by the I3C master device 200 according to the bus control signal corresponding to the I3C address, or send data to the I3C master device 200 according to the bus control signal corresponding to the I3C address.
In this embodiment, the I3C host 200 may include an input module, an analysis module, and an I3C circuit port module; the input module is used for receiving the control command stream and transmitting the control command stream to the analysis module; the analysis module is used for analyzing the slave addresses in the control command stream and transmitting the slave addresses to the I3C circuit port module; the I3C circuit port module is used to receive the slave address that has been resolved and transmit it to the slave device 300 via the I3C bus, so as to perform read/write operations on the slave device 300.
as an implementation manner, in the present invention, the I3C master device 200 has an I3C interface, and can implement an I3C bus protocol, the I3C bus protocol is a completely new protocol standard, and can effectively reduce the physical ports of the integrated device, and support the advantages of low power consumption, high data rate, and other existing port protocols, the I3C bus protocol specification accommodates the key characteristics of I2C and SPI, has low pin count, scalability, low power consumption, higher capacity, and new performance, and is compatible with I2C, allowing the I2C slave device 301 to coexist with new devices of the I3C bus protocol specification on the same port.
As an embodiment, in the present invention, the slave device 300 is a circuit using a hardware description language, and is connected to the I3C bus through an I3C bus port, the slave device 300 can implement communication with the I3C master device 200 through an I3C bus, and when the slave device 300 performs data communication with the I3C master device 200, it can receive a read-write command and a read-write operation sent by the I3C master device 200 to the I3C bus, and perform corresponding feedback according to the read-write command and the read-write operation, so as to perform data communication. For example, the hardware description language may be a circuit described by verilog hdl, VHDL language, which are both a kind of hardware description language.
As an embodiment, in the present invention, the slave device 300 may be an I3C slave device 302, and the I3C slave device 302 adopts an I3C serial communication protocol, which absorbs and unifies the key characteristics of I2C and SPI, reduces the number of pins, increases scalability, and rapidly transmits batch data, and achieves the maximum data rate of many application devices required by a user, and meanwhile, the I3C slave device 302 can initiate START under standard I/O, actively transmit data to the I3C master device 200, and join in an existing application system at any time, and achieve communication with the application system master controller.
as an embodiment, in the present invention, the slave device 300 may be the I2C slave device 301, and in order to achieve the advantage of preserving the I3C bus protocol specification while being compatible with the I2C slave device 301 to communicate with the I3C slave device 302 at a high data rate, the I2C slave device 301 is configured with an I2C slave device 301 specific address, which is an address assigned to the I2C slave device 301 only.
As an embodiment, in the present invention, the slave device 300 may include an I2C slave device 301 and an I3C slave device 302.
it should be noted that, in this embodiment, the I3C master device 200 determines whether the current communication object is the I3C slave device 302 or the I2C slave device 301 through the private address, if the current communication object is the I2C slave device 301, the I3C master device 200 adjusts the clock frequency corresponding to the I2C slave device 301, and performs a read-write operation on the I2C slave device 301 in the I2C protocol manner, and if not, the I3C master device 200 adjusts the clock frequency corresponding to the I3C slave device 302, and performs a read-write operation on the I3C slave device 302 in the I3C protocol manner.
as an embodiment, in the present invention, the I3C slave device 302 further includes an I3C slave device 302 that is newly added to the I3C bus by hot-accessing, the I3C master device 200 avoids the address specific to the I2C slave device 301, and assigns an address to the I3C slave device 302 that is newly added to the I3C bus according to a dynamic address assignment mechanism, the hot-accessing means that after the I3C bus is configured, the I3C slave device 302 can be added to the I3C bus at any time, and the I3C master device 200 assigns a dynamic address to the I3C slave device 302.
As an embodiment, in the present invention, the specific unit in the slave device 300 may be an internet sensor, a wearable device, a medical instrument, a sensor in a mobile device and an automobile system, and the like.
The I3C device provided in the embodiment of the present invention realizes coexistence of an I3C slave device and an I2C slave device on an I3C bus, configures an I2C slave device dedicated address on the I3C bus, and an I3C master device receives a control command stream transmitted by a user side and parses a slave address in the control command stream, and the I3C master device distinguishes whether a communication object is an I3C slave device or an I2C slave device by determining the slave address, and adjusts a clock frequency according to different requirements of the user, thereby meeting different functional requirements, so that when the I3C master device is compatible with the I2C slave device, the advantage of the I3C specification can be retained to perform communication with the I3C slave device at a high data rate.
fig. 2 shows a communication flow chart of a communication method of the I3C device provided in an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment are shown, which is detailed as follows:
the communication method of the I3C device comprises the following steps:
step S10: the user terminal 100 transmits a control command stream to the I3C master device 200 and receives a feedback signal fed back by the I3C master device 200.
step S20: the I3C master device 200 receives the control command stream and parses the control command stream into bus control signals to send to the I3C bus; the control command stream comprises slave addresses, wherein the slave addresses are I3C addresses and/or I2C private addresses.
in step S20, the I3C master device 200 receives the control command stream transmitted from the user end 100, parses the slave address in the control command stream, and transmits a slave address command to the slave device 300 through the I3C bus, and the I3C master device 200 transmits a read/write command to the slave device 300 to wait for the slave device 300 to transmit a feedback signal for acknowledgement when receiving a feedback signal for acknowledgement transmitted from the slave device 300 according to the slave address command or when receiving the control command stream transmitted from the user end 100.
As an embodiment, in the present invention, the I3C master device 200 includes an I3C interface, a control register, an interrupt module, a data buffer, a state machine, a start module, and an end module; the I3C interface is used for realizing the protocol of the I3C bus, the I3C bus is a bus supporting the I3C protocol, and the address or the read-write command sent by the I3C master device 200 is translated into an I3C bus signal according to the I3C bus protocol and sent to the slave device 300 under the I3C bus; the control register module is used for controlling and determining the operation mode and the characteristics of the current execution task; the interrupt module is used by the I3C master device 200 to process IBI requests applied by the slave device; the data buffer area is used for storing data sent by or read from the master device 200 of I3C; the state machine is used for displaying the state of the I3C master device 200 and the operation required by the I3C master device; the starting module is used for generating a starting condition of the equipment and then performing read-write operation; the ending module is used for generating an ending condition and ending the read-write operation.
step S30: the I3C master device 200 determines whether the slave address is the address specific to the I2C slave device 301, and if so, executes step S40, and if not, executes step S50.
Step S40: the I2C slave device 301 receives a bus control signal corresponding to an I2C-specific address on the I3C bus, and receives data transmitted from the I3C master device 200 according to the bus control signal of the I2C-specific address, or transmits data to the I3C master device 200 according to the bus control signal of the I2C-specific address
Further, as an embodiment, in the present invention, as shown in fig. 3, the step of receiving, by the I2C slave device 301, data sent by the I3C master device 200 specifically includes the following steps:
Step S401A: the client control I3C the master device 200 initiates a start command.
Step S402A: the client side controls the I3C master device 200 to send seven bits of slave addresses and one bit of write command 0, waiting for the I2C slave device 301 to send an acknowledge feedback signal.
Step S403A: the I2C slave device 301 receives the I2C private address and responds automatically to the I3C master device 200.
Step S404A: client control I3C the master 200 sends the register address of the I2C slave 301.
Step S405A: the user terminal 100 controls the I3C master device 200 to transmit data, and waits for the feedback signal of the I2C slave device 301 to transmit acknowledgement.
step S406A: I2C sends a feedback signal from device 302 acknowledging.
Step S407A: the steps S405A and S406A may be repeated a plurality of times and sequentially written to a plurality of registers.
step S408A: the I3C master device 200 sends an end signal.
Further, as an embodiment, in the present invention, as shown in fig. 4, the step of sending data from the I2C slave device 301 to the I3C master device 200 specifically includes the following steps:
step S401B: the user terminal 100 controls the I3C master device 200 to initiate a start command.
Step S402B: the user end 100 controls the I3C master device 200 to send seven-bit slave address and write command 0, and waits for the I2C slave device 301 to send a feedback signal confirming.
Step S403B: the I2C slave device 301 receives the I2C private address and responds automatically to the I3C master device 200.
Step S404B: the user end 100 controls the I3C master 200 to send the register address of the I2C slave 301.
Step S405B: the I3C master device 200 initiates a start command.
Step S406B: the I3C master 200 sends a seven bit slave address and one bit read command 1, waiting for the I2C slave 301 to send an acknowledge feedback signal.
step S407B: I2C sends a feedback signal from device 301 acknowledging.
Step S408B: the I3C master 200 reads the data stored in the I2C slave 301 registers.
step S409B: the user terminal 100 controls the I3C master device 200 to transmit a reply signal to the I2C slave device 301.
step 410B: repeating steps 408B and 409B may read multiple data in succession.
step 411B: the I3C master device 200 sends an end signal.
step S50: the I3C slave device 302 receives the bus control signal corresponding to the I3C address on the I3C bus, and receives the data sent by the I3C master device 200 according to the bus control signal of the I3C address, or sends the data to the I3C master device according to the bus control signal of the I3C address.
Further, as an embodiment, in the present invention, as shown in fig. 5, the step of receiving, by the slave device 302, the data sent by the master device 200 of I3C by the I3C specifically includes the following steps:
Step S501A: the user terminal 100 controls the I3C master device 200 to initiate a start command.
Step S502A: the user end 100 controls the I3C master device 200 to send seven bits of slave addresses and one bit of write command 0, waiting for the I3C slave device 302 to send the acknowledge feedback signal.
Step S503A: the I3C slave 302 detects the I3C address and automatically responds to the I3C master 200.
step S504A: the user end 100 controls the I3C master 200 to send the register address of the I3C slave 302.
Step S505A: the user terminal 100 controls the I3C master device 200 to transmit data, and waits for the feedback signal of the I3C slave device 302 to transmit acknowledgement.
step S506A: I3C sends a feedback signal from device 302 acknowledging.
Step S507A: the steps S505A and S506A may be repeated a plurality of times and sequentially written to a plurality of registers.
Step S508A: the I3C master device 200 sends an end signal.
Further, as an embodiment, in the present invention, as shown in fig. 6, the step of sending data from the I3C slave device 302 to the I3C master device 200 specifically includes the following steps:
step S501B: the user terminal 100 controls the I3C master device 200 to initiate a start command.
Step S502B: the user end 100 controls the I3C master device 200 to send seven bits of slave addresses and one bit of write command 0, waiting for the slave device to send an acknowledge feedback signal.
step S503B: the I3C slave device 302 automatically responds to the I3C master device 200.
Step S504B: the user end 100 controls the I3C master 200 to send the register address of the I3C slave 302.
step S505B: the I3C master device 200 initiates a start command.
Step S506B: the I3C master 200 sends a seven bit slave address and a one bit read command 1, waiting for the I3C slave 302 to send an acknowledge feedback signal.
Step S507B: I3C sends a feedback signal from device 302 acknowledging.
step S508B: the I3C master device 200 starts reading data at the register address written in step S504B.
Step S509B: the user terminal 100 controls the I3C master device 200 and the I3C slave device 302 to send whether to continue reading signals to each other, and if the I3C master device 200 stops sending the continue reading signals, the I3C master device 200 initiates an end command; if the I3C slave device 302 stops sending the continue read data signal, then the I3C slave device 302 ends the read operation.
It should be noted that, in this embodiment, parsing the control command stream into bus control signals and sending the bus control signals to the I3C bus includes:
And analyzing the control command stream to obtain an analysis result.
If the slave address included in the control command stream is the I2C dedicated address as a result of the analysis, the frequency of the I3C bus is adjusted to the first frequency, and a bus control signal of the I2C dedicated address is transmitted to the I2C slave 301 from the I3C bus after the frequency adjustment.
If the slave address included in the control command stream is the I3C address, the frequency of the I3C bus is adjusted to a second frequency, and a bus control signal of the I3C address is transmitted to the I3C slave device 302 according to the I3C bus after the frequency adjustment.
wherein the first frequency means that the I3C master device 200 adjusts the clock frequency corresponding to the I2C slave device 301 and the second frequency means that the I3C master device 200 adjusts the clock frequency corresponding to the I3C slave device 302.
It should be noted that, in this embodiment, the read/write operation of the I2C slave device 301 is different from the read/write operation of the I3C slave device 302, and taking the read operations of the two as an example, the I2C slave device 301 determines whether to transmit the next data according to the response signal of the I3C master device 200, and the I2C slave device 301 cannot actively end transmitting data, but for the I3C slave device 302, the I3C master device 200 determines whether to continue the read operation according to whether the I3C master device 200 continues to read information, and the I3C slave device 302 may determine whether to continue the read operation according to whether the I3C slave device 302 continues to read information.
According to the I3C equipment and the communication method provided by the invention, the I2C slave equipment special address is configured on the I3C bus, and the I3C master equipment can judge whether the current communication object is the I3C slave equipment or the I2C slave equipment through the I2C slave equipment special address, so that the working mode of the I3C master equipment is intelligently switched, a good and uniform interaction mechanism is established between a user and the I3C master equipment, the I2C slave equipment is compatible in an intelligent mode, the complexity of the user in operating the I3C bus slave equipment is simplified, new requirements of the I3C bus protocol on functions, speed and the like are met, the I3C can realize information transmission with higher speed, more flexibility and lower power consumption among integrated circuits, the flexibility of user design is improved, and the purposes of reducing power consumption, reducing physical interfaces, high-speed transmission and interconnection cost among integrated circuits are achieved.
the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (9)

1. An I3C device, wherein the I3C device comprises a user end, an I3C master device and a slave device, the slave device comprises an I2C slave device and/or an I3C slave device; the I3C master device is connected with the I2C slave device through an I3C bus, and the I3C slave device is connected with the I3C master device through an I3C bus;
The user side is used for sending a control command stream to the I3C master device and receiving a feedback signal fed back by the I3C master device;
The I3C master device is used for receiving the control command stream, resolving the control command stream into a bus control signal and sending the bus control signal to an I3C bus; the control command stream comprises slave addresses which are I3C addresses and/or I2C private addresses;
the parsing the control command stream into bus control signals and sending the bus control signals to the I3C bus comprises:
Analyzing the control command stream to obtain an analysis result;
If the analysis result is that the slave address contained in the control command stream is the I2C private address, adjusting the frequency of the I3C bus to a first frequency, and sending a bus control signal of the I2C private address to the I2C slave device according to the I3C bus after the frequency is adjusted;
if the analysis result is that the slave address contained in the control command stream is the I3C address, adjusting the frequency of the I3C bus to a second frequency, and sending a bus control signal of the I3C address to the I3C slave device according to the I3C bus after the frequency is adjusted;
the I2C slave device is configured to receive a bus control signal corresponding to the I2C private address on the I3C bus, and receive data sent by the I3C master device according to the bus control signal of the I2C private address, or send data to the I3C master device according to the bus control signal of the I2C private address;
the I3C slave device is configured to receive a bus control signal corresponding to the I3C address on the I3C bus, and receive data sent by the I3C master device according to the bus control signal of the I3C address, or send data to the I3C master device according to the bus control signal of the I3C address.
2. the I3C device of claim 1, wherein the I3C master device includes an input module, a parsing module, and an I3C circuit port module;
The input module is used for receiving the control command stream and transmitting the control command stream to the analysis module;
The analysis module is used for analyzing the slave address in the control command stream and transmitting the slave address to the I3C circuit port module;
The I3C circuit port module is configured to receive the slave address that has been resolved, and transmit the slave address to the slave device through an I3C bus, so that the I3C master device performs read/write operations on the slave device.
3. the I3C device of claim 1, wherein the I3C master determines whether a current communication partner is the I3C slave or the I2C slave by the private address.
4. The I3C device of claim 1, wherein the I3C slave device further comprises an I3C slave device that is newly joined to an I3C bus by hot-access, the I3C master device avoiding the I2C slave device-specific addresses, the I3C slave device being newly joined to an I3C bus being assigned addresses according to a dynamic address assignment mechanism.
5. A communication method based on the I3C device of any one of claims 1-4, wherein the communication method of the I3C device comprises the following steps:
Step S10: the user side sends a control command stream to an I3C master device and receives a feedback signal fed back by the I3C master device;
Step S20: the I3C master device receives the control command stream, resolves the control command stream into bus control signals and sends the bus control signals to an I3C bus; the control command stream comprises slave addresses which are I3C addresses and/or I2C private addresses;
Step S30: the I3C master device judges whether the slave address is the address special for the I2C slave device, if yes, the step S40 is executed, and if not, the step S50 is executed;
Step S40: the I2C slave device receives a bus control signal corresponding to the I2C special address on the I3C bus, and receives data sent by the I3C master device according to the bus control signal of the I2C special address, or sends data to the I3C master device according to the bus control signal of the I2C special address;
step S50: the I3C slave device receives a bus control signal corresponding to the I3C address on the I3C bus, and receives data sent by the I3C master device according to the bus control signal of the I3C address, or sends data to the I3C master device according to the bus control signal of the I3C address;
the parsing the control command stream into bus control signals and sending the bus control signals to the I3C bus comprises:
analyzing the control command stream to obtain an analysis result;
if the analysis result is that the slave address contained in the control command stream is the I2C private address, adjusting the frequency of the I3C bus to a first frequency, and sending a bus control signal of the I2C private address to the I2C slave device according to the I3C bus after the frequency is adjusted;
and if the analysis result shows that the slave address contained in the control command stream is the I3C address, adjusting the frequency of the I3C bus to a second frequency, and sending a bus control signal of the I3C address to the I3C slave device according to the I3C bus after the frequency is adjusted.
6. The communication method of the I3C device according to claim 5, wherein the step of "the I2C slave device receiving the bus control signal corresponding to the I2C specific address on the I3C bus, and receiving the data sent by the I3C master device according to the bus control signal corresponding to the I2C specific address" includes the following steps:
Step S401A: the user side controls the I3C master device to initiate a starting command;
step S402A: the user side controls the I3C master device to send a seven-bit slave address and a one-bit write operation command 0, and waits for the feedback signal of the confirmation sent by the I2C slave device;
Step S403A: the I2C slave device receiving the I2C private address and automatically responding to the I3C master device;
Step S404A: the user side controls the I3C master device to send the register address of the I2C slave device;
Step S405A: the user side controls the I3C master device to transmit data and waits for the feedback signal of the I2C slave device to transmit confirmation;
step S406A: the I2C slave device sends a feedback signal for confirmation;
step S407A: the steps S405A and S406A may be repeated a plurality of times and sequentially written into a plurality of registers
Step S408A: the I3C master sends an end signal.
7. the communication method of the I3C device according to claim 5, wherein the step of the I2C slave device receiving the bus control signal corresponding to the I2C specific address on the I3C bus and sending data to the I3C master device according to the bus control signal corresponding to the I2C specific address includes the steps of:
Step S401B: the user side controls the I3C master device to initiate a starting command;
Step S402B: the user side controls the I3C master device to send a seven-bit slave address and a one-bit write operation command 0, and waits for the feedback signal of the confirmation sent by the I2C slave device;
step S403B: the I2C slave device receiving the I2C private address and automatically responding to the I3C master device;
Step S404B: the user side controls the I3C master device to send the register address of the I2C slave device;
Step S405B: the I3C master initiating a start command;
Step S406B: the I3C master device sends seven bits of slave address and one bit of read operation instruction 1, waits for the I2C slave device to send an acknowledge feedback signal;
step S407B: the I2C slave device sends a feedback signal for confirmation;
step S408B: the I3C master reads the data stored in the I2C slave register;
Step S409B: the user side controls the I3C master device to send a response signal to the I2C slave device;
step 410B: repeating steps 408B and 409B may read multiple data in succession;
step 411B: the I3C master sends an end signal.
8. the communication method of the I3C device according to claim 5, wherein the step of "the I3C slave device receiving the bus control signal corresponding to the I3C address on the I3C bus, and receiving the data sent by the I3C master device according to the bus control signal corresponding to the I3C address" includes the following steps:
Step S501A: the user side controls the I3C master device to initiate a starting command;
step S502A: the user side controls the I3C master device to send a seven-bit slave address and a one-bit write operation command 0, and waits for the feedback signal of the confirmation sent by the I3C slave device;
Step S503A: the I3C slave detects the I3C address and automatically responds to the I3C master;
Step S504A: the user side controls the I3C master device to send the register address of the I3C slave device;
step S505A: the user side controls the I3C master device to send data and waits for the feedback signal of the I3C slave device to send confirmation;
step S506A: the I3C slave device sends a feedback signal for confirmation;
Step S507A: the steps S505A and S506A may be repeated a plurality of times and sequentially written into a plurality of registers;
Step S508A: the I3C master sends an end signal.
9. the communication method of the I3C device of claim 5, wherein the step of the I3C slave device receiving the bus control signal corresponding to the I3C address on the I3C bus and sending data to the I3C master device according to the bus control signal corresponding to the I3C address specifically includes the steps of:
step S501B: the user side controls the I3C master device to initiate a starting command;
step S502B: the user side controls the I3C master device to send a seven-bit slave address and a one-bit write operation instruction 0, and waits for the slave device to send a feedback signal for confirmation;
Step S503B: the I3C slave device automatically responding to the I3C master device;
step S504B: the user side controls the I3C master device to send the register address of the I3C slave device;
step S505B: the I3C master initiating a start command;
step S506B: the I3C master device sends seven bits of slave address and one bit of read operation instruction 1, waits for the I3C slave device to send an acknowledge feedback signal;
Step S507B: the I3C slave device sends a feedback signal for confirmation;
Step S508B: the I3C master starts reading data at the register address written in the step S504B;
Step S509B: the user side controls the I3C master device and the I3C slave device to respectively send a reading continuing signal to each other, and if the I3C master device stops sending the reading continuing signal, the I3C master device initiates an ending command; if the I3C slave stops sending the continue read data signal, the I3C slave ends the read operation.
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