CN1662008A - Communication method of half duplex serial bus with clock singal and communication system - Google Patents
Communication method of half duplex serial bus with clock singal and communication system Download PDFInfo
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Abstract
The system includes host, secondary computer, and serial communication bus. The bus includes four conducting wires: power source wire, common grounding wire, data wire and clock wire. Two ends of the serial bus are connected to terminal circuit respectively. Host and secondary computer through interface circuit are connected to the serial bus respectively. The communication method includes following steps: determining address number as unique id code of secondary computer in N pieces of communication secondary computers connected to shared type serial bus; according to frame structure, communication host sends and receives periodic exchange message to and from serial bus; based on corresponding id code in frame structure sent from host, each secondary computer exchanges data with host. Half-duplex mode is adopted in the invention. The host controls initiation and end of data communication as well as delay of periodic communication between nodes.
Description
[technical field]: the communication system and the method thereof that the present invention relates to a kind of back yard industry Control Network.
[background technology]: at present, in the back yard industry Control Network, RS-232, RS-422 and RS-485 standard are most widely used serial data interface standards, work out and issue by Electronic Industries Association (EIA), and be the industrial standard of serial data interface.
Rs-232 standard is the single-ended full-duplex communication mode that connects one to one, and the serial communication port on the computer is exactly this standard.
For improving the shortcoming that the RS-232 communication distance is short, speed is low, RS-422 has defined single worker, the balance transmission standard that a kind of unit sends, multimachine receives, and is named as the TIA/EIA-422-A standard.
Be the expanded application scope, EIA has formulated the RS-485 standard in nineteen eighty-three again on the RS-422 basis, increased multiple spot, two-way communications capabilities, promptly allows a plurality of transmitters to be connected on same the bus, uses the half-duplex operation mode.
Because the electrical characteristic of RS-232, RS-422 and a RS-485 standard docking port is made regulation, and does not relate to communication protocol, the user can set up the high-level communications protocol of oneself on this basis.
Brief analysis to RS-232, RS-422 and RS-485 standard:
1) universal serial bus includes only data wire in RS-232, RS-422 and the RS-485 standard, and the multinode on the bus adopts asynchronous system to finish synchronously, and the least unit of information transmitted can only be the ASCII character character of standard on bus.
2) in the RS485 standard, the number of nodes on the bus is conditional, and maximum 255, in actual use because of the restriction of aspects such as transmission range, transmission rate, the number of nodes on the bus also will lack usually.
3) in the RS485 standard, when main frame and certain slave communicate, send the address code of slave earlier, set up with slave between be connected and then transmission data.
4) in the RS485 standard, carry out one much more main from multinode between communication the time, if main frame mails to the data difference of each slave, main frame need be set up once respectively with each slave and be connected so, and then transmits data.Work as the slave number of nodes for a long time like this, main frame is communicated by letter the stand-by period with certain slave can be long, inapplicable to the occasion that time delay is strict.
5) in small-sized industrial control network, mostly what transmit on the bus is digitized control information, has or not temperature, the detected temperature value of flow sensor, flow value or the like such as the input signal near switch, limit switch.If these information convert the ASCII character of standard to and transmit, conversion and reduction process are very loaded down with trivial details.Therefore, the very not suitable this Industry Control occasion of RS485 STD bus.
By the analysis to RS-232, RS-422 and RS-485 standard, we can find to have following deficiency based on the communication system that this standard is set up:
1) the ascii character information of transmitting on the bus is not suitable for the transmission of the digital information in the Industry Control.
2) bus upper contact quantity more for a long time, the time of delay of communicating by letter between contact is long, and changes time of delay, the real-time of communication system is poor.
[summary of the invention]: The present invention be directed to the communication system of setting up based on the RS485 standard and have the transmission that is not suitable for the digital information in the Industry Control, the time of delay of communicating by letter between contact is long, the defective of the real-time difference of communication system, provide a kind of simple, efficient, the half duplex serial bus communication means that is fit to the band clock signal of digital information transmission in the back yard industry Control Network, and the communication system of using this method.
The half duplex serial bus communication means of band clock signal of the present invention may further comprise the steps:
---the shared formula universal serial bus that is identified for communicating by letter;
---determine to share each slave in N the slave of communicating by letter that inserts on the formula universal serial bus with address number as the unique identification code of slave, wherein N is an integer, and N 〉=1;
---on universal serial bus, send also receiving cycle sexual intercourse by communication host by frame structure and change information;
---each slave carries out exchanges data according to corresponding identification code and the main frame in the frame structure of main frame transmission;
---finish one time the communication cycle process.
Wherein the frame structure of main frame transmission comprises: sync section, functional section, data segment, ending segment;
---sync section: be the clock signal of logical value=1 of certain time, width setup is W1=a*T, and T is the reference signal cycle of bus timing, and a is an integer, and a 〉=1; Be used to represent the beginning of a communication cycle, send, be connected all slaves on the bus after detecting synchronizing signal, begin a new communication cycle by main frame;
---functional section: for the good bus line command of predefined, sent by main frame, all slaves all can receive and respond; The width setup of functional section is W2=b*T, and b is an integer, and b 〉=1, and what of the shared data bit of functional section spread factor b represent;
---data segment: be used to finish the exchanges data between main frame and the slave, comprise N sub-data segment, the address correspondence of each subdata Duan Yuyi slave, the maximum of communication slave number is N=2
n, n is the width of slave addresses sign indicating number;
Subdata section: comprise that main frame sends to c bit data and check digit two parts that the c bit data of slave and check digit and slave send to main frame;
The width W 3=2 of single subdata section (c+1) * T, c is an integer, and c 〉=1, integer c represents the data bits of each exchanges data between main frame and the slave;
---ending segment: the end of a communication cycle of expression, the clock signal of logical value=0 of sending by main frame, width W 5=d*T, d are integer, and d 〉=1;
A kind of half duplex serial bus communication system with clock signal, comprise main frame, slave, serial communication bus, serial communication bus comprises: power line, common ground, data wire and 4 leads of clock line, the serial communication bus two ends are the connecting terminal circuit respectively, and main frame and slave insert on the serial communication bus by interface circuit respectively.
Advantage of the present invention and good effect: 1) network configuration of this communication system is to share the formula universal serial bus, comprises clock signal and data-signal in the bus; 2) this communication system is made of a plurality of communication contact controllers; 3) there is and has only a communication host in this communication system; 4) one or more communication slaves can be arranged in this communication system, each slave has the identification code of unique address number as slave; 5) adopt between main frame and the slave in this communication system and have the synchronization of clock signals host-host protocol.6) this communication system adopts the data communication of half-duplex.7) initiation of the data communication in this communication system and end are by host computer control.8) communication on the bus is periodic, and the communication delay between contact is determined.9) in each communication cycle, main frame can with whole slave swap datas.10) information format of transmitting on the bus is binary zero, 1 bit stream.11) real-time of the binary data that transmits on the bus is guaranteed, is fit to the Industry Control needs.
[description of drawings]:
The half duplex serial bus communication system architecture schematic diagram of Fig. 1, band clock signal;
Fig. 2, frame structure schematic diagram;
Fig. 3, main-machine communication workflow diagram;
Fig. 4, function code transmission flow figure;
Fig. 5, main frame are carried out the data transmission and reception flow chart with each slave successively;
The workflow diagram of Fig. 6, subdata section;
Fig. 7, slave i communication work flow chart;
Fig. 8, slave receiving function sign indicating number flow chart;
The addressing process flow diagram of Fig. 9, slave i;
The flow chart of Figure 10, slave i and host exchanging data process;
Figure 11, serial bus interface circuit;
Figure 12, console controller schematic diagram;
Figure 13, slave controller principle figure.
Figure 14, slave external interface circuit figure;
Figure 15, the application block diagram of the present invention in the outside input/output signal of elevator.
[embodiment]:
Embodiment 1: the half duplex serial bus communication means of band clock signal:
Shown in Fig. 1～10, the present invention mainly sets forth the communication protocol of the data link layer of fieldbus, design principle for bottom physical layer hardware circuit does not have clear and definite regulation, promptly uses the personnel of this communication protocol can use diverse ways to realize the design of hardware circuit.
Same the present invention does not have clear and definite regulation to the agreement on upper strata, promptly uses the personnel of this communication protocol can come the implication of the data transmitted on the definition bus according to the situation that reality is used.
Communication system architecture of the present invention as shown in Figure 1, its communication means comprises:
The first, definition
(1) definition of serial bus signal:
The fundamental clock cycle: the reference signal of bus timing, its cycle is set at T, and stipulates that the preceding half period is a logical value 0, and the later half cycle is a logical value 1.
Comprise two pulse signals in the universal serial bus: clock signal and data-signal;
Clock signal: clock signal has two basic functions: produce the synchronizing signal of bus and the shift pulse of serial data.
The actual cycle of the clock signal on the bus changes, but its size is the integral multiple of fundamental clock period T.
Data-signal: the logical value of expression serial data is 1, or 0;
(2) definition of serial bus communication cycle (frame) structure:
Communication on the universal serial bus is periodically organized by (frame), sees Fig. 2.
Frame structure: sync section, functional section, data segment, ending segment.1) sync section: the clock signal of the logical value of certain time=1, its width setup are W1=a*T, (a is an integer, and a 〉=1).The beginning of a communication cycle of functional representation of sync section is sent by main frame, is connected all slaves on the bus after detecting synchronizing signal, and the serial data that resets shift counter C begins a new communication cycle.
2) functional section: some bus line commands that predefined is good, it is sent by main frame, and all slaves all can receive and respond.For example, the normal action command of slave, slave emergency stop command, slave reset command, slave test command or the like.
The width setup of functional section is W2=b*T, (b is an integer, and b 〉=1).What of the shared data bit of functional section are the size of spread factor b represented, just represented also that functional section institute can defined function how much.，
3) data segment: finish the exchanges data between main frame and the slave, comprise the experimental process data segment, the address correspondence of each subdata Duan Yuyi slave.
Subdata section: comprise that main frame sends to the c bit data of slave and c bit data and check digit two parts that the check bit sum slave sends to main frame.
The width W 3=of single subdata section ((c+1)+(c+1)) * T=2 (c+1) * T, (c is an integer, and c 〉=1), the size of integer c represented between main frame and the slave each exchanges data data bit what, for example c=8 represents that the width of data on the bus is 8.
The number N of data section equals the number of slave, and the number of slave is decided by the width of slave addresses sign indicating number, and the slave addresses sign indicating number adopts binary coding, so N=2
n, for example the slave number of the 2 bit address sign indicating number correspondences slave number that mostly is 4,3 bit address sign indicating number correspondences most mostly is 8 most, and the like, the slave number of 8 bit address sign indicating number correspondences mostly is 256 or the like most.
Check digit: can three kinds of verification modes: even parity check, odd, no parity check.
The host data verification: the data that main frame sent to slave are carried out parity check.
The slave data check: the data that slave sent to main frame are carried out parity check.
The width W 4=N*W3=(2 of data segment
n) * W3, wherein n represents the width of slave addresses sign indicating number.
4) ending segment: the end of a communication cycle of expression, the width that is sent by main frame is the clock signal of logical value=0 of W5.Set the width W 5=d*T of ending segment, (d is an integer, and d 〉=1).
The second, the course of work---comprise two parts: main-machine communication flow process and slave communication process.
(1) main-machine communication algorithm (see figure 3) on the universal serial bus:
1) sync section:
Main frame lasting output logic value on clock cable is 1 signal.Start timer internal t1 simultaneously, relatively the magnitude relationship of the sync section width value W1 of t1 and setting up to t1=W1, represents that synchronizing signal is effective.
After synchronizing signal was finished, clock signal switched to logical value 0.
At synchronous phase, the data-signal on the bus remains logical value 0.
2) functional section:
In the main frame sending function sign indicating number stage, the clock signal period on the bus=fundamental clock cycle promptly is the pulse signal of fixed cycle T on the clock holding wire.Host function sign indicating number transmission flow is seen Fig. 4.
Function code is to send according to the order of little-endian.Each clock cycle sends 1.Therefore data width is the function code of b, and process of transmitting will continue b clock cycle.
3) data segment:
Finish exchanges data between main frame and the slave at data segment, main frame relies on slave addresses number to discern for the addressing system of a plurality of slaves on the bus, sees Fig. 5.
In each communication cycle, the data that main frame is carried out with each slave successively according to the order of slave addresses number send and receive, and what slaves are arranged in this communication system, and how many individual sub-data segments are just arranged.Therefore main frame repeats the operation of subdata section in communication cycle, up to all finishing the exchange of data with whole slaves.
In the subdata section, be divided into c bit data and the check bit sum that main frame sends to slave i (i represents slave addresses number to be integer, and N 〉=i 〉=1) and receive c bit data and check digit two parts that slave i sends, see Fig. 7.
4) ending segment:
Main frame lasting output logic value on clock cable is 0 signal.Start timer internal t2 simultaneously, relatively the magnitude relationship of the ending segment width value W5 of t1 and setting up to t2=W5, represents that end signal is effective.
At ending segment, the data-signal on the bus remains logical value 0.
(2) the slave communication of algorithms on the universal serial bus:
The a plurality of slaves that are connected on the bus communicate according to communication protocol and main frame.Slave i communication work flow process is seen Fig. 6.
1) sync section:
It is 1 signal that slave detects logical value on the clock cable.Start timer internal t3 simultaneously, the recording clock signal remains the time of logical value 1, compares the magnitude relationship of the synchronizing signal width value W1 of t3 and setting, if t1 〉=W1, the expression synchronizing signal is effective.
2) functional section:
All slaves on the universal serial bus when the clock signal switches to logical value 0 by logical value 1, enter the receiving function sign indicating number stage automatically after detecting the efficient synchronization clock signal.
The function code of being sent by main frame is not distinguished the address digit of slave, but in the face of all are connected slave on the bus, therefore, all slaves receive identical functions sign indicating numbers, behind the slave receiving function sign indicating number, carry out identical operations.
Slave receiving function code stream journey is seen Fig. 8.
3) data segment:
After entering data segment, the count value C1 of slave opening entry serial clock pulse, with itself address number i relatively, and with this judge main frame whether with this slave swap data.Such address deterministic process, we are called slave addresses addressing process.
Address number is that the slave addressing process of i is seen Fig. 9 (i represents slave addresses number to be integer, and N 〉=i 〉=1).
If this machine address number be addressed identically from plane No., this slave will be carried out the reception and the transmit operation of data so.Address number is the slave of i and process such as Figure 10 of host exchanging data.
4) ending segment:
It is 0 signal that slave detects logical value on the clock cable.Start timer internal t4 simultaneously, the recording clock signal remains the time of logical value 0, compares the magnitude relationship of the end signal width value W5 of t4 and setting, if t4 〉=W5, the expression end signal is effective.
The half duplex serial bus communication system of embodiment 2, band clock signal
One) formation of the serial bus communication device of the present invention's design is referring to Fig. 1.
1) four-wire system, i.e. two pairs of unshielded twisted pairs are defined as follows:
Line 1: the single line of first pair of twisted-pair feeder: DC power supply+24V;
No. 2 lines: second line of first pair of twisted-pair feeder: direct current seedbed, i.e. 0V;
No. 3 lines: the single line of second pair of twisted-pair feeder: serial clock signal SCLK;
No. 4 lines: second line of second pair of twisted-pair feeder: serial data signal SDAT;
2) bus power source: for the communication contact that is connected on the bus provides working power.
3) terminating circuit: the signal that transmits in bus is a digital quantity, for anti-stop signal reflects in circuit terminal, causes interference, can use terminal absorption circuit to suppress signal and reflect in circuit terminal.Common terminating circuit can serve as with resistance, is that the resistance in 120 Europe can play the effect that terminal absorbs basically such as resistance.
Two) serial bus interface circuit of the present invention's design is referring to Figure 11.
Serial bus interface circuit comprises two parts: serial communication sends signaling conversion circuit, serial communication received signal change-over circuit.
The serial bus interface circuit function: for improving the distance and the reliability of transmission, the clock on the universal serial bus and the transformat of data-signal are difference form.Usually will to transmit differential signal need two circuits form a current loop, for example the RS485 standard regulation that comes to this.If like this, clock among the present invention and data-signal will be realized differential transfer, just must constitute two current circuits with four circuits.
For this reason, the present invention has designed special-purpose serial bus interface circuit, and its feature is: finish the transmission of two differential signals on a pair of multiple twin circuit.Its operation principle is: clock signal and data-signal alternate transmission, clock signal and data-signal be benchmark as a comparison mutually, can eliminate the signal voltage that common mode disturbances causes and float.
Console controller among the present invention and design according to mentioned above principle from the employed serial interface circuit of machine controller.
Three) console controller schematic diagram is referring to Figure 12.
Console controller is formed: communication protocol processor, serial communication send signaling conversion circuit, serial communication received signal change-over circuit, power-switching circuit.Wherein communication protocol processor is the core of console controller, and it is the microprocessor or the single-chip microcomputer of a band program curing normally, and serial communication protocol is handled and stored the data message that sends and receive designed according to this invention.
Console controller function: by parallel data bus line and central controller (for example original programmable controller of system or the like in the computer plate of electric life controller, other application) swap data, the parallel data bus line here comprises the signal of four main frame outputs: E1OUT, E2OUT, E3OUT, E4OUT, the signal of four main frame inputs: E5IN, E6IN, E7IN, E8IN.The parallel data that console controller sends central processing unit by the protocol processes in the main frame, converts serial data to and sends to universal serial bus and get on, and sends the slave of the appointment on the bus to.The serial data that console controller sends slave on the universal serial bus by the protocol processes in the main frame, converts parallel data to and sends on the parallel bus, sends central controller to.
Four) slave controller principle figure is referring to Figure 13.
Form from machine controller: identical with the composition of console controller, difference is the program curing in the communication protocol processor of slave.What solidify in the slave communication protocol processor is the slave communication protocol that the present invention designs.
Slave controller function: by parallel data bus line and external interface circuit (for example switching signal in the hall hall buttons indicator light of elevator, other application or the like) swap data, the parallel data bus line here comprises the signal of four slave outputs: E1B, E2B, E3B, E4B, the signal of four main frame inputs: E5B, E6B, E7B, E8B.The parallel data of external interface circuit being sent from machine controller by the protocol processes in the slave, converts serial data to and sends to universal serial bus and get on, and sends the main frame on the bus to.Serial data from machine controller sends main frame on the universal serial bus by the protocol processes in the slave, converts parallel data to and sends on the parallel bus, sends external interface circuit to.
Five) external interface circuit of slave is referring to Figure 14.
The slave external interface circuit is formed: output driving circuit and input Acquisition Circuit.Output driving circuit is used to drive outside performer, and as indicator light, relay, contactor or the like, output driving circuit is mainly finished the driving of signal lamp by triode 9013.The input Acquisition Circuit uses resistor voltage divider circuit to finish the collection of input signal, and sends slave to.
Slave external interface circuit function: will carry out level conversion from the signal of machine controller input and output, to adapt to the needs of slave control and outside working control signal.The circuit of this example design is an elevator lobby hall buttons indicating circuit, can finish the input of four button signal and the output of four indicator light signals.
The application block diagram of the present invention in the outside input/output signal of elevator is referring to Figure 15.
A common elevator has a plurality of floors, and (M represents with integer, M 〉=2), each floor hall has some to input or output signal, for example up call button and indicating device (being called the outgoing call demand pusher indicator), fireman's switch, lock ladder switch etc. are arranged in lowermost layer, up/descending hall buttons and indicating device arranged in the intermediate layer, descending hall buttons and indicating device etc. are arranged top.
M is corresponding with the elevator floor number, has in M on the control handwheel in the car of elevator and selects button and indicating device.
Elevator operation the time need continuous acquisition and upgrade outgoing call and in select signal, because these signals all are the discrete switch signals, if use traditional mode of connection, each demand pusher indicator connects 2 holding wires at least, the elevator of M layer has altogether and selects button and (M-2) * 2+2 outgoing call button in the M, need parallel 2M+ (M-2) the * 4+4=6M-4 root holding wire at least of drawing from elevator control cabinet so, when floor number M is big (M 〉=10 usually), required holding wire quantity obviously increases, the Wiring technique complexity, poor stability, maintenance difficulties strengthens.
Serial communication system for this situation uses the present invention to design only need draw two groups of universal serial bus from elevator control cabinet, wherein choosing in the winding lift car, another group is gone the floor outgoing call, obviously simplified wiring technology improves the stability of signal transmission, makes things convenient for operation maintenance.
Claims (8)
1, a kind of half duplex serial bus communication means with clock signal is characterized in that this method may further comprise the steps:
---the shared formula universal serial bus that is identified for communicating by letter;
---determine to share each slave in N the slave of communicating by letter that inserts on the formula universal serial bus with address number as the unique identification code of slave, wherein N is an integer, and N 〉=1;
---on universal serial bus, send also receiving cycle sexual intercourse by communication host by frame structure and change information;
---each slave carries out exchanges data according to corresponding identification code and the main frame in the frame structure of main frame transmission;
---finish one time the communication cycle process.
2, the half duplex serial bus communication means of band clock signal according to claim 1 is characterized in that the frame structure that main frame sends comprises: sync section, functional section, data segment, ending segment; Wherein
---sync section: be the clock signal of logical value=1 of certain time, width setup is W1=a*T, and T is the reference signal cycle of bus timing, and a is an integer, and a 〉=1; Be used to represent the beginning of a communication cycle, send, be connected all slaves on the bus after detecting synchronizing signal, begin a new communication cycle by main frame;
---functional section: for the good bus line command of predefined, sent by main frame, all slaves all can receive and respond; The width setup of functional section is W2=b*T, and b is an integer, and b 〉=1, and what of the shared data bit of functional section spread factor b represent;
---data segment: be used to finish the exchanges data between main frame and the slave, comprise N sub-data segment, the address correspondence of each subdata Duan Yuyi slave;
Subdata section: comprise that main frame sends to c bit data and check digit two parts that the c bit data of slave and check digit and slave send to main frame;
The width W 3=2 of single subdata section (c+1) * T, c is an integer, and c 〉=1, integer c represents the data bits of each exchanges data between main frame and the slave;
---ending segment: the end of a communication cycle of expression, the clock signal of logical value=0 of sending by main frame, width W 5=d*T, d are integer, and d 〉=1;
3, communication means according to claim 1 and 2, the maximum of the slave number that it is characterized in that communicating by letter is N=2
n, n is the width of slave addresses sign indicating number.
4, a kind of half duplex serial bus communication system with clock signal, comprise main frame, slave, serial communication bus, it is characterized in that serial communication bus comprises: power line, common ground, data wire and 4 leads of clock line, the serial communication bus two ends are the connecting terminal circuit respectively, and main frame and slave insert on the serial communication bus by serial bus interface circuit respectively.
5, half duplex serial bus communication system according to claim 4, it is characterized in that serial bus interface circuit comprises: serial communication sends signaling conversion circuit and serial communication received signal change-over circuit two parts, the input that sends change-over circuit is connected main frame or slave respectively with the output that receives change-over circuit, and the output that sends change-over circuit is connected universal serial bus respectively with the input that receives change-over circuit.
6, according to claim 4 or 5 described half duplex serial bus communication systems, it is characterized in that console controller comprises: communication protocol processor---be used for parallel data that the external control central processing unit is sent, converting serial data to sends to universal serial bus and gets on, send the slave of the appointment on the bus to, and the serial data that slave on the universal serial bus is sent, convert parallel data to and send on the parallel bus, send central controller to; Serial communication sends signaling conversion circuit---and be used for that the serial data that communication protocol processor sends is sent to universal serial bus and get on; Serial communication received signal change-over circuit---be used to receive the serial data that slave sends on the universal serial bus, and send into communication protocol processor; Power-switching circuit---the power supply that provides each several part required is provided.
7, according to claim 4 or 5 described half duplex serial bus communication systems, it is characterized in that comprising: communication protocol processor from machine controller---be used for serial data that main frame on the universal serial bus is sent, converting parallel data to sends on the outside parallel bus, send the applications unit to by external interface circuit, and the parallel data that the applications unit is sent, convert serial data to and send on the universal serial bus, send the main frame on the bus to; Serial communication received signal change-over circuit---be used to receive the serial data that main frame sends on the universal serial bus, and send into the slave communication protocol processor; Serial communication sends signaling conversion circuit---and be used for that the serial data that communication protocol processor sends is sent to universal serial bus and get on; Power-switching circuit---the power supply that provides each several part required is provided.
8, half duplex serial bus communication system according to claim 7, it is characterized in that the external interface circuit of slave comprises: output driving circuit is used to drive outside performer; With the input Acquisition Circuit, be used to finish the collection of input signal and send slave to.
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2004
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