CN113722254A - Multi-host communication bus system suitable for industrial control field - Google Patents
Multi-host communication bus system suitable for industrial control field Download PDFInfo
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- CN113722254A CN113722254A CN202110567753.0A CN202110567753A CN113722254A CN 113722254 A CN113722254 A CN 113722254A CN 202110567753 A CN202110567753 A CN 202110567753A CN 113722254 A CN113722254 A CN 113722254A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a multi-host communication bus system suitable for an industrial control field, which is based on a plurality of groups of differential signals, uses a group of differential signal transmission clocks, uses one or more groups of signals to transmit data and can transmit the data in a parallel mode; the bus of the invention transmits the clock of the sender, so that the receiver does not need to recover and extract the clock signal from the data signal, and can receive the data only by using the common shift register, thereby reducing the hardware complexity of signal synchronization and increasing the length of the longest transmission unit. When the bus is used for data transmission, the hardware design is simple, and multiplexing can be performed on the basis of the existing hardware.
Description
Technical Field
The invention belongs to the technical field of bus communication, and particularly relates to a multi-host communication bus system suitable for an industrial control field.
Background
The industrial control bus system is a bus system widely used in the field of industrial control systems, is mainly optimized for the industrial control field, and has strong anti-interference performance. Currently, widely used industrial control buses include RS232, RS485, CAN, and the like. RS232 is a point-to-point communication bus, RS485 is a single-master multi-slave bus based on differential signals, and CAN is a multi-master multi-slave bus based on differential signals.
With the increase of complexity of industrial field devices, a point-to-point bus with a single master and multiple slave type cannot meet new requirements in terms of redundancy and connection complexity, so that more and more industrial control systems require the use of a multi-master and multiple slave bus, but serial multi-master and multiple slave buses such as a CAN (controller area network) belong to a serial transmission bus, and the problems of low transmission efficiency, need of synchronization by a receiving party, short longest transmission word length and the like exist.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a multi-host communication bus system suitable for an industrial control field, which can transmit data in a parallel mode based on a plurality of groups of differential signals and can transmit longer-length data without signal synchronization of slave machines. When the bus is used for data transmission, the hardware design is simple, and multiplexing can be performed on the basis of the existing hardware.
The invention is realized by the following technical scheme:
a multi-host communication bus system suitable for industrial control field comprises:
using multiple groups of differential signals as a physical layer transmission mode, wherein '1' is dominant potential, and when a differential bus has a voltage difference, the differential bus is regarded as data '1'; the '0' is a recessive potential, when no voltage difference exists on the differential bus, the data is regarded as '0', and when no external drive exists on the bus, the recessive potential is kept;
transmitting data using one or more sets of signals using a set of differential signaling clocks;
and a data frame sending process: when the host is ready to send data, firstly monitoring whether the bus is in an idle state, if so, driving a clock signal line by using a standard clock, and sending data '0' of N1 clock cycles to the bus as a frame starting part; in the next N1 clock cycles, the host monitors whether the own sending signal is consistent with the own receiving signal through an exclusive-or gate, if so, the host indicates that no conflict exists on the bus, and if not, the host which has a larger difference with the local clock signal also occupies the bus, and the host which firstly monitors the event gives up the occupation of the bus and goes to a monitoring state; if the host keeps occupying the bus for N1 clock cycles continuously, the host continues to drive the clock signal to transmit N2 cycles of data '1' to the bus, and then sequentially transmits the local address and the destination address, in the stage, the host starts exclusive or check when transmitting the local address and the destination address, if the local drive signal is not consistent with the actual signal of the bus, the host with a smaller difference between the clock signal and the local address also occupies the bus, the host which still keeps correct transmission information keeps occupying the bus, otherwise, the control right of the bus is abandoned; if the host still has control of the bus, the host will transmit the frame information portion for the next N3 cycles; after the frame information part is transmitted, the host adjusts the clock into a high-speed clock and quickly transmits effective data under the clock; after the effective data transmission is finished, the host switches back to the standard clock and transmits the check code part under the clock; finally, the host drives a clock line N4 clock cycles, samples bus data according to the sampling edge of the slave, and stores the bus data as a frame response part in a cache;
and a data frame receiving process: when the slave receives data, if the transmission of continuous data 0 exceeding N1/4 clock cycles occurs, which indicates that the transmission has started, the slave will continue to listen until N2 cycles of data 1 occur on the bus, and at this time, the slave considers that the correct frame start part has been received and is ready to accept further frame data; if the slave receives the correct frame starting part, the slave receives the address part, the frame information part, the data part and the verification part in sequence in the next clock period, when the data transmission of the last clock of the verification part is finished, the slave starts to drive the data line part of the bus, response information is driven to the bus under the clock drive of the host, then the slave sets a receiving flag bit, and a circuit driven by a local clock performs further data processing.
In the technical scheme, in the process of transmitting the frame information part, the data part and the check code part, the host computer uses the clock edge which is the same as the slave computer for sampling to carry out conflict monitoring, and if the data on the bus is not consistent with the drive, the host computer gives up the control on the bus.
In the above technical solution, after the host snoops that the bus is idle for more than 3 × N1+1 maximum clock cycles, it is determined that the bus is in an idle state.
In the technical scheme, in the receiving process of the slave, the local clock consistent with the standard clock is always started for monitoring, and when the bus has no signal transmission in the clock period of N1+1 continuously, the current transmission frame of the bus is considered to be abandoned or has errors, and the frame is abandoned.
In the above technical solution, if the slave receives the correct frame start part, it will receive the address part and judge whether it is the receiving end in the next several clock cycles.
In the above technical solution, the slave will continue to receive the frame information portion, the data portion and the check portion no matter whether it is the receiving end.
In the technical scheme, the slave continuously uses the clock provided by the differential bus in the receiving process, when the data transmission of the last clock of the verification part is finished, if the slave is the receiving end, the slave starts to drive the data line part of the bus and drives the response information to the bus under the clock drive of the host, and then the slave sets the receiving flag bit and carries out further data processing by a circuit driven by a local clock.
In the above technical solution, the bus data frame of the present invention is divided into a start portion, an address portion, a frame information portion, a data portion, a check portion, and a response portion, wherein the start portion is used to indicate generation of a new frame on the bus; the address part is used for indicating the source address and the destination address of the frame; the frame information part is used for indicating the type, length and other necessary additional information of the frame; the data portion represents the data that is actually to be transmitted; the check part is a set of check information generated by calculating an address part, a frame information part and a data part of the frame and used for checking the integrity of the frame; the response part is used for reporting the receiving condition from the slave to the master.
In the above technical solution, the bus of the present invention transmits data by using the rising edge or the falling edge of the clock, and when the master performs data change on the rising edge of the clock, the slave performs data sampling on the falling edge of the clock, thereby forming a rising edge mode; when the master changes data at the falling edge of the clock, the slave samples data at the rising edge of the clock, and the mode is a falling edge mode.
In the above technical solution, the clock used in the present invention includes a standard clock and a high-speed clock, the standard clock is a bus transmission clock specified uniformly, and the master and the slave keep consistent, and the high-speed clock is used for data transmission, and the master may not be consistent but must be higher than the frequency of the standard clock.
The invention has the advantages and beneficial effects that:
the invention is based on multiple groups of differential signals, can transmit data in a parallel mode, and can transmit data with longer length without synchronizing signals of slaves. When the bus is used for data transmission, the hardware design is simple, and multiplexing can be performed on the basis of the existing hardware.
The bus of the invention transmits the clock of the sender (the master), so that the receiver (the slave) does not need to recover and extract the clock signal from the data signal any more, and can realize the data reception by only using a common shift register, thereby reducing the hardware complexity of signal synchronization and increasing the length of the longest transmission unit.
Meanwhile, because the data bus can be expanded, the bus of the invention can be easily expanded to various bandwidths of 4bit, 8bit, 16bit, 32bit and the like, and can adapt to the requirements of different transmission rates.
Drawings
FIG. 1 is a diagram of the physical layer structure of the bus of the present invention;
FIG. 2 is a data link layer frame structure of the bus of the present invention;
FIG. 3 is a data frame transmission process of the bus of the present invention;
FIG. 4 illustrates a data frame reception process of the bus of the present invention;
FIG. 5 is a schematic diagram of the arbitration method of carrier sense for the bus according to the present invention;
FIG. 6 is a carrier sense collision scenario 1 for a bus of the present invention;
FIG. 7 is a carrier sense collision scenario 2 for the bus of the present invention;
fig. 8 shows the carrier sense collision scenario 3 of the bus of the present invention.
For a person skilled in the art, other relevant figures can be obtained from the above figures without inventive effort.
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution of the present invention is further described below with reference to specific examples.
The invention uses a plurality of groups of differential signals as a physical layer transmission mode, wherein '1' is dominant potential, and when a differential bus has voltage difference, the differential bus is regarded as data '1'; a "0" is a recessive potential and is considered a data "0" when there is no voltage difference on the differential bus. When the bus is not externally driven, the recessive potential will be maintained.
Referring to fig. 1, the physical layer architecture of the bus of the present invention uses a set of differential signaling clocks to transmit data using one or more sets of signals. TX is connected with a transmitting signal of a data link layer, RX is connected with a receiving signal of the data link layer, and BUS + and BUS-are respectively connected with the positive electrode and the negative electrode of the differential BUS. In particular, the number of differential signal groups for transmitting data is scalable, but is fixed for a certain usage environment.
Referring to fig. 2, the frame structure of the data link layer of the bus of the present invention is divided into a start portion, an address portion, a frame information portion, a data portion, a check portion, and a response portion. Wherein, the initial part is used for indicating the generation of a new frame on the bus; the address part is used for indicating the source address and the destination address of the frame; the frame information part is used for indicating the type, length and other necessary additional information of the frame; the data portion represents the data that is actually to be transmitted; the check part is a set of check information generated by calculating an address part, a frame information part and a data part of the frame and used for checking the integrity of the frame; the response part is used for reporting the receiving condition from the slave to the master.
The bus of the invention transmits data by using the rising edge or the falling edge of the clock, and when the host computer performs data change on the rising edge of the clock, the slave computer performs data sampling on the falling edge of the clock to form a rising edge mode; when the master changes data at the falling edge of the clock, the slave samples data at the rising edge of the clock, and the mode is a falling edge mode.
The clock used by the invention comprises a standard clock and a high-speed clock, wherein the standard clock is a bus transmission clock specified uniformly, all the master machines and the slave machines are kept consistent, the high-speed clock is used for data transmission, and all the master machines can be inconsistent but must be higher than the frequency of the standard clock.
The bus of the invention adopts a carrier monitoring mode to carry out competition president. Referring to fig. 3, in the data frame transmission process of the bus of the present invention, when the host is ready to transmit data, it first listens to the bus until it is found that the bus is free for more than 3 × N1+1 maximum clock cycles, then drives the clock signal line using the standard clock, and transmits data "0" of N1 clock cycles to the bus as the frame start part; in the next N1 clock cycles, the host will monitor whether the own transmitted signal is consistent with the received signal through the xor gate, if so, it indicates that there is no conflict on the bus, if not, it indicates that a host with a larger difference from the local clock signal is also occupying the bus, and the host monitoring this event first will give up the occupation of the bus and turn to the monitoring state; if the host keeps occupying the bus for N1 clock cycles continuously, the host continues to drive the clock signal to transmit N2 cycles of data '1' to the bus, and then sequentially transmits the local address and the destination address, in this stage, the host starts exclusive OR check when transmitting the local address and the destination address, if the local drive signal is not consistent with the actual signal of the bus, the host with smaller difference between the clock signal and the local address also occupies the bus, the transmitted information still keeps the correct host to keep occupying the bus, otherwise, the control right to the bus is abandoned; if the host still has control over the bus, the host will transmit the frame information portion, including frame type and frame length, for the next N3 cycles; after the frame information part is transmitted, the host adjusts the clock to be in a high-speed clock mode and quickly transmits effective data under the clock; after the effective data transmission is finished, the host switches back to the standard clock and transmits the check code part under the clock; finally, the master drives clock line N4 clock cycles and samples the bus data according to the slave sampling edge, and stores it as a frame response portion in the buffer. In the process of transmitting the frame information part, the data part and the check code part, the host computer uses the clock edge which is the same as the slave computer for sampling to carry out conflict monitoring, and if the data on the bus is not consistent with the drive, the host computer gives up the control on the bus.
Referring to fig. 4, in the data frame receiving process of the bus of the present invention, when the slave receives data, it listens to the bus data based on the clock of the differential bus, and any time transmission of continuous data "0" occurs in excess of N1/4 clock cycles, indicating that transmission has started, the slave will continue to listen until N2 cycles of data "1" occur on the bus, at which time the slave considers that the correct frame start has been received and is ready to receive further frame data; if the slave receives the correct frame start part, it will receive the address part, the frame information part, the data part and the check part in turn in the next several clock cycles, the clock provided by the differential bus will be used continuously in the receiving process, when the data transmission of the last clock of the check part is finished, the slave will start to drive the data line part of the bus and drive the response information to the bus under the clock drive of the host, then the slave will set the receiving flag bit, and the circuit driven by the local clock will process the data further.
During the process of receiving the slave, a local clock (allowing a certain offset) which is basically consistent with the standard clock is always started for monitoring, and when the bus has no signal transmission for N1+1 clock cycles continuously, the current transmission frame of the bus is considered to be abandoned or has errors, and the frame is abandoned. If the slave receives the correct start of frame portion, it will receive the address portion and determine if it is the receiving end for the next several clock cycles. Whether the receiving end is used or not, the receiving end continues to receive the frame information part, the data part and the verification part, the clock provided by the differential bus is continuously used in the receiving process, when the data transmission of the last clock of the verification part is finished, if the slave is used as the receiving end, the slave starts to drive the data line part of the bus and drives the response information to the bus under the clock drive of the host, then the slave is set to receive the flag bit, and a circuit driven by a local clock carries out further data processing.
Fig. 5 shows the arbitration method of carrier sense of the bus of the present invention, and fig. 6, 7 and 8 show three arbitration processes of carrier sense of the bus of the present invention. The first and second cases are applied to the process of the host transmitting the frame start and address parts, the host asynchronously monitors whether the own transmitted signal is consistent with the received signal through an exclusive-or gate, if so, no conflict exists on the bus, otherwise, conflict exists, and the bus data and the host which is not expected to be correct lose the control right on the bus. The third condition is suitable for the process that the host computer transmits the frame type, the data and the verification part and synchronously monitors whether the own sending signal is consistent with the own receiving signal according to the sampling edge of the slave computer through an exclusive-or gate, if so, the bus is not conflicted, otherwise, the bus data and the host computer which is not expected to be correct lose the control right of the bus.
The invention has been described in an illustrative manner, and it is to be understood that any simple variations, modifications or other equivalent changes which can be made by one skilled in the art without departing from the spirit of the invention fall within the scope of the invention.
Claims (10)
1. A multi-host communication bus system suitable for industrial control field is characterized in that:
using multiple groups of differential signals as a physical layer transmission mode, wherein '1' is dominant potential, and when a differential bus has a voltage difference, the differential bus is regarded as data '1'; the '0' is a recessive potential, when no voltage difference exists on the differential bus, the data is regarded as '0', and when no external drive exists on the bus, the recessive potential is kept;
transmitting data using one or more sets of signals using a set of differential signaling clocks;
and a data frame sending process: when the host is ready to send data, firstly monitoring whether the bus is in an idle state, if so, driving a clock signal line by using a standard clock, and sending data '0' of N1 clock cycles to the bus as a frame starting part; in the next N1 clock cycles, the host monitors whether the own sending signal is consistent with the own receiving signal through an exclusive-or gate, if so, the host indicates that no conflict exists on the bus, and if not, the host which has a larger difference with the local clock signal also occupies the bus, and the host which firstly monitors the event abandons the occupation of the bus and turns to a monitoring state; if the host keeps occupying the bus for N1 clock cycles continuously, the host continues to drive the clock signal to transmit N2 cycles of data '1' to the bus, and then sequentially transmits the local address and the destination address, in the stage, the host starts exclusive or check when transmitting the local address and the destination address, if the local drive signal is not consistent with the actual signal of the bus, the host with smaller difference between the clock signal and the local address also occupies the bus, the host which still keeps correct transmission information keeps occupying the bus, otherwise, the control right to the bus is abandoned; if the host still has control of the bus, the host will transmit the frame information portion for the next N3 cycles; after the frame information part is transmitted, the host adjusts the clock to be a high-speed clock and quickly transmits effective data under the clock; after the effective data transmission is finished, the host switches back to the standard clock and transmits the check code part under the clock; finally, the host drives a clock line N4 clock cycles, samples bus data according to the sampling edge of the slave, and stores the bus data as a frame response part in a cache;
and a data frame receiving process: when the slave receives data, if the transmission of continuous data 0 exceeding N1/4 clock cycles occurs, which indicates that the transmission has started, the slave will continue to listen until N2 cycles of data 1 occur on the bus, and at this time, the slave considers that the correct frame start part has been received and is ready to accept further frame data; if the slave receives the correct frame starting part, the slave receives the address part, the frame information part, the data part and the verification part in sequence in a plurality of next clock cycles, when the data transmission of the last clock of the verification part is finished, the slave starts to drive the data line part of the bus, response information is driven onto the bus under the clock drive of the host, then the slave sets a receiving flag bit, and a circuit driven by a local clock carries out further data processing.
2. The multi-host communication bus system of claim 1, wherein: in the process of transmitting the frame information part, the data part and the check code part, the host computer uses the clock edge which is the same as the slave computer for sampling to carry out conflict monitoring, and if the data on the bus is not consistent with the drive, the host computer gives up the control on the bus.
3. The multi-host communication bus system of claim 1, wherein: when the host snoops that the bus is idle for more than 3 × N1+1 maximum clock cycles, the bus is determined to be idle.
4. The multi-host communication bus system of claim 1, wherein: during the process of receiving the slave, a local clock consistent with the standard clock is always started for monitoring, and when the bus has no signal transmission in N1+1 clock cycles continuously, the current transmission frame of the bus is considered to be abandoned or has errors, and the frame is abandoned.
5. The multi-host communication bus system of claim 4, wherein: if the slave receives the correct frame start part, the slave receives the address part and judges whether the slave is the receiving end in the next several clock cycles.
6. The multi-host communication bus system of claim 5, wherein: the slave will continue to receive the frame information portion, data portion and check portion, whether on the receiving side or not.
7. The multi-host communication bus system of claim 6, wherein: the slave continuously uses the clock provided by the differential bus in the receiving process, when the data transmission of the last clock of the verification part is finished, if the slave is the receiving end, the slave starts to drive the data line part of the bus and drives the response information to the bus under the clock drive of the master, and then the slave sets the receiving flag bit and carries out further data processing by a circuit driven by a local clock.
8. The multi-host communication bus system of claim 1, wherein: the bus data frame is divided into a start part, an address part, a frame information part, a data part, a check part and a response part, wherein the start part is used for indicating the generation of a new frame on the bus; the address part is used for indicating the source address and the destination address of the frame; the frame information part is used for indicating the type, length and other necessary additional information of the frame; the data portion represents the data that is actually to be transmitted; the check part is a set of check information generated by calculating an address part, a frame information part and a data part of the frame and used for checking the integrity of the frame; the response part is used for reporting the receiving condition from the slave to the master.
9. The multi-host communication bus system of claim 1, wherein: the bus transmits data by using the rising edge or the falling edge of the clock, and when the host carries out data change on the rising edge of the clock, the slave carries out data sampling on the falling edge of the clock to form a rising edge mode; when the master changes data at the falling edge of the clock, the slave samples data at the rising edge of the clock, and the mode is a falling edge mode.
10. The multi-host communication bus system of claim 1, wherein: the clock used by the invention comprises a standard clock and a high-speed clock, wherein the standard clock is a bus transmission clock specified in a unified way, and all the master and slave machines are kept consistent; the high-speed clock is used for data transmission and has a frequency higher than that of a standard clock.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116915367A (en) * | 2023-09-12 | 2023-10-20 | 苏州萨沙迈半导体有限公司 | Data detection method, storage medium and electronic device |
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