CN112463693A - Multi-board card communication system and method based on M-LVDS bus - Google Patents
Multi-board card communication system and method based on M-LVDS bus Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention provides a multi-board card communication system and a method based on an M-LVDS bus, which comprises the following steps: the system comprises an M-LVDS bus, an M-LVDS drive chip and an M-LVDS controller; the M-LVDS controller outputs a digital signal of control and data to an M-LVDS driving chip; the M-LVDS driving chip realizes the conversion between a digital signal and a differential level signal; the M-LVDS bus can transmit H/L level signals; the M-LVDS bus and the sending channel are correspondingly a receiving channel, and in the receiving direction, the M-LVDS driving chip converts the H/L level signal on the M-LVDS bus into a digital signal and submits the digital signal to the M-LVDS controller. The invention can meet the requirement of transmission rate of 1 Mbs-100 Mbps, the number of the supporting nodes can reach 32, and the transmission distance can reach 50 meters.
Description
Technical Field
The invention relates to the technical field of digital communication, in particular to a multi-board card communication system and method based on an M-LVDS bus.
Background
In embedded systems such as a control system of rail transit, there are many boards, and communication is required between the boards. The communication protocols widely used for the current board-level communication are as follows: PCI, CAN, I2C, SPI, serial port, Ethernet, etc., wherein the CAN bus protocol is used more for serial communication. Based on the considerations of safety, convenience, low cost and the like, the CAN bus protocol is widely used in the automobile industry, the maximum supported length of the CAN bus is 40 meters, and the highest communication speed is 1 Mbps.
In a rail transit control system, the transmission rate between board cards is required to be between 25Mbps and 100Mbps, and a CAN bus cannot meet the communication requirement. The ethernet transmission supports transmission rates of 10/100/1000Mbps, but the ethernet has poor real-time performance and reliability, and is not suitable for use in control embedded systems.
Patent document CN108038073ago discloses a multi-board communication system based on MLVDS, which includes a first communication board and a plurality of second communication boards that are connected and communicated with each other, where the first communication board and the second communication board include an FPGA chip, a first MLVDS chip, and a second MLVDS chip; the first communication board card comprises a clock chip; the FPGA chip of the first communication board card is respectively connected with the clock chip and the second MLVDS chip of the first communication board card, and the clock chip is connected with the first MLVDS chip of the first communication board card; the FPGA chip of the second communication board card is respectively connected with the first MLVDS chip and the second MLVDS chip of the second communication board card; the second MLVDS chip of the first communication board card is connected with the second MLVDS chip of the second communication board card through a data bus, and the first MLVDS chip of the first communication board card is connected with the first MLVDS chip of the second communication board card through a clock bus, so that the first communication board card and the second communication board card share a clock. The patent still leaves room for improvement in structural and technical effects.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a multi-board card communication system and method based on an M-LVDS bus.
The invention provides a multi-board communication system based on an M-LVDS bus, which comprises: the system comprises an M-LVDS bus, an M-LVDS drive chip and an M-LVDS controller; the M-LVDS controller (realized based on FPGA) outputs digital signals of control and data to the M-LVDS driving chip; the M-LVDS driving chip realizes the conversion between a digital signal and a differential level signal; converting the 0 and 1 digital signals into M-LVDS total H/L signals, wherein the M-LVDS bus is used as a transmission medium and can transmit H/L level signals and the like; the M-LVDS bus and the sending channel are correspondingly a receiving channel, and in the receiving direction, the M-LVDS driving chip converts the H/L level signal on the M-LVDS bus into a digital signal and submits the digital signal to the M-LVDS controller.
Preferably, the method further comprises the following steps: a board card component;
the M-LVDS driving chip and the M-LVDS controller are arranged on the board card part;
the board card component is connected with the M-LVDS bus.
Preferably, the number of the board card parts is one or more;
the plurality of board card components are connected with the M-LVDS bus.
Preferably, the M-LVDS bus is a shared bus;
each node on the M-LVDS bus is capable of initiating a transfer transaction.
In order to solve the problem that multiple nodes compete for the bus use right, an arbitration strategy needs to be defined. The signal quality on the bus is deteriorated due to the possibility that multiple nodes drive the bus simultaneously during arbitration. The invention therefore provides that only one node on the bus can actively initiate a bus transaction. This node is typically the main processor board in the control system and is responsible for data collection and processing. The node is called as a master node, and other nodes are called as slave nodes.
Preferably, each node on the M-LVDS bus is provided with a unique chassis number and slot number as a unique identifier of the node. The master node periodically generates a control frame, and polls whether other nodes on the bus are still in an active state or not according to the chassis number and the slot number in sequence so as to identify the nodes on the bus. The format of the control frame and the format of the slave node response frame are described in the following frame format definition section.
If the slave node does not receive the control frame for a long time, the control frame is displayed on the panel of the case through the indicator lamp.
And the master node determines how many nodes are on the bus according to the received application frames of the slave nodes.
Preferably, the master node on the M-LVDS bus is capable of listening to the transmitted control frame while transmitting the control frame. This is mainly to detect that the connection of the master node to the bus is not faulty. If the master node cannot monitor the transmitted control frame, the transmission path of the master node may fail; or the reception path of the master node fails. At this time, the master node will stop sending control frames and display them on the chassis panel through the indicator light.
A backup master node may be provided on the bus. If the backup main node does not receive the control frame for a long time, the backup main node is activated into a main node, takes over the bus, generates the control frame and sends the control frame to the bus.
Preferably, the format of the transmission frame is defined according to the format definition control information of the M-LVDS bus transmission frame, and the format definition result information of the M-LVDS bus transmission frame is obtained.
The format of the frame transmitted on the bus is shown in fig. 2. The frame format is illustrated as follows:
frame start symbol: 8 bits, value 8' h00, for identifying the start of a frame;
frame synchronization symbol: 8 bits, value bit 8' hAA, for clock recovery from the node;
frame type: 8 bits, the frame type value is encoded as follows:
8' hff: and the control frame is used for polling whether the node is in an active state. After receiving the control frame, the slave node transmits a drive control response frame to the bus;
8' hf 0: and the control response frame is used for handling the control frame of the main node. And after receiving the control frame from the node, driving a control response frame to the bus. The control frame and the response control frame appear in pairs, and the specific format and timing relationship are shown in fig. 3.
8' hf5 write command frame for the master node to write data to the slave node. The write command frame is the same as the standard transport frame format of fig. 2.
8' hf 6: and the read command frame is used for sending the read command to the slave node by the master node.
8' hf 7: a read command response frame for sending read data from the node onto the bus. The read command frame and the read command response frame appear in pairs, and the format and timing relationship of the two are shown in fig. 4.
Frame length: 8 bits, indicating the number of bytes of the data payload section, in units of 16 bits, i.e. 2 bytes. A 0 indicates no data payload, a 1 indicates 2 bytes for the data payload portion, a 2 indicates 4 bytes for the data payload portion, …, and so on, and a maximum of 255 indicates 510 bytes for the data payload. In a specific implementation, the maximum value of the frame length may be defined as 128, that is, the data load is 256 bytes at maximum;
destination node address/slave node address: 16 bits, consisting of 8-bit box number + 8-bit slot address.
Data loading: the length is determined by the frame length, and the specific content is analyzed by software;
and (4) checking codes: 16 bits are check codes generated according to frame types, frame lengths, target node addresses, data loads and the like.
The frame transmission on the bus is initiated by the master node, and the response frames of the slave nodes are responded 8 clock cycles after the control frame or the command frame is received. If the slave node does not detect a signal on the bus within 64 bus cycles, it is determined that the slave node is not on the bus. The response frame is spaced above 32 bus clock cycles from the new control or command frame.
Preferably, the reference clock frequency of all nodes on the M-LVDS bus is 100 MHz. The clock frequencies supported on the bus are: 1MHz, 10MHz, 25MHz, 50MHz, 100MHz, etc. After the node is connected to the bus, firstly, a frame start character on the bus is determined, and the bus is characterized in that a falling edge appears after a period of idle state (no device drives the bus, and a signal output to the FPGA by an M-LVDS drive chip is 1), and then a rising edge appears. The number of cycles of the bus clock can be determined by counting the number of cycles between two edges with reference to a clock (100 MHz). For example, if the counter value between two edges is above 750, then it can be inferred that the bus transmission clock frequency is 1 MHz; if the counter value is between 75 and 85, the bus clock frequency can be preliminarily inferred to be about 10 MHz. Based on the frame start, only the transmission clock frequency of the bus can be preliminarily guessed. The transmission clock frequency of the bus is further confirmed according to the frame synchronization symbol.
After the slave node is connected to the bus, 2-3 frames may be passed before the bus transmission clock frequency is determined.
According to the multi-board communication method based on the M-LVDS bus, provided by the invention, the multi-board communication system based on the M-LVDS bus is adopted, and multi-board communication can be carried out based on the M-LVDS bus.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention can meet the requirement of transmission rate of 1 Mbs-100 Mbps, the number of the supporting nodes can reach 32, and the transmission distance can reach 50 meters;
2. the invention can meet the application requirements of control embedded systems such as a rail transit control system and the like;
3. the invention has reasonable structure and convenient use and can overcome the defects of the prior art.
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Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic diagram of a multi-board communication system based on an M-LVDS bus according to the present invention.
Fig. 2 is a diagram illustrating a format of a transmission frame according to an embodiment of the present invention.
Fig. 3 is a diagram illustrating a control frame and a control response frame according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a read command frame and a read command response frame according to an embodiment of the invention.
Fig. 5 is a schematic structural block diagram of a master node M-LVDS controller according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Fig. 1 shows a block diagram of a multi-board communication system based on an M-LVDS bus. The M-LVDS controller (realized based on FPGA) outputs digital signals of control and data to the M-LVDS driving chip, the M-LVDS driving chip realizes the conversion of the digital signals and differential level signals, 0 and 1 digital signals are converted into total H/L signals of the M-LVDS, and an M-LVDS bus is used as a transmission medium to transmit the level signals such as H/L. The M-LVDS driving chip converts the H/L level signal on the M-LVDS bus into a digital signal in the receiving direction and submits the digital signal to the M-LVDS bus controller. The process of transmitting data based on the M-LVDS bus is briefly described, and a specific implementation method of the present invention is described below.
The key points are as follows: defining arbitration policies
Theoretically, the M-LVDS bus is a shared bus, each node on the bus can initiate a transmission transaction, and in order to solve the problem that multiple nodes compete for the right to use the bus, an arbitration policy needs to be defined. The signal quality on the bus is deteriorated due to the possibility that multiple nodes drive the bus simultaneously during arbitration. The invention therefore provides that only one node on the bus can actively initiate a bus transaction. This node is typically the main processor board in the control system and is responsible for data collection and processing. The node is called as a master node, and other nodes are called as slave nodes.
The key points are as follows: identification of nodes on a bus
Each node on the bus has a unique chassis number and slot number as the unique identifier of the node. The master node periodically generates a control frame, and polls whether other nodes on the bus are still in an active state or not according to the chassis number and the slot number in sequence so as to identify the nodes on the bus. The format of the control frame and the format of the slave node response frame are described in the following frame format definition section.
If the slave node does not receive the control frame for a long time, the control frame is displayed on the panel of the case through the indicator lamp.
And the master node determines how many nodes are on the bus according to the received application frames of the slave nodes.
The key points are as follows: implementation of reliability
The master node also monitors the transmitted control frame while transmitting the control frame. This is mainly to detect that the connection of the master node to the bus is not faulty. If the master node cannot monitor the transmitted control frame, the transmission path of the master node may fail; or the reception path of the master node fails. At this time, the master node will stop sending control frames and display them on the chassis panel through the indicator light.
A backup master node may be provided on the bus. If the backup main node does not receive the control frame for a long time, the backup main node is activated into a main node, takes over the bus, generates the control frame and sends the control frame to the bus.
The key points are as follows: definition of transmission frame format
The format of the frame transmitted on the bus is shown in fig. 2. The frame format is illustrated as follows:
frame start symbol: 8 bits, value 8' h00, for identifying the start of a frame;
frame synchronization symbol: 8 bits, value bit 8' hAA, for clock recovery from the node;
frame type: 8 bits, the frame type value is encoded as follows:
8' hff: and the control frame is used for polling whether the node is in an active state. After receiving the control frame, the slave node transmits a drive control response frame to the bus;
8' hf 0: and the control response frame is used for handling the control frame of the main node. And after receiving the control frame from the node, driving a control response frame to the bus. The control frame and the response control frame appear in pairs, and the specific format and timing relationship are shown in fig. 3.
8' hf5 write command frame for the master node to write data to the slave node. The write command frame is the same as the standard transport frame format of fig. 2.
8' hf 6: and the read command frame is used for sending the read command to the slave node by the master node.
8' hf 7: a read command response frame for sending read data from the node onto the bus. The read command frame and the read command response frame appear in pairs, and the format and timing relationship of the two are shown in fig. 4.
Frame length: 8 bits, indicating the number of bytes of the data payload section, in units of 16 bits, i.e. 2 bytes. A 0 indicates no data payload, a 1 indicates 2 bytes for the data payload portion, a 2 indicates 4 bytes for the data payload portion, …, and so on, and a maximum of 255 indicates 510 bytes for the data payload. In a specific implementation, the maximum value of the frame length may be defined as 128, that is, the data load is 256 bytes at maximum;
destination node address/slave node address: 16 bits, consisting of 8-bit box number + 8-bit slot address.
Data loading: the length is determined by the frame length, and the specific content is analyzed by software;
and (4) checking codes: 16 bits are check codes generated according to frame types, frame lengths, target node addresses, data loads and the like.
The frame transmission on the bus is initiated by the master node, and the response frames of the slave nodes are responded 8 clock cycles after the control frame or the command frame is received. If the slave node does not detect a signal on the bus within 64 bus cycles, it is determined that the slave node is not on the bus. The response frame is spaced above 32 bus clock cycles from the new control or command frame.
The key points are as follows: transmission clock frequency determination
The reference clock frequency for all nodes on the bus is 100 MHz. The clock frequencies supported on the bus are: 1MHz, 10MHz, 25MHz, 50MHz, 100MHz, etc. After the node is connected to the bus, firstly, a frame start character on the bus is determined, and the bus is characterized in that a falling edge appears after a period of idle state (no device drives the bus, and a signal output to the FPGA by an M-LVDS drive chip is 1), and then a rising edge appears. The number of cycles of the bus clock can be determined by counting the number of cycles between two edges with reference to a clock (100 MHz). For example, if the counter value between two edges is above 750, then it can be inferred that the bus transmission clock frequency is 1 MHz; if the counter value is between 75 and 85, the bus clock frequency can be preliminarily inferred to be about 10 MHz. Based on the frame start, only the transmission clock frequency of the bus can be preliminarily guessed. The transmission clock frequency of the bus is further confirmed according to the frame synchronization symbol.
After the slave node is connected to the bus, 2-3 frames may be passed before the bus transmission clock frequency is determined.
The key points are as follows: turnover rate of bus signal
For frame transmission, starting from the type of a frame and ending the check code of the frame, if 5 continuous 0 or 1 occurs, a bit bar code is automatically inserted, so that a sufficient turnover rate on a bus signal is ensured, 0 or 1 on the bus for a long time cannot occur, and a node is mistakenly judged as the slave device does not exist.
The points 7 are as follows: generation of frame check code
The objects covered by the check code comprise frame types, frame lengths, target node addresses, data loads and the like. The check code is generated using a CRC16_ CCITT polynomial: x 16+ x 12+ x 5+ 1.
The key points are as follows: reception of frames
After the node judges the frequency of the BUS clock, the BUS clock BUS _ CLK corresponding to the frequency of the BUS clock is recovered at first. On the receiving path, there are two sets of parallel receiving processing logics, and the working clocks of the two sets of logics are BUS _ CLK and-BUS _ CLK respectively, namely, the inversion of the BUS clock and the BUS clock. Both sets of receiving logic will generate a verification result. If the check results of the two sets of receiving logics are correct, taking the BUS _ CLK path of received data for further processing; if one set of check codes is correct and one set of check codes is incorrect, taking the path of the correct check codes; if the two sets of check codes are incorrect, the received data is discarded, and no response is made.
The 8 points are main technical points for realizing the communication system realization method based on the M-LVDS bus. In particular implementations, some specific details, such as the use of a "ping-pong FIFO" on the receive path, etc., will be used and will not be described in detail herein.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (9)
1. A multi-board communication system based on M-LVDS bus is characterized by comprising: the system comprises an M-LVDS bus, an M-LVDS drive chip and an M-LVDS controller;
the M-LVDS controller outputs a digital signal of control and data to an M-LVDS driving chip;
the M-LVDS driving chip realizes the conversion between a digital signal and a differential level signal;
the M-LVDS bus can transmit H/L level signals;
the M-LVDS bus and the sending channel are correspondingly a receiving channel, and in the receiving direction, the M-LVDS driving chip converts the H/L level signal on the M-LVDS bus into a digital signal and submits the digital signal to the M-LVDS controller.
2. The M-LVDS bus based multi-board communication system according to claim 1, further comprising: a board card component;
the M-LVDS driving chip and the M-LVDS controller are arranged on the board card part;
the board card component is connected with the M-LVDS bus.
3. The M-LVDS bus based multi-board communication system according to claim 1 wherein the number of the board components is one or more;
the plurality of board card components are connected with the M-LVDS bus.
4. The M-LVDS bus based multi-board communication system according to claim 1 wherein each node on the M-LVDS bus is capable of initiating a transmission transaction.
5. The M-LVDS bus based multi-board communication system according to claim 4, wherein each node on the M-LVDS bus is provided with a unique chassis number and slot number.
6. The multi-board communication system according to claim 4, wherein the master node on the M-LVDS bus is capable of monitoring the transmitted control frame while transmitting the control frame.
7. The multi-board communication system according to claim 4, wherein the transmission frame format is defined according to the M-LVDS bus transmission frame format definition control information, and the M-LVDS bus transmission frame format definition result information is obtained.
8. The M-LVDS bus based multi-board communication system according to claim 5, wherein the reference clock frequency of all nodes on the M-LVDS bus is 100 MHz.
9. A multi-board communication method based on an M-LVDS bus, characterized in that the multi-board communication system based on the M-LVDS bus according to any one of claims 1 to 8 is used to perform multi-board communication based on the M-LVDS bus.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114221903A (en) * | 2021-11-30 | 2022-03-22 | 新华三技术有限公司合肥分公司 | Data transmission method and device |
| CN114221903B (en) * | 2021-11-30 | 2024-03-12 | 新华三技术有限公司合肥分公司 | Data transmission method and device |
| CN115314070A (en) * | 2022-08-09 | 2022-11-08 | 浙江中控信息产业股份有限公司 | Cascade type high-speed long-line transmission device |
| CN115314070B (en) * | 2022-08-09 | 2024-02-09 | 浙江中控信息产业股份有限公司 | Cascaded high-speed long-line transmission device |
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