JPH11298450A - Serial data transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To request retransmission without an intervention of a receiving side CPU by transmitting to a transmitting side a signal showing that a receiving buffer overflows instead of a parity error signal. SOLUTION: Received data is transferred to a terminal side CPU 10 after it is once stored in a receiving buffer 14 of a receiving part 11. When the buffer 14 overflows, a receiving control circuit 12 generates an overflow signal without the intervention of the CPU 10. A receiving buffer overflow signal detected by the circuit 12 is inputted to an error timing generating circuit 16 and an error signal is produced in the same manner as a parity error time. The error signal is subjected to OR processing at the OR gate 33 of a port part 31 and is outputted to a transmitting and receiving terminal through an output buffer 34. A transmitting end repeats retransmission of error data according to the signal entry.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer controller for a transmission / reception system for transmitting / receiving serial data, and more particularly, to a serial data transfer controller having means for a receiving side to notify a parity error to a transmitting side.

[0002]

2. Description of the Related Art There is an IC card as an alternative to a conventional credit card having a magnetic stripe. The IC card is a card having an IC memory and capable of inputting and outputting data, and generally has a controller unit and a transmission / reception function in addition to the memory, and has a function as a terminal.

[0003] The serial data transfer controller used for transmission and reception of an IC card has a standard for a communication system and a data frame format. Especially,
The serial data transfer controller used in the ISO-7816 compliant smart card has a full duplex asynchronous communication function and uses a common data frame format and communication speed on the transmission side and the reception side. It has been standardized.

FIG. 5 shows a configuration of a conventional serial data transfer controller, and a CPU as an upper device for controlling the serial data transfer controller.
(Central Processing Unit)
It is a block diagram shown with. The serial data transfer controller receives a data sent from the CPU 10 to the CPU 10, a transmission unit 21 sends data transmitted from the CPU 10, and inputs / outputs data input / output from a transmission / reception terminal according to an input signal and an output signal. And a port unit 31.

[0005] The receiving unit 11 includes a parity check circuit 15 for performing a parity check of the received serial data input from the port unit 31, a reception shifter 13 for converting the received serial data into reception parallel data, and a parallel transmission from the reception shifter 13. A reception buffer 14 for temporarily storing data, an error timing generation circuit 16 for generating an error signal at a predetermined timing when a parity error occurs, and a reception control circuit 1 for controlling these reception operations
2 is provided.

The transmission unit 21 includes a transmission buffer 23 for temporarily storing transmission data input from the CPU 10, a transmission shifter 24 for converting data from the transmission buffer 23 into transmission serial data, and both the transmission buffer 23 and the transmission shifter 24. Is provided with a transmission control circuit section 22 for controlling the operation of.

The port section 31 includes an OR gate 33 for ORing transmission serial data and an error signal, an input buffer 32 for receiving an input signal from a transmission / reception terminal, and an output buffer 34 for transmitting an output signal ORed by the OR gate 33. Have.

In the conventional serial data transfer controller, when the result of the parity check is an error, a parity error signal is output to the error timing generation circuit, and the error timing generation circuit 16 outputs the error in a predetermined data frame format (FIG. 3). Outputs character data including signal ON.

In the serial data transfer controller, when the reception buffer overflows, the reception control circuit 12 outputs an overflow interrupt signal to its own CPU 10 to notify the occurrence of overflow of the reception buffer 14. After that, the receiving CPU 1
0 receives this and transmits a retransmission request command for re-reception by interrupt processing. The transmitting-side controller retransmits data according to the retransmission request command.

[0010]

In the conventional serial transfer controller, every time the reception buffer overflows, a request for data retransmission is made by interrupt processing based on the control of the CPU on the receiving side, and the request is sent to the controller on the transmitting side. Therefore, there is a disadvantage that it takes time until the receiving CPU makes a retransmission request.

The present invention has been made in view of the above circumstances, and provides a serial data transfer controller capable of requesting retransmission without the intervention of a receiving CPU or by limiting the intervention of a CPU when a reception buffer overflows. The purpose is to provide.

[0012]

In order to achieve the above object, a serial data transfer controller according to the present invention performs a reception buffer for converting serial input data into parallel data and a parity check of the serial input data. A parity check circuit for transmitting a parity error signal to a transmitting side that has transmitted the serial input data when a parity error is detected. Is transmitted to the transmitting side in place of the parity error signal instead of the parity error signal.

Further, in the serial data transfer controller of the present invention, a reception buffer for temporarily storing received data and transferring it to a host device, an overflow detection circuit for generating an overflow signal when the received buffer overflows, A receiving unit comprising: a parity error detection circuit for detecting a parity error; a parity error notification circuit for notifying a parity error signal to a transmission side when the parity error detection circuit detects a parity error; and a notification of the parity error from the reception side. A serial data transfer controller having a transmission unit for retransmitting data upon receipt of the data, a selector for selecting the overflow signal or the parity error signal, and wherein the overflow detection circuit replaces the parity error signal with the cell. And notifying the transmitting side output connectors.

The serial data transfer controller of the present invention has a counting section for counting an overflow signal, and can generate an interrupt signal to a higher-level device when the count by the counting section reaches a predetermined number. Since the CPU is involved only at the time of an overflow that is considered to be difficult to recover, the occupation time of the CPU is kept low.

In the serial data transfer controller of the present invention, the host device may be a CPU or a DMA. An IC card according to the present invention includes the above serial data transfer controller, has a transmitting / receiving function, and has a function as a host.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a serial data transfer controller according to a first embodiment of the present invention, together with a CPU constituting a higher-level device for controlling the serial data transfer controller.

The serial data transfer controller according to the present invention comprises a receiving section 11 for receiving data, a transmitting section 21 for transmitting data, and a port section 3 for separating transmitted / received data.
And 1. The receiving unit 11 transfers the received data to the CPU 10 when receiving the data, and
1 has a function of transmitting transmission data from the CPU 10, and the port unit 31 has a function of dividing an input signal sent from the outside and an output signal from the inside.

The receiving section 11 includes a receiving shifter 13 for converting received serial data input from the port section 31 into received parallel data, a parity check circuit 15 for performing parity check of the received serial data, and a receiving shifter 13. Is stored once and the CPU 10
, An error timing generation circuit 16 (parity error notification circuit) that generates an error signal when a parity error occurs and an overflow error occurs in the reception buffer 14, and a reception operation of these circuits. And a reception control circuit 12 for controlling the

When the input buffer 32 receives the transmission data, the CPU 10 outputs a transmission data write signal to the transmission control circuit 22. When the input buffer 32 receives the received serial data, it outputs a received data read signal to the reception control circuit 12.

The transmission unit 21 includes a transmission buffer 23 for temporarily storing transmission data input from the CPU 10,
A transmission shifter 24 converts data from the transmission buffer into transmission serial data, and a transmission control unit 22 that controls the operation thereof.

The port section 31 transmits transmission serial data,
An OR gate 33 for ORing a parity error signal or an overflow signal, an input buffer 32 for receiving an input signal from a transmission / reception terminal, and an OR gate 33
And an output buffer 34 for transmitting the output signal.

FIG. 2 is a block diagram showing a connection state between the transmission side (serial data controller A) of the host in the transmission mode and the terminal side (smart card) in the reception mode (serial data controller B). A and the serial data controller B have similar configurations and functions.

The serial data controllers A and B shown in FIG. 2 temporarily store the received data in FIG. 1 in the receiving buffer 14 of the receiving section 11 and then transfer the data to the CPU. When the receiving buffer 14 overflows, the overflow signal is output without intervention of the CPU. , A parity check circuit 15 for detecting a parity error of received data, and a parity error notification circuit for notifying a transmission side of a parity error signal when the parity check circuit 15 detects a parity error. The transmission / reception system includes a transmission unit on the transmission side that retransmits data upon receiving a parity error notification from the reception side.

When the transmission control circuit unit 22 of the serial data controller A receives the transmission data write signal from the CPU 10, it generates a tx_write signal and stores the transmission data in the transmission buffer 23. Thereafter, the transmission control circuit 22 generates a tx_load signal, loads the transmission parallel data in the transmission buffer 23 into the transmission shifter 24, converts it into serial data, and
_Clock is supplied to the transmission shifter 24. The transmission serial data is output to the port unit 31 by the transmission shifter 24 in synchronization with the transmission serial clock tx_clock. In the port section 31, the signal is OR-processed with the error signal which is at the L level at the time of transmission, and then output to the transmission / reception terminal through the output buffer.

In the serial data controller B, the data received from the transmission / reception terminal is input to the reception unit 11 via the input buffer 32 in the port unit 31. Receiver 1
1 in the reception control circuit 12 in the reception basic clock rx_
clock, sample the received serial data,
When the start bit is detected, the reception serial clock rx_clock is output to the reception shifter 13. The reception shifter 13 takes in the received serial data in synchronization with rx_clock. The reception control circuit 12
After outputting rx_clock for one character,
Generate an rx_load signal. The reception parallel data output from the reception shifter 13 is latched at the timing of the rx_load signal and stored in the reception buffer 14. When the reception control circuit 12 receives the reception data read signal, the reception data in the reception buffer 14 is transmitted to the terminal CPU.
It is output to 10.

FIG. 3 is a diagram showing a configuration of a data frame format when transmitting and receiving serial data standardized in the ISO7816 standard. (A) shows a format when no parity error occurs, and (b)
Indicates a format when a parity error occurs. In this example, the data frame format is a total of 1 for the start bit, the data bit, and the parity bit.
0.5 bits are assigned to error bits, 1.5 bits are assigned to stop bits, and 1 bit is assigned to stop bits.

The parity check method according to the ISO 7816 standard and error recovery at the time of a parity error are processed as follows. Parity check circuit 1
5, rx_clo output from the reception control circuit 12
The parity check of the received serial data is performed by the ck signal. If the parity check results in an error,
A parity error signal is output to the error timing generation circuit 16, and the error timing generation circuit 16 outputs a parity error signal as shown in FIG.
The error signal is output at the H level in the data frame format shown in FIG.

At the time of reception, the transmission serial data is at the L level. When there is no error, the error signal is also at the L level, the output of the OR gate 33 is also at the L level, and the output buffer 34 is inactive. It is in the input state. At the time of the parity error, the error signal becomes H level, is OR-processed by the OR gate 33 of the port unit 31, and is output to the transmission / reception terminal through the output buffer 34.

The transmission control circuit 12 of the transmission side serial data controller A of the host judges the error signal in the frame of the error signal shown in FIGS. 3A and 3B. Since it has the function of retransmitting the same data as before, a retransmission request can be made automatically without performing retransmission processing in the processing of the CPU 10.

In the terminal (smart card) serial data controller B, before the data in the reception buffer 14 is read by the reception data read signal, the reception control circuit 12 detects the start bit of the next reception serial data. Generate an overflow interrupt signal.

Returning to FIG. 1, a reception buffer overflow signal detected by the reception control circuit 12 is input to the error timing generation circuit 16, and when the signal is turned on, the data frame shown in FIG. Generates an error signal as in the case of a parity error. This eliminates the need for the retransmission process via the receiving CPU when the receiving buffer overflows, which has been required conventionally. When this error signal is received by the host transmission side, the error data is retransmitted as in the case of receiving the parity error signal as error processing. According to the above configuration, a parity error signal can be generated by the input of the reception buffer overflow signal, and the host transmission side repeats retransmission of the error data by inputting the signal, so that a reception error of the reception side smart card can be prevented. Further, automatic retransmission of data, which was conventionally possible only at the time of a parity error, can be performed at the time of overflow of the reception buffer.

[Second Embodiment] FIG. 4 is a block diagram showing a configuration of a serial data transfer controller according to a second embodiment of the present invention. This figure differs from the first embodiment in that the receiving unit of the terminal (smart card) on the receiving side is provided with an interrupt generation circuit 17 for counting the number of continuous overflows. Other configurations are the same as those of the first embodiment.

Since the receiving section 11 on the terminal side (smart card) includes the interrupt generation circuit 17 for counting the number of continuous overflows, the count is received within the number of retransmissions on the host transmitting side when a parity error occurs. When data cannot be captured, an overflow interrupt signal is generated for the CPU 10 to notify the CPU 10 of an unrecoverable error by the retransmission function on the transmission side. In this way, by operating the CPU only when necessary, the load required for the overflow error processing of the CPU can be reduced.

Although the present invention has been described based on the preferred embodiment, the serial data transfer controller of the present invention is not limited to the configuration of the above-described embodiment, but is limited to the above-described embodiment. The serial data transfer controller obtained by making various modifications and changes from the configuration described in the above is also included in the scope of the present invention.

For example, the host device of the above embodiment is a CPU
DMA (Direct Memory Acc)
ess). The IC of the above embodiment
The card includes a smart card, and in this case, it can also function as a card host. As an application example of the smart card, there is a provision of billing information in mail-order sales in addition to the function of the ID card. There is also an application example as an alternative to the conventional bankbook.

[0036]

According to the serial data transfer controller of the present invention, it is possible to provide a serial data transfer controller capable of requesting retransmission without the intervention of the receiving CPU or with limited intervention of the CPU when the overflow of the reception buffer occurs. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a serial data transfer controller according to a first embodiment of the present invention and a CPU that controls the controller.

FIG. 2 is a block diagram illustrating a connection example between a host and a terminal.

3A and 3B are diagrams illustrating a configuration of a general data frame format, where FIG. 3A illustrates a case where a parity error does not occur, and FIG. 3B illustrates a case where a parity error occurs.

FIG. 4 is a block diagram showing a configuration of a serial data transfer controller according to a second embodiment of the present invention and a CPU for controlling the serial data transfer controller;

FIG. 5 is a block diagram showing a configuration of a conventional serial data transfer controller and a CPU for controlling the configuration.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 CPU 11 reception unit 12 reception control circuit 13 reception shifter 14 reception buffer 15 parity check circuit 16 error timing generation circuit 17 interrupt generation circuit 21 transmission unit 22 transmission control circuit 23 transmission buffer 24 transmission shifter 31 port unit 32 input buffer 33 OR Gate 34 output buffer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 25/40 H04L 25/40 E

Claims (10)

[Claims] 1. A receiving buffer for converting serial input data into parallel data, and a parity error signal is transmitted to a transmitting side which transmitted the serial input data when a parity error of the serial input data was detected by detecting a parity error of the serial input data. A serial data transfer controller having a receiving unit provided with a parity check circuit unit, wherein when the receiving buffer overflows, a signal indicating that the receiving buffer has overflowed is sent to the transmitting side instead of the parity error signal. A serial data transfer controller, characterized in that: 2. The apparatus according to claim 1, further comprising: a counting section for counting the number of times the reception buffer overflows, wherein when the counting by the counting section reaches a predetermined number, an interrupt signal is generated to a host device on the receiving side. 2. The serial data transfer controller according to 1. 3. The system according to claim 1, wherein said higher-level device is a DMA.
Or the serial data transfer controller according to any one of 2. 4. An IC card comprising the serial data transfer controller according to claim 1. 5. An IC card having the serial data transfer controller according to claim 1 and a transmission / reception function and having a function as a host. 6. A receiving buffer for temporarily storing received data and transferring it to a host device, an overflow detecting circuit for generating an overflow signal when the receiving buffer overflows, and a parity error detecting circuit for detecting a parity error of the received data. A receiving unit including a parity error notifying circuit that notifies a transmitting side of a parity error signal when the parity error detecting circuit detects a parity error; and a transmitting side that retransmits data when receiving the parity error notification from the receiving side. And a selector for selecting the transmission serial data and the overflow signal or the parity error signal, wherein the parity error notification circuit replaces the parity error signal. The cell Serial data transfer controller and notifies the sender of the output connectors. 7. The apparatus according to claim 1, further comprising a counting unit for counting the number of times the reception buffer overflows, wherein an interrupt signal is generated to a higher-level device on the receiving side when the count by the counting unit reaches a predetermined number. 7. The serial data transfer controller according to item 6. 8. The system according to claim 6, wherein said higher-level device is a DMA.
Or a serial data transfer controller according to any one of claims 7 to 7. 9. An IC card comprising the serial data transfer controller according to claim 6. 10. An IC card having the serial data transfer controller according to claim 6 and a transmission / reception function and having a function as a host.