JP2008269335A - Data transfer integrated circuit and data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve communication efficiency when occurring of a communication error in data transfer. <P>SOLUTION: When image data is read from a memory 1 and written to an HDD 4, an HDD I/F 3 accumulates the image data transferred by a DMAC 2 in a retry buffer, and writing of the image data to the HDD 4 is performed after completion of accumulation for one transfer portion of data. If a serial communication error occurs at that time, the image data accumulated in the retry buffer within the HDD I/F 3 is retransmitted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data transfer integrated circuit that includes an interface for transmitting / receiving information to / from the outside, such as an ASIC (Application Specific Integrated Circuit), for example, and a data transfer apparatus including the integrated circuit.

Conventionally, since the HDD (Hard Disk Drive) interface is parallel ATA (AT Attachment), communication errors such as CRC (Cyclic Redundancy Check) errors are very few and occur only when there is a real problem. On the other hand, in the case of the S-ATA HDD interface, the bit error rate is 10 ^{-12 according} to the standard because of high-speed (1.5 / 3/6 Gbps) serial communication, which is very high compared to parallel ATA.

In addition, as an example of a device for controlling the number of retries in data recording and reproduction, a means for detecting a defect occurring in the data recording area of the recording medium and a defect corresponding to the size of the data recording or reproducing unit And a means for changing the number of times data could not be recorded or reproduced on the recording medium, which is counted when detecting (see, for example, Patent Document 1).
JP 2000-149464 A

  However, when a serial communication error occurs in the above-described S-ATA HDD interface, an interrupt is currently generated. However, for example, when the communication speed on S-ATA is 1.5 Gbps, an interrupt occurs once every 11 minutes. Will occur. For this reason, if this interrupt is processed by software and re-transmission / reception is performed, there is a problem that the efficiency is low.

  Further, the above-mentioned Patent Document 1 is for efficiently recording or reproducing data without losing the continuity of the data, and is efficient by processing an interrupt when a communication error occurs by software. It was not even considered to improve the badness.

  The present invention has been made in view of such a situation, and an object thereof is to provide a data transfer integrated circuit and a data transfer device capable of improving communication efficiency when a communication error occurs in data transfer.

  In order to achieve such an object, a data transfer integrated circuit according to the present invention includes an interface for performing data communication with another device, has a retry buffer, and when a communication error occurs in data communication via the interface, By using the retry buffer, retry processing is performed by hardware without software intervention.

  The data transfer integrated circuit according to the present invention includes an interface for performing data communication with other devices, has a restart function for DMAC (Direct Memory Access Controller), and a communication error in data communication via the interface. When the error occurs, the retry processing may be performed by hardware without intervention of software by restarting the DMAC.

  It is preferable to include an interrupt generation means for generating an interrupt according to the number of occurrences of communication errors in data communication via the interface.

  There may be provided a communication speed control means for reducing the communication speed of the interface according to the number of occurrences of communication errors in data communication via the interface.

  Preferably, the interrupt generation means interrupts when a communication error in data communication via the interface occurs a predetermined number of times.

  When a communication error in data communication via the interface occurs a predetermined number of times, the communication speed control means may decrease the communication speed of the interface.

  A number setting means for receiving the setting of the number of occurrences of communication errors until the post-processing is performed, and when the communication error in the data communication via the interface occurs the number of times set by the number setting means, the interrupt generation means interrupts It may be done.

  A number of times setting means for receiving the setting of the number of occurrences of communication errors until the post-processing is performed, and when the communication error in the data communication through the interface occurs the number of times set by the number of times setting means, the communication speed control means The communication speed by the interface may be reduced.

  A data transfer apparatus according to the present invention includes the above-described data transfer integrated circuit according to the present invention, and has a function of writing / reading data to / from a hard disk via the interface.

  As described above, according to the present invention, it is possible to improve communication efficiency when a communication error occurs during data transfer.

  Next, an embodiment in which a data transfer integrated circuit and a data transfer device according to the present invention are applied to an ASIC having an S-ATA interface and an electronic multifunction device will be described in detail with reference to the drawings.

First, the basic configuration and operation of the S-ATA interface part of the ASIC common to the embodiments of the present invention will be briefly described.
FIG. 1 is a diagram showing a part of the configuration of an ASIC installed in an electronic multifunction peripheral (data transfer apparatus) according to this embodiment.

  The memory 1 is a memory for temporarily storing various data such as image data handled by the electronic multi-function peripheral according to the present embodiment and for the CPU to use as a work area.

  When reading image data from the HDD 4, the DMAC (Direct Memory Access Controller) 2 receives the image data from the HDD I / F (interface) 3 and writes it to the memory 1. When writing image data to the HDD 4, the image data is read from the memory 1, and the image data is transferred to the HDD I / F 3.

When reading image data from the HDD 4, the HDD I / F 3 reads the image data from a plurality of connected HDDs 4, performs appropriate data arrangement processing, and passes the data to the DMAC 2. When writing image data to the HDD 4, the image data is received from the DMAC 2, divided into data arrays corresponding to a plurality of connected HDDs, and passed to the HDD 4.
The ASIC according to this embodiment is connected to the HDD 4 via an S-ATA interface, and the HDD I / F 3 is an interface for high-speed serial communication. HDD_A / B / C / D is an HDD device conforming to the S-ATA standard.

  In the configuration of this embodiment described above, the retry buffer and its control circuit, the serial communication error count and its control circuit are included in the HDD I / F 3 portion.

[First Embodiment]
Next, a first embodiment of the present invention will be described with reference to FIGS.
In the first embodiment, a retry buffer is provided in the HDD I / F 3.

Here, consider an electronic multi-function peripheral (having a copy function, a printer function, a facsimile function, a scanner function, etc.) having an HDD interface. The ASIC of the electronic multifunction peripheral has a plurality of S-ATA interfaces, and has a function of writing / reading image data or other data handled by the electronic multifunction peripheral to / from the HDD 4.
An ASIC having such an S-ATA interface, having a retry buffer, and configured to automatically perform retry processing in hardware without software intervention when an S-ATA I / F serial communication error occurs. The

Next, the operation of the first embodiment will be described with reference to the flowchart of FIG.
First, the case of reading from the memory 1 and writing image data to the HDD 4 will be described.
When the DMAC 2 is activated by software, the DMAC 2 issues a write command to the HDD 4 via the HDD I / F 3. In parallel with this, the DMAC 2 reads the image data from the designated memory address and transfers it to the HDD I / F 3. The HDD I / F 3 stores the image data transferred from the DMAC 2 in the retry buffer, and writes the image data to the HDD 4 when storage for one transfer is completed. At this time, if a serial communication error occurs, the image data stored in the retry buffer in the HDD I / F 3 is retransmitted.

Next, a case of reading from the HDD 4 and writing image data to the memory 1 will be described.
When the DMAC 2 is activated by software, the DMAC 2 issues a read command to the HDD 4 via the HDD I / F 3. The image data transmitted from the HDD 4 is temporarily stored in the retry buffer. If there is no serial communication error, the DMAC 2 writes the image data stored in the retry buffer to the designated memory address. At this time, if a serial communication error occurs, the image data stored in the retry buffer is discarded without being transferred to the DMAC 2.

  According to the first embodiment described above, since re-transmission / reception is automatically performed by hardware using a retry buffer without intervention of software processing, it is possible to avoid a reduction in efficiency.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS.
In the second embodiment, the HDD I / F 3 has a function capable of restarting the DMAC 2 when it detects a serial communication error.

  More specifically, the ASIC has a restart function to the DMAC 2 and automatically performs a retry process by hardware without any software when a serial communication error of the S-ATA I / F occurs.

Next, the operation of the second embodiment will be described with reference to the flowchart of FIG.
First, the case of reading from the memory 1 and writing image data to the HDD 4 will be described.

  When the DMAC 2 is activated by software, the DMAC 2 issues a write command to the HDD 4 via the HDD I / F 3. In parallel with this, the DMAC 2 reads the image data from the designated memory address and transfers it to the HDD I / F 3. The HDD I / F 3 writes the image data transferred from the DMAC 2 to the HDD 4. At this time, if a serial communication error occurs, the HDD I / F 3 issues a restart request to the DMAC 2. Receiving this, the DMAC 2 temporarily stops the transfer being executed and restarts again. After restarting, start over from the write command issue procedure.

Next, a case of reading from the HDD 4 and writing image data to the memory 1 will be described.
When the DMAC 2 is activated by software, the DMAC 2 issues a read command to the HDD 4 via the HDD I / F 3. If there is no serial communication error, the received image data is written by the DMAC 2 to the designated memory address. If a serial communication error occurs, the HDD I / F 3 issues a restart request to the DMAC 2. Receiving this, the DMAC 2 temporarily stops the transfer being executed and restarts again. After restarting, start over from the read command issue procedure.

  According to the second embodiment described above, since retransmission processing can be performed by hardware without using a retry buffer for retransmission, avoiding an increase in circuit scale and avoiding a decrease in efficiency. It becomes possible.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS.
In the third embodiment, a function for counting the number of occurrences of serial communication errors in the HDD I / F 3, a function for comparing the count value with a fixed value, and a function for generating an interrupt are added. Yes.
More specifically, in the ASIC in the first or second embodiment described above, an interrupt is generated when a serial communication error occurs a specified number of times.

Next, the operation of the third embodiment will be described with reference to the flowchart of FIG.
Here, the case where the image data is read from the memory 1 and the image data is written to the HDD 4 is the same as the case where the image data is read from the HDD 4 and the image data is written to the memory 1. Will be described.

When a serial communication error occurs, the HDD I / F 3 increments the error occurrence count and compares it with a predetermined fixed value. If it is equal to or less than the fixed value, the error processing of the first or second embodiment is performed. When the fixed value is exceeded, the DMAC 2 is stopped and an interrupt is generated (interrupt generation means).
For example, the software acquires the status of the HDD and prompts the user to replace the HDD in the interrupt process.

According to the third embodiment described above, when a serial communication error occurs a specified number of times, an interrupt can be generated. Therefore, the HDD device check is performed by this interrupt, and there is a quality problem in the HDD. In the event of a failure, it will be possible to notify the exchange.
Further, when the HDD quality is poor, the serial communication error can be reduced by replacing the HDD, and the performance of the system can be maintained.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIGS.
In the fourth embodiment, a function capable of setting a communication speed with the HDD is added to the HDD I / F 3.

  More specifically, in the ASIC in the first or second embodiment described above, the communication speed of the S-ATA interface is reduced when a serial communication error occurs a specified number of times.

Next, the operation of the fourth embodiment will be described with reference to the flowchart of FIG.
Here, the case where the image data is read from the memory 1 and the image data is written to the HDD 4 is the same as the case where the image data is read from the HDD 4 and the image data is written to the memory 1. I'll give you that.

  When a serial communication error occurs, the HDD I / F 3 increments the error occurrence count and compares it with a predetermined fixed value. If it is equal to or less than the fixed value, the error processing of the first or second embodiment is performed. If the fixed value is exceeded, the S-ATA communication speed is reduced by one step (for example, 3.0 Gbps → 1.5 Gbps), and the HDD device is reset. After the reset, negotiation is executed between the HDD I / F 3 and the HDD device, and re-linking is performed at a communication speed shifted down by one level (communication speed control means).

  After this negotiation is completed, the HDD I / F 3 issues a restart request to the DMAC 2. Receiving this, the DMAC 2 temporarily stops the transfer being executed and restarts again. After restarting, start over from the write command issue procedure.

  According to the above-described fourth embodiment, when a serial communication error occurs a specified number of times, the communication speed of the S-ATA interface can be reduced, so that the serial communication error can be reduced.

[Other Embodiments]
In the third and fourth embodiments described above, a register may be provided in the HDD I / F 3 so that the prescribed number of serial communication errors can be set by software (number setting means).
That is, in the ASIC as the third and fourth embodiments described above, the prescribed number of serial communication errors may be set to an arbitrary number.

As an operation in this configuration example, first, regarding the setting of the number of times until the processing at the time of occurrence of the serial communication error in the third and fourth embodiments described above is performed, a setting input from the user is performed by an input unit (not shown) or the like. receive.
Then, in the processing when the serial communication error occurs in the third and fourth embodiments described above, the error occurrence count is compared with the specified count set in the register. Other operations are the same as those in the third and fourth embodiments described above.
Therefore, for the operations shown in FIGS. 4 and 5 described above, the specified number of times in the figure can be arbitrarily set by the register.

  According to the configuration example described above, the specified number of serial communication errors can be set to an appropriate value, so that the HDD device replacement time and communication speed can be appropriately reduced.

Each of the above-described embodiments is a preferred embodiment of the present invention, and the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.
For example, in each of the above-described embodiments, the electronic multifunction peripheral has been described. However, for example, an image forming apparatus such as a copier, a printer, a facsimile, or a scanner may be used.
Further, the present invention can be similarly applied to various fields as an HDD I / F error processing method or an S-ATA I / F error processing method in an electronic multifunction peripheral.

It is a block diagram which shows the structural example of ASIC as embodiment of this invention. It is a sequence diagram which shows the operation example by 1st Embodiment. It is a sequence diagram which shows the operation example by 2nd Embodiment. It is a sequence diagram which shows the operation example by 3rd Embodiment. It is a sequence diagram which shows the operation example by 4th Embodiment.

Explanation of symbols

1 Memory 2 DMAC
3 HDD I / F
4 HDD

Claims (9)

It has an interface for data communication with other devices,
Has a retry buffer,
A data transfer integrated circuit characterized in that, when a communication error occurs in data communication via the interface, retry processing is performed by hardware without using software by using the retry buffer. It has an interface for data communication with other devices,
Has a restart function to DMAC (Direct Memory Access Controller),
A data transfer integrated circuit characterized in that, when a communication error occurs in data communication through the interface, retry processing is performed by hardware without software intervention by restarting the DMAC.   3. The data transfer integrated circuit according to claim 1, further comprising interrupt generation means for generating an interrupt according to the number of occurrences of a communication error in data communication via the interface.   3. The data transfer integrated circuit according to claim 1, further comprising a communication speed control means for reducing a communication speed of the interface according to the number of occurrences of communication errors in the data communication via the interface.   4. The data transfer integrated circuit according to claim 3, wherein said interrupt generation means interrupts when a communication error in data communication through said interface occurs a predetermined number of times.   5. The data transfer integrated circuit according to claim 4, wherein when a communication error in data communication through the interface occurs a predetermined number of times, the communication speed control means reduces the communication speed through the interface. A number setting means for receiving the setting of the number of occurrences of communication errors until the post-processing is performed,
4. The data transfer integrated circuit according to claim 3, wherein said interrupt generating means interrupts when a communication error in data communication through said interface occurs for a number of times set by said number setting means. A number setting means for receiving the setting of the number of occurrences of communication errors until the post-processing is performed,
5. The data transfer integration according to claim 4, wherein when a communication error in data communication through the interface occurs the number of times set by the number setting means, the communication speed control means reduces the communication speed by the interface. circuit.   9. A data transfer apparatus comprising the data transfer integrated circuit according to claim 1 and having a function of writing / reading data to / from a hard disk via the interface.

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