JPH0681014B2 - Flip-flop circuit - Google Patents
Flip-flop circuitInfo
- Publication number
- JPH0681014B2 JPH0681014B2 JP63107028A JP10702888A JPH0681014B2 JP H0681014 B2 JPH0681014 B2 JP H0681014B2 JP 63107028 A JP63107028 A JP 63107028A JP 10702888 A JP10702888 A JP 10702888A JP H0681014 B2 JPH0681014 B2 JP H0681014B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- nand circuit
- nand
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフリップフロップ回路に関する。TECHNICAL FIELD The present invention relates to a flip-flop circuit.
〔従来の技術〕 従来フリップフロップ回路には第５図に示す回路が用い
られていた。[Prior Art] Conventionally, a circuit shown in FIG. 5 has been used for a flip-flop circuit.
第５図において、はセット端子、はリセット端子、
φはクロック信号、Ｑは正出力、は負出力である。
が低レベル（以下「０」という）でが高レベル（以下
「１」という）のときが「０」になると、Ｑが
「１」，が「０」になる。またが「１」でが
「０」のときが「０」になると、Ｑが「０」，が
「１」になる。が「１」でが「１」のとき、又は
が「１」のときは、Ｑ及びは前の状態を保持する。In FIG. 5, is a set terminal, is a reset terminal,
φ is a clock signal, Q is a positive output, and is a negative output.
When is low level (hereinafter referred to as “0”) and is high level (hereinafter referred to as “1”), it becomes “0”, and Q becomes “1” and becomes “0”. Also, when is “1” and is “0”, it becomes “0”, so that Q becomes “0” and becomes “1”. When is “1” and is “1”, or when is “1”, the previous states of Q and are retained.
上述した従来のフリップフロップ回路は、第６図のタイ
ミングチャートに示すようにの立下りと共にが立上
るとOR回路２の出力は中間レベルまで下降し、その後
「１」になる。この場合「１」から「０」に向っていた
NAND回路３の出力は中間値にとどまる。またNAND回路３
の出力を入力とするNAND回路４の出力は「０」から
「１」に向うが中間値にとどまる。In the conventional flip-flop circuit described above, the output of the OR circuit 2 drops to an intermediate level when the rising edge rises along with the falling edge as shown in the timing chart of FIG. 6, and then becomes "1". In this case, it was going from "1" to "0"
The output of the NAND circuit 3 remains at the intermediate value. Also NAND circuit 3
The output of the NAND circuit 4 which receives the output of the above goes from "0" to "1" but remains at the intermediate value.
第６図に示す，，の組合せは、第５図の論理回路
をMOSトランジスタで構成すると必ず生ずる。この中間
値を論理回路へ入力すると、ある回路では「０」と判定
し、他の回路では「１」と判定し、論理回路が誤動作
し、また、特にCMOS回路へ入力した場合Ｐ−MOS,N−MOS
に貫通電流が流れ、消費電力が増大するという欠点があ
る。The combination of and shown in FIG. 6 is always generated when the logic circuit of FIG. 5 is constituted by MOS transistors. When this intermediate value is input to the logic circuit, it is determined as "0" in one circuit and as "1" in the other circuit, the logic circuit malfunctions, and especially when it is input to the CMOS circuit, the P-MOS, N-MOS
There is a drawback in that a through current flows through and power consumption increases.
本発明のフリップフロップ回路は、リセット信号とクロ
ック信号を入力とする第１のOR回路およびセット信号と
クロック信号を入力とする第２のOR回路のそれぞれの出
力を第１及び第２のNAND回路へ入力し、第１のNAND回路
の出力を第２のNAND回路へ、また第２のNAND回路の出力
を第１のNAND回路へと入力し、第１又は第２のNAND回路
の出力とクロック信号を入力とする第３のNAND回路の出
力を、第１又は第２のNAND回路へ入力し、第３のNAND回
路の論理閾値を、第１及び第２のNAND回路よりも低く設
定している。In the flip-flop circuit of the present invention, the respective outputs of the first OR circuit receiving the reset signal and the clock signal and the second OR circuit receiving the set signal and the clock signal are used as the first and second NAND circuits. The output of the first NAND circuit to the second NAND circuit and the output of the second NAND circuit to the first NAND circuit, and the output of the first or second NAND circuit and the clock. The output of the third NAND circuit that receives the signal is input to the first or second NAND circuit, and the logical threshold value of the third NAND circuit is set lower than that of the first and second NAND circuits. There is.
第１図は本発明の第１の実施例を示す回路図である。第
１図において、はセット端子、はリセット端子、
はクロック、Ｑは正出力、は負出力である。OR回路1,
2、NAND回路3,4は第５図に示す従来例と同じものである
が、NAND回路５の論理閾値はNAND回路3,4よりも低く設
定してある。FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, is a set terminal, is a reset terminal,
Is a clock, Q is a positive output, and is a negative output. OR circuit 1,
2. The NAND circuits 3 and 4 are the same as those of the conventional example shown in FIG. 5, but the logical threshold of the NAND circuit 5 is set lower than that of the NAND circuits 3 and 4.
第２図に示すタイミングチャートのように、の立下り
と同時にが立上るとOR回路２に中間値が現れる場合が
ある。このときNAND回路４の出力は「０」から「１」に
向って変化し、一時的に中間値になる。As in the timing chart shown in FIG. 2, if the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the rising edge of the OR gate, an intermediate value may appear in the OR circuit 2. At this time, the output of the NAND circuit 4 changes from “0” to “1” and temporarily becomes an intermediate value.
前述したようにNAND回路５の論理閾値はNAND回路3,4よ
りも低く設定してあるので、NAND回路５は中間値を
「１」と判定し、が「１」なのでNAND回路５の出力は
「０」になる。従ってNAND回路４の出力は中間値から
「１」になり、NAND回路３の出力は中間値から「０」に
なる。このようにフリップフロップ回路の出力が中間値
にとどまることはない。As described above, since the logical threshold value of the NAND circuit 5 is set lower than that of the NAND circuits 3 and 4, the NAND circuit 5 judges that the intermediate value is "1", and since "1", the output of the NAND circuit 5 is It becomes "0". Therefore, the output of the NAND circuit 4 changes from the intermediate value to "1", and the output of the NAND circuit 3 changes from the intermediate value to "0". In this way, the output of the flip-flop circuit does not stay at the intermediate value.
第３図は本発明の第２の実施例を示す回路図である。第
３図においてはセット端子、はリセット端子、は
クロック、Ｑは正出力、は負出力である。OR回路1,
2、NAND回路3,4は第５図に示す従来例と同じものである
が、NAND回路５の論理閾値はNAND回路3,4よりも低く設
定してある。FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In FIG. 3, is a set terminal, is a reset terminal, is a clock, Q is a positive output, and is a negative output. OR circuit 1,
2. The NAND circuits 3 and 4 are the same as those of the conventional example shown in FIG. 5, but the logical threshold of the NAND circuit 5 is set lower than that of the NAND circuits 3 and 4.
第４図に示すタイミングチャートのように、の立下り
と同時にが立上るとOR回路２に中間値が現れる場合が
ある。このときNAND回路４の出力は「０」から中間値に
向い、NAND回路３の出力は「１」から中間値へ向うが、
前述したようにNAND回路５の論理閾値はNAND回路3,4よ
りも低く設定してあるので、NAND回路３の出力を「１」
と判定して、が「１」なのでNAND回路５の出力は
「０」になる。従ってNAND回路３の出力は再び「１」に
もどり、NAND回路４の出力は「０」にもどる。NAND回路
3,4の出力にはヒゲ状のパルスが出るので、インバータ
6,7を付加して除去している。このようにフリップフロ
ップの出力が中間値にとどまることはない。また、第３
図においてNAND回路５の出力をNAND回路４へ接続して
も、第１図においてNAND回路５の出力をNAND回路３へ接
続しても同様の効果が得られる。As shown in the timing chart of FIG. 4, an intermediate value may appear in the OR circuit 2 when rises at the same time as the fall of. At this time, the output of the NAND circuit 4 goes from "0" to the intermediate value, and the output of the NAND circuit 3 goes from "1" to the intermediate value.
As described above, since the logical threshold value of the NAND circuit 5 is set lower than that of the NAND circuits 3 and 4, the output of the NAND circuit 3 is set to "1".
Is judged to be "1", the output of the NAND circuit 5 becomes "0". Therefore, the output of the NAND circuit 3 returns to "1" again, and the output of the NAND circuit 4 returns to "0". NAND circuit
Since a whisker-shaped pulse appears at the output of 3, 4,
6,7 are added and removed. In this way, the output of the flip-flop does not stay at the intermediate value. Also, the third
Similar effects can be obtained even if the output of the NAND circuit 5 is connected to the NAND circuit 4 in the figure or if the output of the NAND circuit 5 is connected to the NAND circuit 3 in FIG.
以上説明したように、本発明は、入力信号の変化と同時
にクロック信号が変化しても出力には中間値を生じない
フリップフロップ回路を実現でき、その出力を入力とす
る論理回路に誤動作は生じない。また、CMOS回路におい
て貫通電流による消費電力の増大が抑えられるという効
果がある。As described above, the present invention can realize a flip-flop circuit that does not generate an intermediate value in the output even if the clock signal changes at the same time as the input signal changes, and malfunction occurs in the logic circuit that receives the output. Absent. Further, there is an effect that an increase in power consumption due to a through current can be suppressed in the CMOS circuit.
第１図は本発明の第１の実施例を示す回路図、第２図は
第１図の動作を説明するためのタイミングチャート、第
３図は本発明の第２の実施例を示す回路図、第４図は第
３図の動作を説明するためのタイミングチャート、第５
図は従来の一例を示す回路図、第６図は第５図の動作を
説明するためのタイミングチャートである。 1,2……OR回路、３〜５……NAND回路。FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram showing a second embodiment of the present invention. , FIG. 4 is a timing chart for explaining the operation of FIG. 3, and FIG.
FIG. 6 is a circuit diagram showing a conventional example, and FIG. 6 is a timing chart for explaining the operation of FIG. 1,2 ... OR circuit, 3-5 ... NAND circuit.
Claims (1)
第１のOR回路およびセット信号とクロック信号を入力と
する第２のOR回路のそれぞれの出力を第１及び第２のNA
ND回路へ入力し、第１のNAND回路の出力を第２のNAND回
路へ、また第２のNAND回路の出力を第１のNAND回路へと
入力し、第１又は第２のNAND回路の出力とクロック信号
を入力とする第３のNAND回路の出力を、第１又は第２の
NAND回路へ入力し、第３のNAND回路の論理閾値を、第１
及び第２のNAND回路よりも低く設定したことを特徴とす
るフリップフロップ回路。1. Outputs of a first OR circuit having a reset signal and a clock signal as inputs and a second OR circuit having a set signal and a clock signal as inputs, respectively.
Input to the ND circuit, the output of the first NAND circuit to the second NAND circuit, and the output of the second NAND circuit to the first NAND circuit, and the output of the first or second NAND circuit. And the output of the third NAND circuit, which receives the clock signal as input,
Input to the NAND circuit and set the logical threshold of the third NAND circuit to the first
And a flip-flop circuit characterized by being set lower than the second NAND circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63107028A JPH0681014B2 (en) | 1988-04-27 | 1988-04-27 | Flip-flop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63107028A JPH0681014B2 (en) | 1988-04-27 | 1988-04-27 | Flip-flop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01276814A JPH01276814A (en) | 1989-11-07 |
| JPH0681014B2 true JPH0681014B2 (en) | 1994-10-12 |
Family
ID=14448686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63107028A Expired - Fee Related JPH0681014B2 (en) | 1988-04-27 | 1988-04-27 | Flip-flop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0681014B2 (en) |
-
1988
- 1988-04-27 JP JP63107028A patent/JPH0681014B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01276814A (en) | 1989-11-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |