JPH0677280U - Ceramic multilayer board - Google Patents
Ceramic multilayer boardInfo
- Publication number
- JPH0677280U JPH0677280U JP1534493U JP1534493U JPH0677280U JP H0677280 U JPH0677280 U JP H0677280U JP 1534493 U JP1534493 U JP 1534493U JP 1534493 U JP1534493 U JP 1534493U JP H0677280 U JPH0677280 U JP H0677280U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- dielectric constant
- layer
- ceramic body
- high dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】
【目的】 製造時にコンデンサーのショートが発生しな
い構造のセラミック多層基板を提供する。
【構成】 セラミック体2の内部に、高誘電率体6を電
極4、5によりはさんで形成されたコンデンサーを内蔵
する構造のセラミック多層基板において、少なくとも前
記セラミック体2と前記高誘電率体6との界面12と前
記電極4、5とが接する部分に、絶縁層11−1、11
−2を設ける。
(57) [Abstract] [Purpose] To provide a ceramic multilayer substrate having a structure in which a short circuit of a capacitor does not occur during manufacturing. In a ceramic multi-layer substrate having a structure in which a capacitor formed by sandwiching a high dielectric constant material 6 between electrodes 4 and 5 is built in a ceramic body 2, at least the ceramic body 2 and the high dielectric constant material 6 are provided. Insulating layers 11-1 and 11 are provided at the portions where the interface 12 with the electrodes 4 and 5 are in contact with each other.
-2 is provided.
Description
【0001】[0001]
本考案は、セラミック体の内部に、高誘電率体を電極によりはさんで形成され たコンデンサーを内蔵する構造のセラミック多層基板に関するものである。 The present invention relates to a ceramic multilayer substrate having a structure in which a capacitor formed by sandwiching a high dielectric constant material between electrodes is built in a ceramic body.
【0002】[0002]
従来から、アルミナ等の材質からなるセラミック体の内部に、多層の配線層を 設けるとともに、上下の配線層を電極とし、これらの電極間に高誘電率体をはさ んでコンデンサーを形成した構造のセラミック多層基板は、種々のものが知られ ている。 Conventionally, a ceramic body made of a material such as alumina is provided with a multilayer wiring layer, and upper and lower wiring layers are used as electrodes, and a high dielectric constant material is sandwiched between these electrodes to form a capacitor. Various ceramic multilayer substrates are known.
【0003】 図3は従来のコンデンサー内蔵型のセラミック多層基板の一例におけるコンデ ンサーの部分の構成を示す図である。図3に示す例において、21は上層のセラ ミック体、22は中層のセラミック体、23は下層のセラミック体、24は上層 セラミック体内に設けられた上部電極、25は下層セラミック体内に設けられた 下部電極、26は中層セラミック体22内において上部電極24と下部電極25 との間にはさまれて設けられた高誘電率体である。FIG. 3 is a diagram showing a configuration of a capacitor portion in an example of a conventional ceramic multilayer substrate with a built-in capacitor. In the example shown in FIG. 3, 21 is an upper ceramic body, 22 is an intermediate ceramic body, 23 is a lower ceramic body, 24 is an upper electrode provided in the upper ceramic body, and 25 is provided in the lower ceramic body. The lower electrode, 26 is a high dielectric constant material provided between the upper electrode 24 and the lower electrode 25 in the middle layer ceramic body 22.
【0004】[0004]
上述した構成のコンデンサー内蔵型のセラミック多層基板を得るには、通常、 高誘電率テープをグリーンテープ内に埋め込んだ中層のグリーンテープを準備し 、表面に下部電極をスクリーン印刷した下層のグリーンテープ上に載せ、中層の グリーンテープ上にスクリーン印刷により上部電極を形成し、最後に上層のグリ ーンテープを載せ、さらに必要な層数の配線層およびグリーンシートを載せ、最 後にこの状態で焼成して製造している。 In order to obtain a ceramic multilayer substrate with a built-in capacitor having the above-mentioned structure, it is usually necessary to prepare a middle-layer green tape in which a high-dielectric-constant tape is embedded in the green tape, and the lower electrode is screen-printed on the surface of the lower-layer green tape On top, form the upper electrode by screen printing on the middle layer of green tape, finally place the upper layer of green tape, and then place the required number of layers of wiring layers and green sheets, and finally burn in this state to manufacture. is doing.
【0005】 しかしながら、上述したようにしてコンデンサー内蔵型のセラミック基板を得 ると、高誘電率テープはグリーンテープに埋め込んだ構造であるため、高誘電率 テープとグリーンテープとの界面に隙間が存在し、焼成時に電極を構成するAg 等の金属が拡散して、上部電極と下部電極との間がショートしてしまい、コンデ ンサーとして機能しなくなる問題があった。However, when the ceramic substrate with a built-in capacitor is obtained as described above, since the high dielectric constant tape has a structure embedded in the green tape, a gap exists at the interface between the high dielectric constant tape and the green tape. However, there is a problem that the metal such as Ag forming the electrode diffuses during firing, causing a short circuit between the upper electrode and the lower electrode, and thus not functioning as a capacitor.
【0006】 本考案の目的は上述した課題を解消して、製造時にコンデンサーのショートが 発生しない構造のセラミック多層基板を提供しようとするものである。An object of the present invention is to solve the above problems and to provide a ceramic multilayer substrate having a structure in which a short circuit of a capacitor does not occur during manufacturing.
【0007】[0007]
本考案のセラミック多層基板は、セラミック体の内部に、高誘電率体を電極に よりはさんで形成されたコンデンサーを内蔵する構造のセラミック多層基板にお いて、少なくとも前記セラミック体と前記高誘電率体との界面と前記電極とが接 する部分に、絶縁層を設けたことを特徴とするものである。 The ceramic multi-layered substrate of the present invention is a ceramic multi-layered substrate having a structure in which a capacitor formed by sandwiching a high-dielectric constant material between electrodes is built in the ceramic body. An insulating layer is provided at a portion where the interface with the body and the electrode are in contact with each other.
【0008】[0008]
上述した構成において、少なくともセラミック体と高誘電率体との界面と電極 との間に設けた絶縁層が、焼成時におけるセラミック体と高誘電率体との界面を 通しての電極材料の拡散を防止し、電極間のショートを防ぐことができる。 In the above-described structure, the insulating layer provided at least between the interface between the ceramic body and the high dielectric constant body and the electrode prevents diffusion of the electrode material through the interface between the ceramic body and the high dielectric constant body during firing. It is possible to prevent the short circuit between the electrodes.
【0009】[0009]
図1は本発明のセラミック多層基板の一例におけるコンデンサーの部分の構成 を示す図である。図1に示す例において、1は上層のセラミック体、2は中層の セラミック体、3は下層のセラミック体、4は上層セラミック体1内に設けられ た上部電極、5は下層セラミック体内に設けられた下部電極、6は中層セラミッ ク体2内において上部電極4と下部電極5との間にはさまれて設けられたチタン 酸バリウム等からなる高誘電率体であり、これらの構成は従来の例と同様である 。なお、本例においては、説明の都合上セラミック体を上層、中層、下層とわけ て記載したが、実際のセラミック多層基板においてはこれら各層は一体となり区 別できない。 FIG. 1 is a diagram showing a configuration of a capacitor portion in an example of the ceramic multilayer substrate of the present invention. In the example shown in FIG. 1, 1 is an upper layer ceramic body, 2 is an intermediate layer ceramic body, 3 is a lower layer ceramic body, 4 is an upper electrode provided in the upper layer ceramic body 1, and 5 is provided in a lower layer ceramic body. The lower electrode 6 is a high dielectric constant material made of barium titanate, etc., which is provided between the upper electrode 4 and the lower electrode 5 in the middle layer ceramic body 2. Similar to the example. In this example, the ceramic body is described as the upper layer, the middle layer, and the lower layer for convenience of description, but in an actual ceramic multi-layer substrate, these layers cannot be separated as one unit.
【0010】 本実施例のセラミック多層基板において重要なのは、上部電極4と高誘電率体 6との間および下部電極5と高誘電率体6との間に、ガラス等の材料からなる上 部絶縁層11−1と下部絶縁層11−2を設けて、少なくとも中層セラミック体 2と高誘電率体6との界面12と上部電極4および下部電極5との間を絶縁した 点である。そのため、セラミック多層基板の製造時の焼成においても、上部絶縁 層11−1および下部絶縁層11−2が、上部電極4および下部電極5のAg等 の金属の界面12方向の拡散を防止することができる。What is important in the ceramic multilayer substrate of this embodiment is that the upper insulation made of a material such as glass is provided between the upper electrode 4 and the high dielectric constant body 6 and between the lower electrode 5 and the high dielectric constant body 6. The point is that the layer 11-1 and the lower insulating layer 11-2 are provided to insulate at least the interface 12 between the middle-layer ceramic body 2 and the high dielectric constant body 6 and the upper electrode 4 and the lower electrode 5. Therefore, the upper insulating layer 11-1 and the lower insulating layer 11-2 should prevent the diffusion of the metal such as Ag of the upper electrode 4 and the lower electrode 5 toward the interface 12 even during firing of the ceramic multilayer substrate. You can
【0011】 なお、本実施例のように、上部絶縁層11−1と下部絶縁層11−2を設けて 高誘電率体6と上部電極4または下部電極5との間を絶縁しても、高誘電率体6 からなるコンデンサーに絶縁層11−1および11ー2から構成されるコンデン サーが直列に接続された構造となるだけであり、コンデンサーの全体としての容 量は若干減るもののコンデンサーとして機能することはいうまでもない。Even if the upper insulating layer 11-1 and the lower insulating layer 11-2 are provided to insulate the high dielectric constant body 6 from the upper electrode 4 or the lower electrode 5 as in this embodiment, Only the capacitor composed of the insulating layers 11-1 and 11-2 is connected in series to the capacitor composed of the high-dielectric constant material 6, and the capacity of the capacitor as a whole is slightly reduced. It goes without saying that it works.
【0012】 上述した構成のセラミック多層基板を得るには、高誘電率テープをグリーンテ ープ内に埋め込んだ中層のグリーンテープを準備し、表面に下部電極をスクリー ン印刷しさらに下層絶縁層をスクリーン印刷した下層のグリーンテープ上に載せ 、中層のグリーンテープ上にスクリーン印刷により上部絶縁層およびその上に上 部電極を形成し、最後に上層のグリーンテープを載せ、さらに必要な層数の配線 層およびグリーンシートを載せ、最後にこの状態で焼成して製造することができ る。なお、高誘電率テープをグリーンテープに埋め込むには、グリーンテープに パンチにより孔を明け、その孔に高誘電率テープをパンチで埋め込む方法等の従 来から公知の方法を使用することができる。In order to obtain the ceramic multilayer substrate having the above-described structure, a middle layer green tape in which a high dielectric constant tape is embedded in a green tape is prepared, a lower electrode is screen-printed on the surface, and a lower insulating layer is further formed. It is placed on the screen-printed lower layer green tape, the upper insulating layer and the upper electrode are formed on it by screen printing on the middle layer green tape, and finally the upper layer green tape is placed, and wiring for the required number of layers. It can be manufactured by placing the layers and the green sheet and finally firing in this state. To embed the high-dielectric-constant tape in the green tape, a conventionally known method such as a method of punching holes in the green tape and embedding the high-dielectric-constant tape in the holes with a punch can be used.
【0013】 図2は本考案のセラミック多層基板の他の例におけるコンデンサーの部分を示 す図である。図2に示す例では、図1に示す例のように上部絶縁層11−1およ び下部絶縁層11−2を上部電極4および下部電極5と高誘電率体6との間の全 面に配置するのとは異なり、中層セラミック体2と高誘電率体6との界面12に 対応する位置にのみ上部絶縁層11−1、11−2を設けている。図2に示す構 造のセラミック多層基板においても、図1に示すものと同様に、セラミック多層 基板を製造するための焼成時における、上部電極4および下部電極5のAg等の 金属の界面12を通じての拡散を防止することができる。FIG. 2 is a diagram showing a capacitor portion in another example of the ceramic multilayer substrate of the present invention. In the example shown in FIG. 2, as in the example shown in FIG. 1, the upper insulating layer 11-1 and the lower insulating layer 11-2 are formed on the entire surface between the upper electrode 4 and the lower electrode 5 and the high dielectric constant material 6. The upper insulating layers 11-1 and 11-2 are provided only at the positions corresponding to the interface 12 between the middle-layer ceramic body 2 and the high dielectric constant body 6, unlike the case where the upper insulating layers 11-1 and 11-2 are arranged. In the ceramic multilayer substrate having the structure shown in FIG. 2, as in the case shown in FIG. 1, the upper electrode 4 and the lower electrode 5 are intercalated through the metal interface 12 such as Ag during firing for manufacturing the ceramic multilayer substrate. Can be prevented from spreading.
【0014】[0014]
以上の説明から明らかなように、本考案によれば、少なくともセラミック体と 高誘電率体との界面と電極との間に絶縁層を設けているため、セラミック多層基 板を製造する際の焼成時において、セラミック体と高誘電率体との界面を通して の電極材料の拡散を防止しでき、電極間のショートを防ぐことができる。 As is clear from the above description, according to the present invention, since the insulating layer is provided at least between the interface between the ceramic body and the high dielectric constant body and the electrode, it is possible to perform firing during the production of the ceramic multilayer substrate. At times, it is possible to prevent the diffusion of the electrode material through the interface between the ceramic body and the high dielectric constant material, and to prevent a short circuit between the electrodes.
【図1】本考案のセラミック多層基板の一例におけるコ
ンデンサーの部分の構成を示す図である。FIG. 1 is a diagram showing a configuration of a capacitor portion in an example of a ceramic multilayer substrate of the present invention.
【図2】本考案のセラミック多層基板の他の例における
コンデンサーの部分の構成を示す図である。FIG. 2 is a diagram showing a configuration of a capacitor portion in another example of the ceramic multilayer substrate of the present invention.
【図3】従来のセラミック多層基板の一例におけるコン
デンサーの部分の構成を示す図である。FIG. 3 is a diagram showing a configuration of a capacitor portion in an example of a conventional ceramic multilayer substrate.
1 上層セラミック体 2 中層セラミック体 3 下層セラミック体 4 上部電極 5 下部電極 6 高誘電率体 11−1 上部絶縁層 11−2 下部絶縁層 12 界面 1 Upper Layer Ceramic Body 2 Middle Layer Ceramic Body 3 Lower Layer Ceramic Body 4 Upper Electrode 5 Lower Electrode 6 High Dielectric Constant 11-1 Upper Insulating Layer 11-2 Lower Insulating Layer 12 Interface
Claims (1)
極によりはさんで形成されたコンデンサーを内蔵する構
造のセラミック多層基板において、少なくとも前記セラ
ミック体と前記高誘電率体との界面と前記電極とが接す
る部分に、絶縁層を設けたことを特徴とするセラミック
多層基板。1. A ceramic multilayer substrate having a structure in which a capacitor formed by sandwiching a high dielectric constant material between electrodes is built in the ceramic body, and at least an interface between the ceramic body and the high dielectric constant material and the interface. A ceramic multi-layer substrate, characterized in that an insulating layer is provided at a portion in contact with the electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1534493U JPH0751813Y2 (en) | 1993-03-30 | 1993-03-30 | Ceramic multilayer board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1534493U JPH0751813Y2 (en) | 1993-03-30 | 1993-03-30 | Ceramic multilayer board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0677280U true JPH0677280U (en) | 1994-10-28 |
JPH0751813Y2 JPH0751813Y2 (en) | 1995-11-22 |
Family
ID=11886182
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1534493U Expired - Fee Related JPH0751813Y2 (en) | 1993-03-30 | 1993-03-30 | Ceramic multilayer board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0751813Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005191102A (en) * | 2003-12-24 | 2005-07-14 | Kyocera Corp | Wiring board and its manufacturing method |
-
1993
- 1993-03-30 JP JP1534493U patent/JPH0751813Y2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005191102A (en) * | 2003-12-24 | 2005-07-14 | Kyocera Corp | Wiring board and its manufacturing method |
JP4610185B2 (en) * | 2003-12-24 | 2011-01-12 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH0751813Y2 (en) | 1995-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6252761B1 (en) | Embedded multi-layer ceramic capacitor in a low-temperature con-fired ceramic (LTCC) substrate | |
US6778058B1 (en) | Embedded 3D coil inductors in a low temperature, co-fired ceramic substrate | |
JPH09129476A (en) | Ceramic electronic part | |
US20020026978A1 (en) | Multilayer ceramic substrate and manufacturing method therefor | |
JPH0632378B2 (en) | Multi-layer ceramic board with built-in electronic components | |
JP4074353B2 (en) | Manufacturing method of ceramic multilayer support | |
JPH0677280U (en) | Ceramic multilayer board | |
US6627021B2 (en) | Method of manufacturing laminated ceramic electronic component and method of manufacturing laminated inductor | |
JP2684877B2 (en) | Multilayer board | |
JPH06232005A (en) | Lc composite component | |
JP2001313230A (en) | Capacitor array | |
JPH11330705A (en) | Substrate containing capacitor and manufacture thereof | |
US20100142115A1 (en) | Buried capacitor, method of manufacturing the same, and method of changing capacitance thereof | |
KR20220086169A (en) | Multilayered capacitor and board for mounting the same | |
KR100566052B1 (en) | Built-in capacitor using dissimilar dielectrics and method of manufacturing the same | |
JP2000012375A (en) | Laminated ceramic electronic component | |
JPH05347227A (en) | Laminated thin film capacitor | |
JP2001257473A (en) | Multilayer ceramic board and manufacturing method thereof | |
JP2766085B2 (en) | Manufacturing method of laminate | |
JP2002270465A (en) | Terminal electrode of laminate electronic component | |
JPH0669663A (en) | Multilayered substrate incorporating capacitor | |
JPH08273970A (en) | Laminated ceramic electronic component | |
JP2874685B2 (en) | Method for manufacturing multilayer substrate | |
JPH01262695A (en) | Ceramic multilayer board having built-in capacitor | |
JP2001230552A (en) | Circuit board and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |