JPH0677098B2 - Camera focus detection device using image sensor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a focus detection device for a camera using a self-scanning image sensor having a charge storage section that constitutes an image sensor array and a transfer section for transferring the stored charge.

2. Description of the Related Art Conventionally, as a focus detection device for a camera as described above, there is known a device that uses a CCD (Charge Coupled Device) including a photodiode array as a charge storage unit and a transfer unit and a CCD shift register as a self-scanning image sensor. Has been. When a positive pulse called an integration clear pulse is input to the CCD, each of the photodiodes that make up the photodiode array is charged to approximately the power supply voltage level and then discharged by the disappearance of the integration clear pulse (hereinafter,
This is considered to be the accumulation of negative charges and is called charge accumulation), but the charge accumulation speed changes according to the subject brightness, that is, the intensity of light incident on each photodiode,
If the subject brightness is low, it is necessary to accumulate the charge for a long time. Conversely, if the subject brightness is extremely high, the accumulated charge of each photodiode is saturated in a short time, and based on that, a reliable image signal is obtained. Can't get
For this reason, it is necessary to provide a light receiving means for monitoring and to control the transfer timing of the accumulated charge from the photodiode array to the CCD shift register according to the intensity of the light incident on it. Therefore, the output is restored to the initial level equal to the level of the power supply voltage by the generation of the integration clear pulse,
Simultaneously with the disappearance of the integration clear pulse, a monitor circuit configured to reduce the output at a speed according to the output of the monitor light receiving means, and a determination means for determining that the output of the monitor circuit has decreased by a predetermined level, When the determination is made, shift pulse generating means for generating a shift pulse for transferring the accumulated charge from the photodiode array to the CCD shift register is provided. How to secure the reference signal that should be compared with the output of 1 is a problem. In other words, the output of the monitor circuit itself begins to drop according to the subject brightness immediately after the integration clear pulse disappears, and the output of the monitor circuit before the generation of the integration clear pulse also differs depending on the conditions such as the subject brightness during the previous operation. It is difficult to obtain the above-mentioned reference signal from the output itself of the monitor circuit. On the other hand, it is conceivable to provide a constant voltage source as the reference signal generating means, but if there is a fluctuation in the power supply voltage, a fluctuation will occur on the side of the initial output level of the monitor circuit immediately after the integration clear pulse disappears. Even if the output of the shift circuit is compared with the output of, the output decrease of the monitor circuit at the predetermined level cannot be correctly determined, and the generation timing of the shift pulse changes even under the same luminance condition. Considering this, it may be possible to use the power supply voltage itself as the reference signal, but the way the output of the monitor circuit decreases depends on its own circuit characteristics, and noise occurs in the power supply voltage. Since this is easy, it is not possible to correctly determine the decrease in the predetermined level of the output of the monitor circuit even with this method.

An object of the present invention is to detect a focus of a camera which can easily secure a reference signal to be compared with the output of a monitor circuit and can always generate a shift pulse at a constant timing under the same brightness condition. The purpose is to provide a device.

The present invention provides a reference signal generating circuit having a device and a circuit configuration having the same characteristics as those of a monitor circuit as a reference signal generating means, and the reference signal as a reference signal to be compared with the output of the monitor circuit is used as a reference signal. From the signal generation circuit,
The feature is that a steady output is generated after the integration clear pulse disappears.

Embodiment Next, an embodiment of the present invention will be described with reference to FIGS. 1 to 11.

First, in FIG. 1 showing the entire circuit of this embodiment,
As will be described later, (1) is a photoelectric conversion block including a self-scanning image sensor such as a CCD, an image signal output circuit, a brightness monitor light receiving element, a brightness monitor circuit, and a reference signal generation circuit, (10) is a transfer clock pulse generation block, (20) is a circuit block which forms a digital signal which is the basis of the focus adjustment state judgment of the photographing lens based on the signal from the photoelectric conversion block (1), and (30) is a circuit The microcomputer performs the control operation of each circuit block while determining the focus adjustment state of the photographing lens based on the digital signal from the block (20).

Further, (40) controls the amplification factor of the amplifier in the circuit block (20) based on the output of the brightness monitor circuit in the photoelectric conversion block (1), while the self-scanning type in the photoelectric conversion block (1). A brightness determination circuit that controls the charge storage time (photocurrent integration time) of the image sensor, (AN1) and (AN2) are AND circuits that form gate means together with an OR circuit (OR1), and (DF1) is a flip-flop (FF0 described later). ) (FF1)
To (FF6) D flip-flops that generate reset pulses, (DF2) D flip-flops (CL1) that generate shift pulses that transfer the charges accumulated in the charge storage unit to the transfer unit in the image sensor,
Is a clock circuit that generates the reference clock pulse, (FF
0) is an RS flip-flop.

FIG. 2 shows the photoelectric conversion block (1) described above, and includes photodiode rows (P1) (P2) (P3) ... (Pn-2).
Image sensor array (Pn-1) (Pn)
A), integration clear gate (ICG), shift gate (SG),
The above-mentioned self-scanning image sensor is configured by the CCD shift register (SR). Where is the transfer part
The number of cells in the CCD shift register (SR) is 3 more than the number of photodiodes (number of pixels) in the image sensor array (PA), which is the charge storage unit, and the cells (R1) (R2) (R3) are fed in blanks as described below. For image sensor array (PA)
Photodiodes (P1) (P2) (P3)… (Pn-2)
The accumulated charges of (Pn-1) (Pn) are stored in cells (R4) (R5) (R6) ...
It is transferred to (Rn + 1) (Rn + 2) (Rn + 3). Each photodiode has a power supply (+ V) as shown in FIG.
On the other hand, it consists of a pair of diodes (D1) (D2) and FET (Q10) connected in parallel with each other through a switch (S) corresponding to an integration clear gate (ICG), and one diode (D1) is a light source. It is installed to receive. FET (Q10)
Is designed to keep the voltage across the diode (D1) substantially constant and to ignore the capacitance of the diode (D1).
Its gate is grounded. Now, when the switch (S) is closed, charges are accumulated between the anode and cathode of the diode (D2), and the anode voltage becomes equal to the power supply voltage. Then, when the switch (S) is opened next time, the diode (D2) is turned on by the FET (Q
10) and its anode voltage drops over time. That is, it may be considered that the negative charge is accumulated in the cathode of the diode (D2) at a speed according to the intensity of the light incident on the diode (D1), and therefore each photodiode responds to the intensity of the incident light. At speed,
Description will be made assuming that charges are accumulated.

The switch (S1) is actually the integration clear gate (IC
It is composed of a semiconductor analog switch that becomes conductive by the integration clear pulse input to G) and becomes non-conductive when the pulse disappears. The shift gate (SG) receives the accumulated charge of the photodiodes (P1) (P2) (P3) ... (Pn-2) (Pn-1) (Pn) and receives the shift pulse described later, and the cell of the CCD shift register (SR). (R4) (R5) (R6) ... (Rn + 1) (Rn +
2) Transfer to (Rn + 3) in parallel. The charge accumulation of the photodiodes (P1) (P2) (P3) ... (Pn-2) (Pn-1) (Pn) is terminated by the input of the shift pulse to the shift gate (SG). The CCD shift register (SR) receives a transfer clock pulse (φ1) (φ2), which will be described later, every time it is input.
At the falling edge of the transfer clock pulse (φ1), the accumulated charge for one cell is sequentially output to the image signal output circuit described later. In addition,
A predetermined number (10) of photodiodes (P1) (P2) ... (P10) counted from one end of the image sensor array (PA) are covered with an aluminum film and are used for dark output correction as described later. . In Fig. 2, (T8) and (T9) are the power source (+) for the above-mentioned image sensor, circuit (MC) (RS) (VS).
This is a power supply terminal for supplying V).

By the way, the position of the image sensor array (PA) in the camera depends on the focus detection method. FIG. 4 shows an example of a focus detection optical system to which the present invention can be applied.
L) is a condenser lens, (L1) and (L2) are a pair of re-imaging lenses symmetrically arranged with respect to the main optical axis (l) of the taking lens (TL), (M) is a mask, and (F) is a camera. This is the planned imaging plane of the taking lens (TL), which is equivalent to the film plane.
According to this optical system, when the photographic lens (TL) forms a subject image on or before and after the planned image formation surface (F),
The re-imaging lenses (L1) (L2) re-form the subject image as first and second images on the image sensor array (PA), and the first and second images on the image sensor array (PA). The image interval is the focus adjustment state of the taking lens (TL), that is, the projected image plane (F) of the subject image formed thereby.
It changes depending on the shift state. Therefore, if the distance between the first and second images is detected based on the output of each pixel of the image sensor array (DA), the defocus amount and the defocus direction indicating the focus adjustment state of the taking lens (TL) can be determined. The output processing method required for this will be described later. In FIG. 4, the image sensor array (PA) is located at or near a position conjugate with the planned imaging plane (F) with respect to the condenser lens (CL) and the pair of re-imaging lenses (L1) and (L2). Will be placed.

In FIG. 2 again, (MP) is a photodiode which is a light receiving element for brightness monitor, (MC) is a brightness monitor circuit, (RS) is a reference signal generating circuit, and (VS) is an image signal output circuit. Brightness monitor circuit (MC) is FET (Q1) (Q
2) Consists of (Q3) and condenser (C1).

The gate of the FET (Q1) is connected to the integral clear gate (3) of the image sensor, and the FET (Q1) is turned on by the integral clear pulse that has passed through the integral clear gate (ICG), which causes the capacitor (C1) to be the power supply voltage. (+
V) level is charged. The connection point (J1) between the FET (Q1) and the capacitor (C1) is connected to the anode of the photodiode (MP) via the EFT (Q12), while the FET (Q2) is connected.
Is connected to the gate. The gate of the FET (Q12) is grounded, and the voltage across the photodiode (MP) is kept substantially constant so that the influence of the capacitance can be ignored. The FETs (Q2) and (Q3) are connected in series to the power supply, and form a buffer with low output impedance and high input impedance.
3) is used in the source follower, so FET (Q
2) The voltage (Vm) corresponding to the potential of the connection point (J1) is output from the output terminal (T1) drawn from the connection point of (Q3). When the integration clear pulse disappears, the FET (Q1) becomes non-conductive, the capacitor (C1) is discharged by the photocurrent of the photodiode (MP), and the output voltage of the terminal (T1) drops accordingly. Fig. 5 shows this terminal (T1)
It shows the change over time of the output voltage of
(L2) (l3) (l4) (l5) show that the rate of voltage drop changes with brightness. The rising edge indicated by (RN) represents the noise induced by the integral clear pulse.

The reference voltage generator (RS) consists of FETs (Q4) (Q5) (Q6) and a capacitor (C2).
It has the same characteristics as (Q1), (Q2), (Q3), and capacitor (C1), and its circuit connection is the brightness monitor circuit (M
FET (Q1) (Q2) (Q3) and capacitor (C) in C)
It is the same as the circuit connection in 1). However, the gate of the FET (Q5) is only connected to the connection point (J2) of the FET (Q4) and the capacitor (C2), and therefore the FET (Q2) (Q2)
FETs (Q5) (Q6) that form a buffer with low output impedance and high input impedance, similar to 3)
The voltage signal output from the output terminal (T2) drawn from the connection point is kept constant as shown in FIG. 5 even after the integration clear pulse disappears. That is, the potentials at the connection points (J1) (J2) immediately after the disappearance of the integration clear pulse (T0) are the FETs (Q1) (Q2) (Q3) and the capacitor (C1) as described above.
And FET (Q4) (Q5) (Q6) and capacitor (C2) have the same characteristics, so they are equal to each other, so terminal (T2)
The voltage signal output from the terminal can be used as a reference voltage (Vref) for obtaining the amount of drop of the voltage signal output from the terminal (T1).

The image signal output circuit (VS) consists of FETs (Q7) (Q8) (Q9) and capacitors (C3).
Use the same characteristics as FET (Q1) (Q2) (Q3) and capacitor (C1). However, in circuit connection, FE
The transfer clock pulse (φ1) is applied to the gate of T (Q7), and the connection point (J3) between the FET (Q7) and the capacitor (C3) is the gate of the FET (Q8) and the image. It is connected to the transfer terminal of the CCD shift register (5) of the sensor. Therefore, one transfer pulse (φ1)
FET (Q7) is turned on each time
3) is charged to the level of the power supply voltage (+ V) and the image signal output circuit (VS) is reset, but it is transferred by each transfer pulse (φ1) CCD shift register (5)
The output terminal (T3) drawn from the connection point of the FETs (Q8) and (Q9) that constitute a buffer with low output impedance and high input impedance eventually discharges the image. The output corresponding to the accumulated charge of each photodiode, which is a pixel of the sensor, is sequentially output as a voltage signal (V _0s ), and they _collectively form an image signal.

(C1) in the above circuits (MC) (RS) (VS)
Although (C2) and (C3) are described as capacitors for convenience of explanation, they can be replaced with PN junctions of diodes,
When integrating these circuits, each is manufactured as a diode. The photodiode (MP), which is a light receiving element for monitoring, is arranged near the image sensor array (PA) so as to receive a part of the light that has passed through the taking lens.

Next, referring again to FIG. 1, the transfer clock pulse (φ
1) An example of the circuit configuration of the transfer clock pulse generation block (10) for generating (φ2) will be described. (FF1) (FF2) ...
(FF6) is a flip-flop circuit that forms a frequency divider circuit, and the clock pulse (cycle 2 μm from the clock circuit (CL1) is input to the T input of the first-stage flip-flop (FF1).
Seconds) is entered. Flip-flop (FF3) (FF4)
The Q outputs of (FF5) and (FF6) are input to the OR circuit (OR2), and the output of the OR circuit (OR2) is input to one input of the AND circuit (AN4). AND circuit (AN
The other input of 4) is connected to the terminal (T22) of the microcomputer (30) via the inverter (IN1), and when the terminal (T22) outputs the signal of "0", this AND circuit ( The "1" signal of the OR circuit (OR2) is output from AN4). On the other hand, the AND circuit (AN5) has one input connected to the clock circuit (CL2) and the other input connected to the above-mentioned terminal (T22). Therefore, the above-mentioned terminal (T22) is a signal of "1". Output the clock circuit (C
Output the clock pulse from L2). Here, the cycle of the clock pulse output from the clock circuit (CL2) is set to be several tens of times shorter than the cycle of the output (Q6) of the flip-flop FF6 that divides the clock pulse output from the clock circuit (CL1). ing. The OR circuit (OR3) shifts the CCD in the photoelectric conversion block (1) by using the signal of "1" as the transfer clock pulse (φ2) when one of the output signals of the AND circuit (AN4) (AN5) is "1". Output to register (SR). The OR circuit (OR3) has an inverter (IN2).
Is connected, and this inverter (IN2) is (φ2)
CCD shift register (SR) in photoelectric conversion block (1) with transfer clock pulse (φ1) in phase opposite to
And to the image signal output circuit (VS) (see FIG. 2). In addition, the terminal (T2
The signal "1" from 2) is a signal for causing the image sensor to perform the initialization operation.

FIG. 6 shows an example of the brightness determination circuit (40) and the circuit block (20). In this figure, (T10) (T11) (T12) are terminals connected to terminals (T1) (T2) (T3) of FIG. 2, respectively, and terminals (T13) (T15) (T16) will be described later. From the microcomputer (30) to the data bus (DB
Latch pulse, sample designation pulse, and sample designation reset pulse are input via 1). In addition, the terminal (T1
4) is connected to one input of the AND circuit (AN2) in FIG. First, the brightness determination circuit (40) will be described.
This circuit is a comparator (AC1) (AC2) (AC3) (AC4) for discriminating stepwise how much the output voltage (Vm) of the brightness monitor circuit (MC) drops after disappearance of the integral clear pulse.
Is equipped with. The inverting inputs of these comparators are connected to the terminal (T10) via the buffer (B1). On the other hand, the non-inverting input of these comparators (AC1) (AC2) (AC3) (AC4) is connected to the connection point (J) of the resistor (R1) and the constant current source (I1).
4), connection point (J5) between resistance (R2) and constant current source (I2), connection point (J6) between resistance (R3) and constant current source (I3), resistance (R4)
And the constant current source (I4) are connected to the connection point (J7) respectively, and the resistors (R1) (R2) (R3) (R4) are connected to the terminal (T11) via the buffer (B2). . With such circuit connection, the above-mentioned reference voltage generation circuit (RS) applied to the terminal (T11) at the connection points (J4) (J5) (J6) (J7)
Voltage (Vref) from resistance (R1) (R2) (R3) (R4) respectively
The voltage generated by subtracting the voltage drop at
1) Resistance value of (R2) (R3) (R4) and constant current source (I1)
By selecting the current values of (I2), (I3) and (I4), the comparator can be selected according to the degree of voltage drop of the output voltage (Vm) of the brightness monitor circuit (MC) input to the terminal (T10). (AC
1) The output of (AC2) (AC3) (AC4) is sequentially inverted from "0" to "1". (DF3) (DF4) (DF5) are D flip-flops whose D inputs are connected to the outputs of the comparators (AC1) (AC2) (AC3), and these CP inputs have the microcomputer (Fig. 1). Latch pulse from 30) is at terminal (T1
3) for a predetermined time (1
If a shift pulse occurs after (00 ms) or before the predetermined time has elapsed, the shift pulse is input in synchronization with it. Then, when the latch pulse is input,
The D flip-flops (DF3) (DF4) (DF5) output the outputs of the immediately preceding comparators (AC1) (AC2) (AC3) to the Q output, and output inverted outputs from the outputs. (AN6) has one input connected to the Q output of the D flip-flop (DF3) and the other input connected to the output of the D flip-flop (DF4). (AN7) has one input connected to the D flip-flop. (DF4) output, the other input is D
An AND circuit connected to the Q output of the flip-flop (DF5), and the output (b) of the AND circuit (AN6) (AN7)
(C), output of D flip-flop (DF3) (a),
The Q output (d) of (DF5) and the output (e) of the comparator (AC4) become the output of the brightness determination circuit (40). That is,
These outputs become signals indicating the brightness level detected by the monitor light receiving element (PM).

This will be described in more detail with reference to FIG.
In the figure, (1), (l2), (l3), and (l4) are when the voltage drop that occurs from the time when the integration clear pulse disappears (t0) to the time when the above-mentioned predetermined time (100 msec) elapses (t3) is less than 0.35 V, respectively. ,
If 0.35V to less than 0.7V, 0.7V to less than 1.4V,
It shows the output voltage change of the brightness monitor circuit (MC) in the case of 1.4V to less than 2.8V. Moreover, (l5) is the time before the above-mentioned predetermined time (100msec) has elapsed from the time when the integration clear pulse disappeared (t0). It shows the output voltage change of the same monitor circuit (MC) when the voltage drop of 2.8V occurs at the time point (t2). (1)
The voltage drop of (l2) (l3) (l4) (l5) depends on the magnitude of the photocurrent of the monitor light receiving element (DM) as described above, and the brightness monitor circuit (MC) When the output voltage change of (1) is (1) (l2) (l3) (l4), it is low luminance, and when it is (l5), it is high luminance. Now, the reference voltage generation circuit (RS) in which the voltages at terminals (J4) (J5) (J6) (J7) are input to terminals (T11), respectively.
Output voltage (Vref) of 0.35V, 0.7V, 1.4V,
The above resistance (R1) (R2) (R3) to be 2.8V lower
Resistance value of (R4) and constant current source (I1) (I2) (I3) (I4)
When the current value of is set, the Q output and output of the D flip-flops (DF3) (DF4) (DF5) corresponding to (1) (l2) (l3) (l4) (l5) after the latch pulse is generated,
And output of brightness monitor circuit (MC) (a) (b) (c)
(D) and (e) are as shown in Table 1 below.

In the case of (l5), the output (d) of the comparator (AC4) is a predetermined time (100 msec) from the time when the integration clear pulse disappears (t0).
At the time (t2) before elapses, it changes from "0" to "1".

The remaining circuit of FIG. 6 constitutes the circuit block (20) of FIG. (22) is the terminal (T12) through the buffer (B3)
Output voltage (V) of the image signal output circuit (VS)
_0s ) and the output voltage (V _ref ) of the reference signal generation circuit (RS) input from the terminal (T11) via the buffer (B2). .
(24) is a photodiode (P2) (Q9) at both ends of a predetermined number (10) of photodiodes (P2) to (P9) covered with an aluminum film in the image sensor array (PA).
Is a peak value detection circuit that detects the peak value (V2) (pixel signal of the lowest level) of the image signal corresponding to the accumulated charge except for, and outputs it by latching it.
For the pixel signal corresponding to the accumulated charge of the photodiode in the image sensor array (PA) receiving the first and second images, which is not covered with the aluminum film,
A signal V2 for so-called dark output correction is formed. That is, the microcomputer (30) stores the accumulated charge of the cell (R5) when the accumulated charge is sequentially transferred from the CCD shift register (SR) to the image signal output circuit (VS) by the transfer clock pulse (φ1) (φ2). Simultaneously with the start of data transfer, the sample specified pulse is sent via the data bus (DB1) to the pin (T15)
To the data bus (DB) at the same time when the transfer of the accumulated charge of the cell (R12) is completed.
Output to terminal (T16) via 1). Therefore, the peak value detection circuit (24) takes in the corresponding image signal of the accumulated charges of the cells (R5) to (R12), in other words, the accumulated charges of the photodiodes (P2) to (P9), and calculates the peak of them. The value will be detected.

(26) is the output signal (V1) (V2) of the circuits (22) and (24)
Is an amplifier which differentially amplifies, and whose amplification factor is configured to be controlled by the outputs (a), (b), (c), and (d) of the above-described luminance determination circuit (40). In this amplifier, (OP) is an operational amplifier, and its input terminals (f) and (g) are connected to the circuit (2) via input resistors (R5) and (R6).
2) and (24), respectively. (R7) to (R1
4) is a resistor provided for setting the amplification factor of the operational amplifier (OP), and is (R5) (R6) (R7) (R8) (R11) (R1
When the resistance value of 2) is r, (R9) (R13) has a resistance value of 2r, and (R10) (R14) has a resistance value of 4r. (AS
1) to (AS8) are analog switches, of which (AS1) to (AS4) selectively select resistors (R7) to (R10) according to outputs (a), (b), (c) and (d). While enabling and setting the feedback resistance value of the operational width device (OP), (AS
5) to (AS8) selectively enable the resistors (R11) to (R14) according to the outputs (a), (b), (c), and (d) to set the bias resistance value of the amplifier (OP). . That is, the states of the analog switches and the resistances to be activated when the voltage drops (1), (l2), (l3), (l4), and (l5) described above are as shown in Table 2 below.

In the above table, A is the amplification factor of the operational amplifier (OP), and the output voltage of this amplifier (OP) is represented by V _out = E + (V2-V1) × A, which is the A / D converter (ADC). Entered in. However, E is the voltage of the constant voltage source (E), and A / D converter (AD
Set appropriately according to the input level range of C). Then, each output of the A / D converter (ADC) corresponding to each pixel signal is taken into the terminal (T22) of the microcomputer shown in FIG. 1 through the data bus (DB1), and digitally output based on a predetermined program. The focus state of the taking lens is detected by the calculation. Thus, the amplifier (2
6) changes the amplification factor according to the output of the brightness judgment circuit (50) and outputs a signal suitable for signal processing in the A / D converter (ADC), so the focus of the shooting lens in a wide brightness range. The condition can be adjusted.

Referring again to FIG. 1, the terminal (T17) of the microcomputer (30) is the output terminal of the integral clear paris. Also, the terminal (T19) of the microcomputer (30)
Outputs a signal of "1" when the shift pulse generation is enabled, and the image sensor array (P
During transfer of the accumulated charge from A) to the CCD shift register (SR), the signal "0" that inhibits the generation of shift pulse is output. Furthermore, the terminal (T18) of the microcomputer (30)
From, when the above-mentioned predetermined time elapses from the extinction time (t0) of the integration clear pulse, or when a shift pulse occurs before the predetermined time elapses, the "1" signal is output in response to the generation of the shift pulse. Is output. This signal becomes a latch pulse for the luminance determination circuit (40). Terminal (T1
The integration clear pulse output from 7) is input to the integration clear gate (ICG) of the image sensor in the photoelectric conversion block (1) through the terminal (T6), while the flip-flop (FF0) is set and its Q Set the output to "1" to open the AND circuit (AN1). When the flip-flop (FF0) is set and the signal (1) that permits the generation of the shift pulse is output from the terminal (T19),
And circuit (AN2) is also opened. From the output terminal (T14) of the brightness determination circuit (40), only when the subject brightness is high as shown by (l5) in FIG. 5, a predetermined time (100 m The signal (e) of "1" is output at the time point (t2) before the elapse of seconds). On the other hand, when the subject brightness is low, as indicated by (1) (l2) (l3) (l4) in FIG. 5, the output from the terminal (T18) of the microcomputer (30) is (t3 At the point of time)), it becomes "1", and the output (e) of the output terminal (T15) of the brightness determination circuit (40) is kept at "0". Therefore, when the subject brightness is high, the output of the AND circuit (AN2) becomes "1" at the time of (t2), and when the subject brightness is low, the output of the AND circuit (AN1) becomes "1". ", And one of the outputs of" 1 "is input to the D input of the D flip-flop (DF1) via the OR circuit (OR1). The clock circuit (CL
Since the reference clock pulse (cycle 2 μs) from 1) is input, as shown in FIG. 6, D is input at the falling edge of the reference clock pulse immediately after the “1” signal is input to the D input. The Q output of the flip-flop (DF1) becomes "1",
The flip-flop (FF0) is reset, the opened AND circuit (AN1) or (AN2) is closed, and the flip-flops (FF1) to (FF6) in the transfer clock pulse generation block (10) are reset. Q outputs (Q1) to (Q6) are all "0". When the AND circuit (AN1) or (AN2) is closed in this way, the Q output of the D flip-flop (DF1) returns to "0" at the next falling edge of the reference clock pulse, and eventually the Q output This means that a positive pulse having a time width of 2 μsec has been output. This positive pulse is the reset pulse. On the other hand, in the D flip-flop (DF2), the Q output becomes "1" at the falling edge of the reference clock pulse from the clock circuit (CL1) immediately after the Q output of the D flip-flop (DF1) becomes "1", Immediately after the Q output of the D flip-flop (DF1) returns to "0", the Q output returns to "0" at the fall of the reference pulse of the same clock circuit. Therefore, a positive pulse having a time width of 2 μsec which rises in synchronization with the falling edge of the reset pulse is generated at the Q output of the D flip-flop (DF2), which is a shift pulse. This shift pulse is input to the terminal (T21) of the microcomputer (30) and also to the shift gate (SG) of the image sensor in the photoelectric conversion block (1) via the terminal (T7).

The above is a description of the entire circuit configuration of FIG. 1 and the circuit blocks constituting it. Before explaining the overall operation, refer to FIG. 7 and FIG. Will be explained.

FIG. 7 shows the outputs of the flip-flops (FF1) to (FF6) immediately after being reset by the reset pulse generated at the Q output of the D flip-flop (DF1) and the transfer pulse (φ
1) and the shift pulse which is the Q output of the D flip-flop (DF2). As described above, flip-flops (FF1) to (FF6) are generated at the rising edge of the reset pulse.
Are reset and their Q outputs (Q1) to (Q6) are all "0". As a result, the output of the OR circuit (OR2) becomes "0", the transfer clock pulse (φ2) falls to "0", and conversely the transfer clock pulse (φ1) becomes "1".
Rise to. Then, after 2 μsec has elapsed, the reset pulse falls, the shift pulse rises to “1” at the same time, and the shift pulse falls to “0” 2 μsec later. Next, the output of the OR circuit (OR2) becomes "1" when the Q output (Q3) of the flip-flop (FF3) becomes "1", which means that the reset pulse rises to "0". It is 8 μs after it goes down, and eventually the transfer clock pulse (φ1)
Is held in the state of “1” for 10 μs. The shift pulse is generated and disappears while the transfer clock pulse (φ1) is in the "1" state. In this way, the transfer clock pulse generation block (10) is reset immediately after the time (t2) or (t3), and the shift pulse is generated while the newly output transfer clock pulse (φ1) continues. The reason is that the end point of the charge accumulation (integration) of the photodiode array (P1) (P2) (P3) ... (Pn-2) (Pn-1) (Pn) in the image sensor array (PA) is unnecessary. This is to avoid being late. If a shift pulse is generated in synchronism with the first transfer clock pulse (φ1) generated after (t2) or (t3), then (t2) or (t3)
From the point of time, the time is approximately one cycle of the transfer clock pulse at the maximum. The photodiodes (P1) (P2) (P3) ...
-1) The charge accumulation of (Pn) may be unnecessarily performed, and when the subject is extremely bright, the charge accumulation may be saturated and a correct image signal may not be obtained. or,
Since the point after the time point (t2) or (t3) at which the shift pulse is generated is not always constant, there is a possibility that the image signal level may not be constant. In contrast,
In FIG. 7, since there is always a shift pulse within two cycles (4 μsec) of the reference clock pulse from the time point (t2) or (t3), there is no such fear.

As shown in FIG. 7, the outputs (Q3) (Q4) (Q5) (Q6) of the next transfer clock pulse (φ1) are all "0".
After 120 μs, it becomes “1”, and the time to keep this state is 8 μs. All transfer clock pulses after this transfer clock pulse are in the state of "1" for 8 μs and then 12
It is in the state of "0" for 0 microseconds. Therefore, the cycle of the transfer clock pulse (φ1) is 128 μs, and its duty cycle is not 1/2, and the duration ratio between the state of “1” and the state of “0” is 1/15. If you do this, CCD
Transfer of the accumulated charge from one cell of the shift register (SR) to the image signal output circuit (VS) is performed at the falling edge of the transfer clock pulse, so signal processing, especially A in the A / D converter (ADC) Since it is possible to secure a sufficient / D time and use an inexpensive A / D converter (ADC) with a slow conversion speed, it is possible to reduce the cost of the camera that uses this. Become.

FIG. 8 shows the output of the image signal output circuit (VS) and the amplifier (26) after the shift pulse of the image sensor is transferred to the transfer clock pulse (φ1) (φ2) and the reference signal generation circuit (R).
S) is shown together with the output. In the case of FIG. 7, it is assumed that the CCD shift register (SR) is in an empty state when the shift pulse is generated. To create this empty state, photodiodes (P1) (P2) (P3) ...
The charge accumulated in (Pn-2) (Pn-1) (Pn) is transferred to the CCD shift register (S
R clock pulses (φ1) (φ)
2) should be given to the register. For example, when the number of cells of the register (SR) is 100, if 100 transfer clock pulses (φ1) and (φ2) are given, all the charges accumulated in the register will be discharged. However, it is true that the charge stored in the CCD shift register (SR) is not completely discharged in the first charge discharging operation when the image sensor is started. In this case, therefore, the discharging operation is usually repeated several times. Creates a completely empty state. Such a series of operations is called an initialization operation of the image sensor. In FIG. 8, the photodiodes (P1) (P2) (P3) ... (Pn-2) (Pn
-1) (Pn) accumulated charge is transferred in parallel to the CCD shift register (SR), and the first transfer clock pulse (φ
At the trailing edge of 1), the accumulated charge in the cell (R1) is transferred to the image signal output circuit (VS). As a result, the image signal output circuit (V
S) outputs the output (V _os1 ) corresponding to the accumulated charge of the cell (R1) to the terminal (T3). After that, transfer clock pulse (φ
Every time 1) falls, the output (V _os2 ) (V _os3 ) ... (V _os (n +) corresponding to the accumulated charge of the cells (R2) (R3) ... (Rn + 3)
3)) is sequentially output from the image signal output circuit (VS).
Among these outputs, (V _os1 ) (V _os2 ) (V _os3 ) is an output corresponding to the accumulated charge of the empty feed cells (R1) (R2) (R3), and (V _os4 ) to (V _os4 ). _Vos13 ) is the dark output corresponding to the accumulated charge of the photodiodes (P1) to (P16) coated with aluminum, that is, the cells (R4) to (R13). As shown by ΔS, a difference corresponding to the accumulated charge amount based on the dark current generated in the photodiodes (P1) to (P10) occurs between these two types of outputs.

The output of the calculation circuit (22) shown by (V1) is obtained by calculating V1 = V _ref −V _os for each (V _os ), and the dark outputs (V _os4 ) to (V _os13 ). which corresponds to the output of which (V _OS5) to (V _{OS 12)} of the arithmetic circuits corresponding (22) is taken to the peak value detection circuits described above (24).
Then, the one having the maximum value is output from the peak value detection circuit (24) as (V2). In FIG. 7, the broken line shows this (V2), and therefore V '
= V1-V2 corresponds to the output of the amplifier (26) represented by _Vout = E + (V1-V2) * A.

Next, the operation of the microcomputer (30) shown in FIG. 1 and the operation of the entire circuit by the operation will be described with reference to the flowchart of FIG.

First, when a start signal is given to the microcomputer (30) by operating a switch (not shown), the microcomputer (30) outputs a signal of "1" to the terminal (T22) in step # 1 and the image sensor Perform the initialization operation. That is, transfer clock pulse (φ
1) As (φ2), a fast-cycle clock pulse from the clock circuit (CL2) is input to the CCD shift register (SR) via the terminals (T4) (T5). At this time, the terminal (T1
Since the signal "0" that prohibits the generation of shift pulse is output from 9) and no shift pulse is generated, the CCD shift register (SR) does not receive the accumulated charge from the image sensor array (PA) and The accumulated charges of are sequentially discharged. (Or, do not prohibit the generation of shift pulses,
It is also possible to generate an integration clear pulse as in the normal CCD drive, then immediately generate a shift pulse so that the accumulated charge can be ignored, and then discharge the accumulated charge of the CCD shift register by the transfer clock pulse. ) This discharging operation is repeated several times as described above, so that the CCD shift register (SR) becomes empty. Here, one discharging operation is completed by applying the transfer clock pulses (φ1) (φ2) by the number of processes of the CCD shift register (SR). After a lapse of a predetermined time to guarantee the discharging operation several times, the microcomputer (30) sets the output of the terminal (T22) to "0" and is formed based on the reference clock pulse from the clock circuit (CL1). Input the pulse of which the duration ratio of "1" state and "0" state is 1/15 as transfer clock pulse (φ1) and the pulse of opposite phase as transfer clock pulse (φ2) to CCD shift register (SR) Let Next, the microcomputer (30) outputs a signal of "1" which permits the generation of the shift pulse from the terminal (T19) in the step of # 2, whereby the AND circuit (AN1) is opened. When the integration clear pulse is output from the terminal (T17) in step # 3, the flip-flop (FF
0) is set and the AND circuit (AN2) is also opened. At the same time, the integration clear pulse is input to the integration clear gate (ICG) to clear the accumulated charge of each photodiode of the image sensor array (PA), while the FET (Q1) (Q
4) becomes conductive and the capacitors (C1) and (C2) are charged to the level of the power supply voltage. This integration clear pulse is (t0)
Disappears at each point of time, which causes each photodiode of the image sensor array (PA) to start accumulating charges, and the brightness monitor circuit (MC) at a speed according to the brightness of the subject detected by the monitor light receiving element (PM). Output voltage (V
m) begins to descend as shown in Fig. 5. Further, the microcomputer (30) sets the internal programmable preset counter to # 4 as soon as the integration clear pulse disappears.
Set in the step of, this counter is a predetermined time
Start counting 100 ms. Next, the microcomputer (30) inputs to the terminal (T20) whether or not the drop amount of the output voltage (Vm) of the brightness monitor circuit (MC) has reached 2.8V in step # 5. ) Output (e), the output (e) is "1", the fifth
When it is determined that the case is shown by (15) in the figure, # 9
Go to step and set the output of the terminal (T19) to “0”,
Disables the generation of shift pulses. However, when the output (e) becomes "1", as shown in FIG. 6, the reset pulse is continuously output from the D flip-flop (DF1) and the shift pulse is output from the D flip-flop (DF2) within an extremely short time. The reset pulse resets the flip-flop (FF0) and the AND circuits (AN1) (AN2).
Is closed, the shift pulse which is prohibited from being generated in the step of # 9 is a shift pulse which may be newly generated after the step of # 10 described later. On the other hand, the output (e) is "0" in the step of # 5, and (1) (l
2) If it is determined to be one of the cases shown in (l3) and (l4), the microcomputer (30) subtracts “1” from the contents of the programmable preset counter described above in step # 6, and the microcomputer At the step, it is judged whether or not the content of the counter becomes "0". If the content is not "0", the process returns to step # 5 and # 6
Then, in step # 7, it is determined again whether the content of the programmable preset counter becomes "0". Here, if the time required for the step cycle of # 5, # 6, and # 7 is ts, it is set such that ts × N = 100 msec. Therefore, N times # 5, # 6, and # 7 are set.
If the steps of are repeated, the contents of the programmable preset counter become "0". That is, if 100 msec has elapsed after this counter was set in step # 4,
In the step of the microcomputer (30) # 8, a signal of "1" is output from the terminal (T18), and this signal is passed through the AND circuit (AN1) (OR1) to the D flip-flop (DF1).
Input to the D input of. Therefore, a reset pulse is output from the D flip-flop (DF1), the flip-flop (FF0) is reset, and the AND circuit (AN1) (AN
While 2) is closed, a shift pulse is subsequently generated from the D flip-flop (DF2). However, even in this case, the time elapses further and the output voltage (V
When the drop amount of m) reaches 2.8 V, the output (e) of the brightness determination circuit (40) becomes "1", which is determined in the step of # 5. A "0" signal that prohibits pulse generation is output.

The shift pulse generated as described above is input to the terminal (T21) of the microcomputer (30) and also to the shift gate (SG) via the terminal (T7). As a result, the accumulated charge of each photodiode of the image sensor array (PA) is transferred to the corresponding cell of the CCD shift register (SR), and the transfer clock pulse (φ
1) (φ2) sequentially transfers the accumulated charge of each cell of the register (SR) to the image signal output circuit (VS). Then, image signals (V _os1 ) (V _os2 ) ... (V _os (n + 3)) are sequentially output from the output terminal (T3) of the image signal output circuit (VS), and V _out = E + from the amplifier (26). (V1-V2) A
The signals represented by are sequentially output. These signals are sequentially converted into digital signals by the A / D converter (ADC) and input to the microcomputer (30) via the data bus (DB1).

On the other hand, when the above-mentioned shift pulse is input to the terminal (T21), the microcomputer (30) outputs an integral clear pulse from the terminal (T17) in step # 10. For this reason,
The accumulated charge of each photodiode of the image sensor array (PA) is cleared, and the charge accumulation of each photodiode is restarted at the same time when the integration clear pulse disappears.
Of course, the output of the brightness monitor circuit (MC) also starts to drop at a speed corresponding to the brightness of the subject detected by the monitor light receiving element (PM) as described above. That is, although the second charge storage cycle is started, the microcomputer (30) causes the internal programmable preset counter to count the number of cells of the CCD shift register (SR) at the same time when the integration clear pulse disappears. Set to. This is step # 11. The microcomputer (30) receives a digital signal corresponding to the accumulated charge of each cell from the A / D converter (ADC) and stores it in the internal random access memory (step # 12), and each time it receives it. Then, 1 is subtracted from the contents of the programmable preset counter (step # 13), and it is determined in step # 14 whether the contents become "0". #
When the contents of the programmable preset counter set in step 11 become "0", the process proceeds to step # 15. Microcomputers at this step (30)
Calculates the focus adjustment state of the taking lens (TL), that is, the defocus amount and the defocus direction with respect to the planned focal plane (F) by performing the following calculation, for example. That is,
Photodiodes (P1) (P2) (P3) ... (Pn-2) (Pn-1) (Pn) to (Pn) of the image sensor array (PA)
Among those excluding 1) to (P10), those included in the area where the above-mentioned first image is formed in FIG. 4 are the photodiodes of the reference portion and those included in the area where the second image is formed. The photodiode of the reference portion is used, and the photodiodes of the reference portion and the reference portion are provided from one side of the image sensor array (PA) (A1) (A2) ... (Am), (B).
1) When (B2) ... (Bm + K-1), the digital signals from the A / D converter (ADC) corresponding to the charges accumulated in them are (a1) (a2) ... (am), ( b1) (b2)… (b2m
+1) Performs set of K operations, obtaining what the minimum among the _{C1, C2 ... C k-1} , C k. For example, when the value of C2 is the minimum, the photodiodes (B2), (B3), ...
The image formed at m) (Bm + 1) is the best match. Therefore, in this case, the space between the photodiodes (A1) and (B2) on the image sensor array (PA) is the space between the first and second images described above, which is determined by the focus detection optical system during focusing. By comparing the predetermined distance between the first and second images, it is possible to calculate the defocus amount and the defocus direction of the taking lens at that time. Note that the calculation method described here is an example, and in order to more accurately determine the defocus amount, for example, the applicant of the present invention has a Japanese Patent Application No. Sho 58-2622,
The calculation method proposed in Japanese Patent Application No. 58-113936 may be used.

After the above calculation in step # 15, the microcomputer (30) again determines the voltage drop amount of the output (Vm) of the brightness monitor circuit (MC) based on the output (e) of the brightness determination circuit (40). In step # 16, it is determined whether or not the voltage reaches 2.8V in the period from step # 11 to # 15. To execute the steps from # 11 to # 15, for example,
It shall take 50 ms. The output (e) is "1",
If the voltage drop amount of the output (Vm) has reached 2.8V, the integration clear pulse is output again from the terminal (T17) in step # 17, and the image sensor array ( PA) clear the charge stored in each photodiode and let them start charge storage again. This is because if the output (e) is "1" at the time of the determination in step # 16, the image sensor array (PA)
This is because the charge storage of each photodiode may already be saturated. In this case, the microcomputer (36) sets the internal programmable preset counter in step # 17 at the same time when the integration clear pulse disappears.
It is set to count 100 ms, and then in step # 18, the terminal (T19) outputs a "1" signal that permits the generation of shift pulses. After that, the process returns to step # 5 and the above steps are repeated. On the other hand, if the output (e) is “0” in the step # 16 and the voltage drop amount of the output (Vm) has not reached 2.8V, the microcomputer (30) is programmed by the above step in the step # 19. The preset counter is set so as to count 50 msec, and then the above step # 18 is performed.
At this time, the counter is set to count 50 msec because about 50 msec has already passed from the disappearance of the integral clear pulse output in step # 10 as described above, and the remaining 50 msec. This is because if the counter is counted by that counter, the charge accumulation of 100 msec in total is allowed in each photodiode of the image sensor array (PA). That is, in this case, the step cycles # 5, # 7, and # 8 are repeated up to 50 / ts times. of course,
If the programmable preset counter can be used for other purposes without being used for other purposes, set the programmable preset counter to 100 m after the end of step # 10.
It may be set so as to count seconds, and step # 20 is unnecessary.

The operation of the microcomputer (30) and the operation of the entire circuit due to the operation have been described above with reference to FIG.
As can be understood from the above description, in this embodiment, the defocus amount and the defocus amount in the microcomputer (30) are started after the transfer of the accumulated charge of the photodiode of the image sensor array (PA) is started by the shift pulse. The generation of new shift pulses is prohibited until the calculation of the focus direction is completed. Also, each photodiode of the image sensor array (PA) does not have to wait for the calculation to end immediately after the generation of the previous shift pulse. Charge accumulation is starting. The reason for this is as follows.

In other words, drive the shooting lens based on focus detection,
When performing the focus adjustment, the photographing lens can be focused in a shorter time as the number of focus detection operations performed within a fixed time increases. Therefore, considering the time required for one focus detection operation, the charge accumulation (photocurrent integration) time Ti in the CCD image sensor array (PA) and the charge accumulated in the image sensor array are calculated by the CCD shift register ( S
R) to the image signal output circuit (VS), and then the time Td required for signal processing and calculation of the defocus amount and defocus direction (this is called data processing time for convenience). (Ti + Td), and when performing focus detection operation repeatedly and continuously, if the next detection operation is performed after the previous detection operation is completed, it is necessary to perform the detection operation n times. The time is (Ti + Td) × n. However, the speed of charge accumulation (photocurrent integration) in the CCD image sensor array (PA) depends on the intensity of the light incident on it, and if the incident light intensity is low, the speed slows down, and charge accumulation for a long time occurs. Must be done. Therefore, 1
The time required for each focus detection operation becomes long, and the number of focus detection operations that can be performed within a certain period of time is restricted, so that the taking lens cannot be focused in a short time. on the other hand,
In the case of CCD, there is no problem even if the image sensor array (PA) is made to accumulate charges while transferring the accumulated charges from the shift register (SR) to the image signal output circuit (VS). Therefore, the integration clear pulse can be generated immediately after the shift pulse is generated, and in this way, the image sensor array (PA) performs new charge accumulation during the above-described data processing time Td, so that the incident light intensity is reduced. Even if it is low, the time required for one focus detection operation is shortened,
The number of focus detection operations performed within a certain period of time increases, and it becomes possible to focus the taking lens in a short time. However, on the other hand, the CCD shift register (S
R) accumulated charge is being transferred to the image signal output circuit (VS) while new accumulated charge is transferred to the CCD shift register (SR)
Transferred to the CCD (which is possible due to the structure of the CCD)
Old and new accumulated charges are mixed in the shift register (SR), and an erroneous image signal is output. Also, the microcomputer (30) cannot hold a new signal because the data in the random access memory must be held during the calculation in step # 15. Therefore, the shift pulse is prohibited during the above-mentioned data processing time Td.

FIGS. 10A and 10B show how the focus detection operation is repeated in the above embodiment,
In the same figure, (A) is the case of Ti <Td, and (B) is the case of Ti> Td. In the figure (A), the dotted line shows the charge accumulation period after the disappearance of the integration clear pulse generated in step # 10.
The charges accumulated during this period are cleared by the integral clear pulse generated in step # 17 as described above.
On the other hand, as shown in FIGS. 11 (A) and 11 (B), in the case where the photodiode of the image sensor array (PA) is made to start the charge accumulation after the data processing is always finished, as previously assumed. In the figure, (A) shows the case where Ti <Td, and (B) shows the case where Ti> Td. Comparing FIG. 11 (B) with FIG. 10 (B), it can be clearly seen that the number of focus detection operations in a given time increases in the case of the above embodiment.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. For example, not only CCD but also B
BD (Bucket Brigade Device), CID (Charge Injection)
Device), MOS (Metal Oxide Semiconductor) type image sensor, etc. can be used. Also, the focus detection method is not limited to the one using the focus detection optical system shown in FIG. 4, but is disclosed in, for example, Japanese Patent Laid-Open Nos. 54-159259 and 57-70.
No. 504, JP-A-57-45510, etc., a lenslet is arranged on the planned focal plane of the taking lens or a plane conjugate therewith, and a self-scanning image sensor is arranged behind it. As a result, a method of calculating both the defocus amount and the defocus direction as the focus adjustment state of the photographing lens, or JP-A-55-155308, JP-A-57-72110, and JP-A-57-88418. As shown in Fig. Etc., a self-scanning image sensor is arranged on the planned focal plane of the taking lens or on a plane conjugate therewith and before and after it, and only the defocus direction is detected as the focus adjustment state of the taking lens. The present invention can also be applied to the above.

Effects As described above with reference to the embodiments, according to the focus detection apparatus for a camera of the present invention, a reference signal generation circuit adopting an element and a circuit configuration having a reference voltage to be compared with the output of the monitor circuit and having the same characteristics as the monitor circuit. Can be easily secured by. In that case, if the power supply voltage fluctuates and the initial value of the output of the monitor circuit changes, the output of the reference signal generation circuit also changes. Therefore, the output of the monitor circuit has a predetermined level with respect to the output of the reference signal generation circuit. Can always be detected correctly, so that the shift pulse can always be generated at the same timing when the subject brightness condition does not change.

[Brief description of drawings]

FIG. 1 is an overall circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing details of the photoelectric exchange block (1) in FIG. 1, and FIG. 3 is a photodiode constituting each pixel of the image sensor array. And an equivalent circuit diagram of the integration clear gate, FIG. 4 is a diagram showing the focus detection optical system in the above-mentioned embodiment, FIG. 5 is a diagram showing a temporal change of the output of the monitor circuit, and FIG. 6 is a diagram of FIG. A circuit diagram showing a concrete example of the brightness determination circuit (40) and the block (20), FIGS. 7 and 8 are diagrams showing output waveforms in each part of the circuit of FIG. 1, and FIG. A flow chart showing the operation of the computer,
FIGS. 10 (A) and (B) are time charts showing how the focus detection operation is repeated in the above embodiment, and FIG. 11 shows data on each photodiode constituting the image sensor array of the image sensor after data processing. 6 is a time chart showing how the focus detection operation is repeated when charge accumulation is started. (PA) (ICG) (SG) (SR) ... self-scanning image sensor, (PA) ... image sensor array (charge storage unit), (SR) ... shift register (transfer unit), (VS) ... image signal output Circuit, (MC) ... Monitor circuit, (MP) ... Monitor light receiving means, (RS) ... Reference signal generation circuit, (Q1)
(Q4)… Switch element, (C1) (C2)… Capacitance element, (Q
2) (Q3) (Q5) (Q6) ... buffer circuit, (30) ... microcomputer (integral clear pulse generation means), (4
0) (AC4) ... Judgment means, (DF2) ... Shift pulse generation means, (10) ... Transfer clock pulse generation means.

Claims (1)

[Claims] 1. A focus detection device for a camera, which detects a focus adjustment state of a photographing lens based on accumulated charges transferred from a charge accumulation type image sensor array, and a monitor light-receiving element for detecting subject brightness, and the image sensor. An integral clear pulse generating means for generating an integral clear pulse for clearing the accumulated charges in the array, and an output at a predetermined level when the integral clear pulse is input, and thereafter a speed according to the subject brightness detected by the light receiving means. A monitor circuit whose output changes at, and a reference signal generation circuit that generates the reference signal to be compared with the output of the monitor circuit as the output when the integration clear pulse is input. And the output of the monitor circuit reaches a predetermined relationship with the output of the reference signal generation circuit. And a shift pulse generating means for generating a shift pulse for transferring the accumulated charge of the image sensor, both the monitor circuit and the reference signal generating circuit, the switch element whose conduction cutoff state is changed by the integral clear pulse, A capacitive element connected to the switch element, and the output end of the monitor light receiving means is connected to a charge storage path to the capacitive element,
Switch element of the above monitor circuit and reference signal generation circuit,
A focus detection device for a camera, wherein the capacitive element is configured by an element having the same characteristics and a circuit configuration.