JPH0642724B2 - Image sensor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a self-scanning image sensor such as a CCD (charge coupled device).

2. Description of the Related Art When a CCD, for example, is used as a focus detection device for a camera, unnecessary charges are accumulated inside after power is turned on. Therefore, the accumulated charge transfer unit including a CCD shift register must be discharged after discharging the charges. Even if an image signal is obtained based on the accumulated charge output from the image sensor, it does not correctly correspond to the intensity distribution of the subject image on the image sensor, and the focus adjustment state of the taking lens cannot be detected correctly. For this reason,
Immediately after the focus detection command is given, it is necessary to empty the image sensor as an initializing operation to discharge the unnecessary charges, but the unnecessary charges cannot be completely discharged by once or twice of the empty driving, and usually several times or more. Multiple idle drives are required. On the other hand, the normal image sensor drive cannot be performed at a certain speed or higher due to the restrictions (such as the A / D conversion speed of the A / D converter) coming from the processing arithmetic circuit. If they are performed at the same speed, a long time elapses from when a command for starting the focus detection is given until the focus detection is actually enabled, which causes a problem such as losing a shooting opportunity.

Therefore, it is conceivable to switch the speed between the idle drive and the normal drive so that the idle drive is performed at a higher speed. However, in the CCD, not only the charge storage unit including the photodiode but also the charge transfer unit including the CCD shift register is used. The amount of accumulated charge that is sequentially output from the charge transfer unit by the first normal drive when the final high-speed empty drive is completed and the normal drive is performed next after the high-speed empty drive is completed although the optical sensitivity is slightly negligible. However, due to the photosensitivity of the charge transfer unit itself, there is a problem that it does not correspond to the intensity distribution of the subject image on the image sensor.

To explain this in detail, to drive the CCD empty now,
The processing operation circuit is set so that the accumulated charge output from it is not used for focus detection (or the result is not used for lens drive or display even if processing operation is performed).
Then, a pulse of two or more phases called a transfer clock pulse is applied to the CCD image sensor, and unnecessary charges existing in each cell of the charge transfer unit are sequentially transferred between the cells each time the transfer clock pulse is input. Discharge from the end cell. Here, the period of the transfer clock pulse (this is 1 /
H) is set shorter than the normal drive. Further, in this case, transfer of charges from the charge storage unit to the charge transfer unit is prohibited. Considering the case of the last empty drive,
With the first transfer clock pulse, the residual charge of the first cell of the charge transfer section is discharged, while the residual charge of the second cell is the first cell and the residual charge of the third cell is the second charge. If there are M cells, the remaining charge of the Mth cell is transferred to the (M-1) th cell. Due to this transfer, the Mth cell becomes empty, but it takes (1 / H) time to start the transfer by the second transfer clock pulse, so during this period, depending on its own photosensitivity. The charge is slightly accumulated. This charge is transferred to the (M-1) th cell by the second transfer pulse, and then within (1 / H) time until the transfer by the third transfer clock pulse starts. In the (M-1) th-Mth cells, charge accumulation is performed by their own photosensitivity. In this way, immediately after the transfer by the M-th transfer clock pulse is completed in the final empty driving, the (2,3, ... -1) / H, (M-2) / H, (M-3) / H ・
--- The electric charge accumulated over the time of 1 / H exists. Immediately after this, the cycle of the transfer clock pulse is switched to the cycle of normal drive (1 / L) and the first
Assuming that the second normal drive is performed (in the general-purpose drive, the processing operation circuit is set to perform the processing operation based on the charge output from the image sensor, and the charge transfer from the charge storage unit to the charge transfer unit is performed. , The electric charge of the M-th cell of the charge transfer section is 1 /
L, 2 / L, 3 / L ... M / L is discharged over a period of time, and these are sequentially input to the processing arithmetic circuit. That is, the transfer clock pulse cycle is from (1 / H) to (1 / L)
It takes a time of (Mn) / H + n / L until the charge transferred from the Mth cell existing in the nth cell is output from the output terminal of the charge transfer unit at the time of switching to Therefore, the charge accumulation time in the charge transfer portion varies depending on the value of n. This means that, in addition to the difference in the charge amount corresponding to the intensity distribution of the subject transferred from each photodiode of the charge storage unit to each corresponding cell of the charge transfer unit, the charge amount corresponding to the cell position of the charge transfer unit is This means that there is a difference. At this time, correct focus detection cannot be performed even if an image signal is obtained based on the charges output from the charge transfer unit and processed and calculated.

It is an object of the present invention to solve the above-mentioned problems and to provide an image sensor that can always obtain an image signal that correctly corresponds to the object intensity distribution on the image sensor during normal driving.

The image sensor of the present invention is characterized in that charges remaining in the charge transfer portion are discharged at high speed (idle driving), subsequently discharged at normal speed, and then charge accumulation is started. It is a thing.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. Prior to that, first, in the present invention, the image sensor is idle-dried a plurality of times at a high speed and then only once at a normal speed. The reason is explained by the above example.

In the above example, considering the amount of accumulated charge in each cell of the charge transfer unit immediately after the image sensor is idle driven by the transfer clock pulse of the cycle (1 / L), the light sensitivity of each cell is 1, 2,3 ... (M-1) in the Mth cell
/ L, (M-2) / L, (M-3) / L ... Charges accumulated over the time of 1 / L are accumulated. After this cycle (1 /
When driven normally in (L), the charge of each cell is 1 / L, 2 / L,
3 / L ・ ・ ・ ・ M / L is output over time,
Eventually, until the electric charge transferred from the Mth cell existing in the nth cell is output from the output terminal of the charge transfer unit at the time when the idle driving in the cycle (1 / L) is finished, (Mn ) /
It takes a time of L + n / L = M / L, which means that there is no difference in the charge storage time in the transfer unit, that is, the output charge amount, depending on the value of n. Therefore, by performing the idle drive once at normal speed,
Since it is possible to avoid a difference that does not relate to the intensity distribution of the subject image on the image sensor from occurring in the charge amount discharged by the first normal driving, it is always based on the image signal corresponding to the intensity distribution of the subject image. It becomes possible to perform correct focus detection. Even in the normal driving, immediately after the end of the previous normal driving, the electric charge accumulated by multiplying (Mn) / L exists in the n-th cell, but the time until the next normal driving outputs it. Similarly becomes M / L, and the photosensitivity of each cell of the charge transfer section does not affect the image signal.

Next, an embodiment of the present invention will be described with reference to FIGS.

First, in FIG. 1 showing the entire circuit of this embodiment,
(1) is, as will be described later, a photoelectric conversion block including a self-scanning image sensor such as a CCD, an image signal output circuit, a light receiving element for brightness monitor, a brightness monitor circuit, and a reference signal generating circuit, (10) is a transfer clock pulse generation block, (20) is a circuit block that forms a digital signal that is the basis of the focus adjustment state determination of the taking lens based on the signal from the photoelectric conversion block (1), (30)
Is a microcomputer that determines the focus adjustment state of the photographing lens based on the digital signal from the circuit block (20) and controls each circuit block.

Further, (40) controls the amplification factor of the amplifier in the circuit block (20) based on the output of the luminance monitor circuit in the photoelectric conversion block (1), while the self-scanning type in the photoelectric conversion block (1) The brightness judgment circuit that controls the charge storage time (photocurrent integration time) of the image sensor, (AN ₁ ) (AN ₂ ) is the OR circuit (O
R ₁ ) and an AND circuit which constitutes a gate means, (DF ₁ ) is a D flip-flop which generates a reset pulse for resetting flip-flops (FF ₀ ) (FF ₁ ) to (FF ₆ ) described later, (D
F ₂ ) is a D that generates a shift pulse for transferring the charge accumulated in the charge accumulating section in the image sensor to the transfer section.
Flip-flop, (CL ₁ ) is a clock circuit for generating a reference clock pulse, and (FF ₀ ) is an RS flip-flop.

FIG. 2 shows the photoelectric conversion block (1) described above.
Photodiode example (P ₁ ) (P ₂ ) (P ₃ ) ・ ・ ・ ・ (Pn- ₂ ) (Pn- ₁ )
The image sensor array (PA) made of (Pn), the integration clear gate (ICG), the shift gate (SG), and the CCD shift register (SR) constitute the self-scanning image sensor. Here, the number of cells of the CCD shift register (SR), which is the transfer unit, is three more than the number of photodiodes (number of pixels) of the image sensor array (PA), which is the charge storage unit, and the cells (R ₁ ) (R ₂ ) (R ₃ ) is for the blank feed described later, and each photodiode (P ₁ ) (P ₂ ) (P
₃ ) ・ ・ ・ (Pn- ₂ ) (Pn- ₁ ) (Pn) is stored in the cells (R ₄ ) (R ₅ ) (R
₆ ) ... (Rn + ₁ ) (Rn + ₂ ) (Rn + ₃ ) are transferred by a shift pulse. As shown in FIG. 3, each photodiode has a pair of diodes (D ₁ ) connected in parallel to each other via a switch (S) corresponding to an integral clear gate (ICG) with respect to a power source (+ V). ) (D ₂ ) and FET (Q ₁₀ ), one diode
(D ₁ ) is installed to receive light. The FET (Q ₁₀ ) keeps the voltage across the diode (D ₁ ) approximately constant and
It is provided so that the capacitance of (D ₁ ) can be ignored, and its gate is grounded. Now, when the switch (S) is closed, charges are accumulated between the anode and cathode of the diode (D ₂ ),
The anode voltage becomes equal to the power supply voltage. Then, when the switch (S) is opened next, the diode (D ₂ ) is discharged through the FET (Q ₁₀ ) by the photocurrent of the diode (D ₁ ), and its anode voltage drops with the passage of time. That is, this may be considered as a negative charge is accumulated in the cathode of the diode (D ₂ ) at a speed according to the intensity of the light incident on the diode (D ₁ ), and therefore each photodiode is The description will be made assuming that the charges are accumulated at a corresponding speed.

The switch (S) is actually composed of a semiconductor analog switch which becomes conductive by an integration clear pulse input to the integration clear gate (ICG) and becomes non-conductive when the pulse disappears. The shift gate (SG) is a photodiode (P ₁ ) (P
₂ ) (P ₃ ) ・ ・ ・ ・ ・ (Pn− ₂ ) (Pn− ₁ ) (Pn) accumulated charge is received by the shift pulse described later and the cell of CCD shift register (SR)
(R ₄ ) (R ₅ ) (R ₆ ) ... (Rn + ₁ ) (Rn + ₂ ) (Rn + ₃ ) are transferred in parallel. Photodiode (P ₁ ) (P ₂ ) (P ₃ ) ・ ・ ・ ・ ・ (Pn- ₂ )
(Pn- ₁ ) (Pn) charge accumulation is due to shift pulse shift gate (S
It ends by the input to G). Further, the CCD shift register (SR) sequentially accumulates the accumulated charge for one cell at the trailing edge of the transfer clock pulse (φ ₁ ) every time the later-described transfer clock pulse (φ ₁ ) (φ ₂ ) is input. Output to the image signal output circuit. In addition, counting from one end of the image sensor array (PA), a predetermined number (10) of photodiodes (P ₁ ) (P ₂ ) ...
.. (P ₁₀ ) is covered with an aluminum film and is used for setting the reference level of the image signal as described later.
(T ₈ ) and (T ₉ ) in Fig. 2 are the above-mentioned image sensor and circuit (MC).
This is a power supply terminal for supplying power (+ V) to (RS) and (VS).
Further, (AN ₀ ) is an AND circuit provided to pass only the shift pulse synchronized with the transfer clock pulse (φ ₁ ).

By the way, the position of the image sensor array (PA) in the camera depends on the focus detection method. FIG. 4 shows an example of a focus detection optical system to which the present invention can be applied. (TL) is a taking lens, (CL) is a condenser lens, and (L ₁ ) (L ₂ ) is a taking lens (TL). The main optical axis of
a pair of re-imaging lenses symmetrically arranged with respect to (l), (M)
Is a mask, and (F) is a planned imaging plane of the taking lens (TL) equivalent to the film surface of the camera. According to this optical system, when a subject image is formed by the taking lens (TL) on or before and after the planned image forming surface (F), the re-imaging lenses (L ₁ ) and (L ₂ ) are The image is re-formed as the first and second images on the image sensor array (PA), but the interval between the first and second images on the image sensor array (PA) is the focus adjustment state of the taking lens (TL). That is, it changes depending on the shift state of the subject image formed thereby with respect to the planned imaging plane (F). Therefore, if the distance between the first and second images is detected based on the output of each pixel of the image sensor array (PA), the taking lens (T
The defocus amount and the defocus direction indicating the focus adjustment state of L) can be determined, and the output processing method required for that will be described later. In FIG. 4, the image sensor array (PA) is located at a position conjugate with the planned image forming plane (F) with respect to the condenser lens (CL) and the pair of re-imaging lenses (L ₁ ) (L ₂ ), or its conjugate position. It is placed in the vicinity.

In FIG. 2 again, (MP) is a photodiode which is a light receiving element for brightness monitor, (MC) is a brightness monitor circuit, and (R
S) is a reference signal generation circuit, and (VS) is an image signal output circuit. The brightness monitor circuit (MC) consists of FET (Q ₁ ) (Q ₂ ) (Q ₃ ) and capacitor (C ₁ ). The gate of the FET (Q ₁ ) is connected to the integral clear gate (ICG) of the image sensor, and the FET (Q ₁ ) is turned on by the integral clear pulse passing through the integral clear gate (ICG), which causes the capacitor (C ₁ )
Is charged to the level of the power supply voltage (+ V). FET (Q ₁₎ and the connection point of the capacitor (C ₁₎ (J ₁₎ is while being connected to the anode of the FET photodiode through (Q ₁₂₎ (MP), is connected to the gate of the FET (Q ₂₎ ing. The gate of the FET (Q ₁₂ ) is grounded, and the voltage across the fort diode (MP) is kept substantially constant so that the influence of the capacitance can be ignored. FET (Q ₂ ) (Q ₃ ) are connected in series to the power supply and form a buffer with low output impedance and high input impedance.Because FET (Q ₃ ) is used as a source follower. , The voltage (Vm) corresponding to the potential of the connection point (J ₁ ) is output from the output terminal (T ₁ ) drawn from the connection point of the FETs (Q ₂ ) and (Q ₃ ). When the integration clear pulse disappears, the FET (Q ₁ ) becomes non-conductive, the capacitor (C ₁ ) is discharged by the photocurrent of the photodiode (MP), and the output voltage of the terminal (T ₁ ) drops accordingly. Fifth
The figure shows the change over time of the output voltage at this terminal (T ₁ ). (L ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) shows that the rate of voltage drop depends on the brightness. It shows that it changes. The rising edge indicated by (RN) represents the noise induced by the integral clear pulse.

The reference voltage generator (RS) consists of FETs (Q ₄ ) (Q ₅ ) (Q ₆ ) and capacitors (C ₂ ), which are the above-mentioned FETs (Q ₁ ) (Q ₂ ).
(Q ₃ ) and capacitor (C ₁ ) have the same characteristics,
The circuit connection is also FET (Q ₁ ) in the brightness monitor circuit (MC).
It is the same as the circuit connection of (Q ₂ ) (Q ₃ ) and capacitor (C ₁ ).
However, FET (Q in FET (Q ₄₎ and the connection point of the capacitor (C ₂₎ (J _2)
5 ) gates are only connected, and therefore
FET (Q ₅ ) that forms a buffer with low output impedance and high input impedance, similar to FET (Q ₂ ) (Q ₃ ).
The voltage signal output from the output terminal (T ₂ ) drawn from the connection point of (Q ₆ ) is kept constant as shown in FIG. 5 even after the integration clear pulse disappears. That is, the potential of the connection point (J ₁ ) (J ₂ ) immediately after the disappearance of the integration clear pulse (t ₀ ) is equal to that of the FET (Q ₁ ) (Q ₂ ) (Q ₃ ) and the capacitor (C ₁ ) as described above. FET (Q ₄ ) (Q ₅ )
Since the characteristics of (Q ₆ ) and the capacitor (C ₂ ) are the same, they are equal to each other, so the voltage signal output from the terminal (T ₂ ) is equal to the luminance of the voltage signal output from the terminal (T ₁ ). It can be used as a reference voltage (Vref) for obtaining a dependent drop amount.

The image signal output circuit (VS) is composed of FETs (Q ₇ ) (Q ₈ ) (Q ₉ ) and capacitors (C ₃ ), and preferably FET (Q ₁ ) (Q ₂ ).
Use the same characteristics as (Q ₃ ) and capacitor (C ₁ ) respectively. However, in the circuit connected to the gate of the FET (Q ₇₎ being adapted to transfer clock pulse (phi ₁₎ is applied, Moreover, FET (Q ₇₎ and the connection point of the capacitor (C ₃₎ ( J ₃ ) is FET
It is connected to the gate of (Q ₈ ) and the transfer terminal of the CCD shift register (5) of the image sensor. Therefore, every time one transfer pulse (φ ₁ ) is input, the FET (Q ₇ ) becomes conductive and the capacitor (C ₃ ) is charged to the level of the power supply voltage (+ V), and the image signal output circuit ( VS) is reset, but it is repeatedly discharged according to the charge accumulated in the CCD shift register (5) transferred by each transfer pulse (φ ₁ ) and eventually forms a buffer with low output impedance and high input impedance. From the output terminal (T ₃ ) drawn from the connection point of the FETs (Q ₈ ) and (Q ₉ ) that are connected to each other, the output corresponding to the accumulated charge of each photodiode that is a pixel of the image sensor is sequentially output as a voltage signal (V _os ), which together form the image signal.

Although (C ₁ ) (C ₂ ) (C ₃ ) in the above circuits (MC) (RS) (VS) is described as a capacitor for convenience of explanation, it can be replaced with a PN junction of a diode, When integrating these circuits, each is manufactured as a diode. In addition, the photodiode (M
P) is arranged near the image sensor array (PA) so as to receive a part of the light that has passed through the taking lens.

Next, referring again to FIG. 1, an example of the circuit configuration of the transfer clock pulse generation block (10) for generating the transfer clock pulses (φ ₁ ) (φ ₂ ) will be described. (FF ₁ ) (FF ₂ ) ・ ・ ・
(FF ₆ ) is a flip-flop circuit that forms a frequency divider circuit, and the clock pulse (cycle 2 μsec) from the clock circuit (CL ₁ ) is input to the T input of the _first -stage flip-flop (FF ₁ ). Q of flip-flop (FF ₃ ) (FF ₄ ) (FF ₅ ) (FF ₆ )
Outputs are respectively input in an OR circuit (OR _2), the output of the OR circuit (OR ₂₎ is input to one input of the AND circuit (AN _4). The other input of the AND circuit (AN ₄ ) is connected to the terminal (T) of the microcomputer (30) via the inverter (IN ₁ ).
₂₂ ), and when the terminal (T ₂₂ ) outputs a signal of "0", the output of the OR circuit (OR ₂ ) is output from this AND circuit (AN ₄ ). On the other hand, input AND circuit (AN ₅₎ is the one being connected to the Q output of the flip-flop (FF _2), the other input is connected to the aforementioned terminal (T _22), thus the above-mentioned terminals (T ₂₂ ) Outputs a signal of “1”, the Q output of the flip-flop (FF ₂ ) is output. Here, the Q output of the flip-flop (FF ₂ ) is a clock pulse having a period of 8 μsec. The OR circuit (OR ₃ ) is the AND circuit (AN ₄ ) (A
When any output signal of N ₅ ) is "1", the signal of "1" is used as the transfer clock pulse (φ ₂ ) in the photoelectric conversion block.
Output to CCD shift register (SR) in (1). Further, an inverter (IN ₂ ) is connected to the OR circuit (OR ₃ ), and this inverter (IN ₂ ) uses a signal having a phase opposite to that of (φ ₂ ) as a transfer clock pulse (φ ₁ ) for the photoelectric conversion block. C in (1)
It outputs to the CD shift register (SR) and the image signal output circuit (VS) (see FIG. 2). The microcomputer (3
0 signal "1" from the terminal (T ₂₂₎ of) is a signal for causing empty driving of the image sensor at high speed.

FIG. 6 shows an example of the brightness determination circuit (40) and the circuit block (20). In this figure, (T ₁₀ ) (T ₁₁ ) (T ₁₂ ) are terminals connected to terminals (T ₁ ) (T ₂ ) (T ₃ ), respectively, and terminal (T ₃ ).
(T ₄ ) is connected to the terminal (T ₁₁ ) via the buffer (B ₂ ). With such circuit connection, the connection point (J ₄ ) (J ₅ ) (J ₆ ).
The voltage (Vref) of the reference voltage generation circuit (RS) applied to the terminal (T ₁₁ ) is applied to (J ₇ ) by resistors (R ₁ ) (R ₂ ) (R ₃ ) (R ₄ ), respectively. A voltage is generated by subtracting the voltage drop, and the resistance (R ₁ ) (R ₂ )
By selecting the resistance value of (R ₃ ) (R ₄ ) and the current value of the constant current source (I ₁ ) (I ₂ ) (I ₃ ) (I ₄ ), the above-mentioned input to the terminal (T ₁₀ ). The output of the comparator (AC ₁ ) (AC ₂ ) (AC ₃ ) (AC ₄ ) sequentially changes from “0” to “1” according to the voltage drop of the output voltage (Vm) of the brightness monitor circuit (MC). Flip to. For (DF ₃ ) (DF ₄ ) (DF ₅ ), the D input is connected to the output of the comparator (AC ₁ ) (AC ₂ ) (AC ₃ ).
These are flip-flops, and the shift pulse from the D flip-flop (DF ₂ ) is input to these CP inputs.
The shift pulse is generated at the terminal (T ₁₄ ) as described later.
Rises to “1”, or when the terminal (T ₁₈ ) of the microcomputer (30) rises to “1” after a predetermined time (100 msec) has passed from the fall of the integration clear pulse. is there.

Then, when the shift pulse is input, the D flip-flops (DF ₃ ) (DF ₄ ) (DF ₅ ) turn on the comparators (AC ₁ ) (AC ₂ ) immediately before.
The output of (AC ₃ ) is output to the Q output, and the inverted output is output from the output. (AN ₆ ) is an AND circuit in which one input is connected to the Q output of the D flip-flop (DF ₃ ) and the other input is connected to the output of the D flip-flop (DF ₄ ), and (AN ₇ ) is one input Is an AND circuit connected to the Q output of the D flip-flop (DF ₄ ) and the other input to the output of the D flip-flop (DF ₅ ), and the output (b of the AND circuit (AN ₆ ) (AN ₇ ) (b ) (c), D flip-flop (DF ₃ ) output (a), (DF ₅ )
Q output (d) and the output (e) of the comparator (AC ₄ ) become the output of the brightness determination circuit (40). That is, those outputs become signals indicating the brightness level detected by the monitor light receiving element (PM).

This will be described in more detail with reference to FIG.
In the figure, (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) is the point at which the integration clear pulse disappears (t ₀ ).
From 0.35V to 0.7 when the voltage drop that occurs from the above to the above-mentioned predetermined time (100msec) (t ₃ ) is less than 0.35V, respectively.
From 0.7V to less than V, from 1.4V to less than 1.4V
It shows the output voltage change of the brightness monitor circuit (MC) when it is less than 2.8V, and (l ₅ ) is the time when the integration clear pulse disappears.
At the time (t ₂ ) before the above-mentioned predetermined time (100 msec) elapses from (t ₀ ).
It shows the output voltage change of the same monitor circuit (MC) when the voltage drop of 2.8V occurs. Which voltage drop of (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) depends on the magnitude of the photocurrent of the monitor light receiving element (MP) as described above. If the output voltage change of the brightness monitor circuit (MC) is (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ), it is low brightness, and if it is (l ₅ ). This is the case of high brightness. Now, the voltage at the terminals (J ₄ ) (J ₅ ) (J ₆ ) (J ₇ ) is 0.35% less than the output voltage (Vref) of the reference voltage generator (RS) input to the terminals (T ₁₁ ), respectively. V, 0.7V, 1.4V, 2.8V
The resistance value of the above resistance (R ₁ ) (R ₂ ) (R ₃ ) (R ₄ ) and the current value of the constant current source (I ₁ ) (I ₂ ) (I ₃ ) (I ₄ ) If you set
Q output of D flip-flop (DF ₃ ) (DF ₄ ) (DF ₅ ), corresponding to (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) after the shift pulse is generated.
Output and output of brightness monitor circuit (MC) (a) (b) (c) (d)
(e) is as shown in Table 1 below.

In the case of (l ₅ ), the output (e) of the comparator (AC ₄ ) becomes “0” at the time (t ₂ ) before the predetermined time (100 msec) elapses from the time (t ₀ ) when the integration clear pulse disappears. It changes from "1" to "1", the terminal (T ₁₄ ) is set to "1", and a shift pulse is generated in the D flip-flop (DF ₂ ).

The remaining circuit of FIG. 6 constitutes the circuit block (20) of FIG. (22) is the output voltage (V _os ) of the image signal output circuit (VS) input from the terminal (T ₁₂ ) via the buffer (B ₃ ) and the terminal (T ₁₁ ) via the buffer (B ₂ ). Output (V ₁ ) corresponding to the difference from the output voltage (Vref) of the reference signal generator (RS) input from
Is a subtraction circuit for generating. (24) is covered with an aluminum film in the image sensor array (PA) and a predetermined number (10)
Number) of photodiodes (P ₁ ) (P ₁₀ ) excluding the diodes (P ₁ ) and (P ₁₀ ) at both ends of the photodiode (P ₁ ) corresponding to the accumulated charge of the image signal peak value (V ₂ ) (at the lowest level) Pixel signal) is detected, and it is output by latching it, which allows the image sensor array (PA) that is not covered with the aluminum film to receive the first and second images described above. A signal V _{2 serving as} a reference level is formed with respect to the pixel signal corresponding to the accumulated charge of the photodiode. That is, the microcomputer (30) uses the transfer clock pulse (φ ₁ ) (φ ₂ ) for the CCD system register.
When the accumulated charge is sequentially transferred from (SR) to the image signal output circuit (VS), the sampling instruction pulse is sent via the data bus (DB ₁ ) at the same time as the start of the transfer of accumulated charge of the cell (R ₅ ) to the terminal (T ₁₅ ), and then, at the same time as the transfer of the accumulated charge of the cell (R ₁₂ ) is completed, a sample designated reset pulse is output to the terminal (T ₁₆ ) via the data bus (DB ₁ ). Therefore, the peak value detection circuit (24) takes in the corresponding image signals of the accumulated charges of the cells (R ₅ ) to (R ₁₂ ), in other words, the accumulated charges of the photodiodes (P ₂ ) to (P ₉ ), and Of these, the peak value will be detected.

(26) is an amplifier that differentially amplifies the output signals (V ₁ ) and (V ₂ ) of the circuits (22) and (24), and the amplification factor thereof is the above-described luminance determination circuit (4
0) is an amplifier configured to be controlled by outputs (a) (b) (c) (d). In this amplifier, (OP) is an operational amplifier, and its input terminals (f) and (g) are connected to circuits (22) and (24) via input resistors (R ₅ ) and (R ₆ ), respectively. . (R ₇ ) to (R ₁₄ ) are resistors provided for setting the amplification factor of the operational amplifier (OP), and (R ₅ ) (R ₆ ) (R ₇ ) (R ₈ ) (R ₁₁ ) ( When the resistance value of R ₁₂ is r, (R ₉ ) (R ₁₃ ) is the resistance value of 2r, and (R ₁₀ ) (R ₁₄ ).
Has a resistance of 4r. (AS ₁ ) to (AS ₈ ) are analog switches, of which (AS ₁ ) to (AS ₄ ) are outputs (a) and (b).
According to (c) and (d), the resistors (R ₇ ) to (R ₁₀ ) are selectively enabled to set the feedback resistance value of the operational width device (OP), while (A
S ₅₎ to (AS ₈₎ is a bias resistor of the output (a) (b) (c ) ( resistance in accordance with d) (R ₁₁₎ to (R ₁₄₎ selectively enabled to the amplifier (OP) Set the value. That is, the above (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l
The states of the analog switches and the resistances to be activated when the voltage drops of ₅ ) occur are as shown in Table 2 below.

In the above table, A is the amplification factor of the operational amplifier (OP), and the output voltage of this amplifier (OP) is represented by Vout = E + (V ₁ −V ₂ ) × A, which is the A / D converter ( ADC). However, E is the voltage of the constant voltage source (E), and is set appropriately according to the input level range of the A / D converter (ADC). Then, the output of the A / D converter (ADC) corresponding to each pixel signal is taken into the microcomputer of FIG. ₁ via the data bus (DB ₁ ), and is photographed by digital calculation based on a predetermined program. The focus adjustment state of the lens is detected. Thus, the amplifier (26) of FIG.
Changes the amplification factor according to the output of the brightness determination circuit (40),
Since it outputs a signal suitable for signal processing in an A / D converter (ADC), it is possible to adjust the focus state of the taking lens in a wide range of brightness.

Referring again to FIG. 1, the microcomputer
The terminal (T ₁₇ ) of (30) is the output terminal of the integral clear paris. Also, the signal (1) is output from the terminal (T ₁₉ ) of the microcomputer (30) when the generation of the shift pulse is permitted, and the image sensor array (PA) transfers the CCD shift register (SR) as described later. A signal "0" for inhibiting the generation of the shift pulse is output during the transfer of the accumulated charge to the.
Furthermore, from the terminal (T ₁₈ ) of the microcomputer (30),
When the above-mentioned predetermined time elapses from the extinction time (t ₀ ) of the integration clear pulse, a signal of "1" is output, and a shift pulse is generated from the D flip-flop (DF ₂ ) in response to this signal. The integral clear pulse output from the terminal (T ₁₇ ) is the terminal
While being input to the integration clear gate (ICG) of the image sensor in the photoelectric conversion block (1) via (T ₆ ), the flip-flop (FF ₀ ) is set and its Q output is set to “1”.
Then open the AND circuit (AN ₁ ). Also, when the flip-flop (FF ₀ ) is set and the signal (1) that permits the generation of the shift pulse is output from the terminal (T ₁₉ ),
And circuit (AN ₂ ) is also opened. From the output terminal (T ₁₄ ) of the brightness determination circuit (40), only when the subject brightness is high as shown in (l ₅ ) of FIG. ₅ , a predetermined value from the disappearance time (t ₀ ) of the integration clear pulse is determined. Time (t ₂ ) before time (100 ms) has elapsed
Outputs the signal (e) of "1". On the other hand, when the subject brightness is low, as shown by (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) in FIG. 5, the terminal of the microcomputer (30)
The output of (T ₁₈ ) becomes “1” at the time of (t ₃ ), and the output (e) of the output terminal (T ₁₅ ) of the brightness determination circuit (40) is kept at “0”.
Therefore, if the subject brightness is high, the AND circuit (AN ₂ )
Output becomes “1” at the time of (t ₂ ), and when the subject brightness is low, the output of the AND circuit (AN ₁ ) becomes “1” at the time of (t ₃ ), and either one of the “1” becomes “1”. The output of "" is input to the D input of the D flip-flop (DF ₁ ) via the OR circuit (OR ₁ ). Since the reference clock pulse (cycle 2 μsec) from the clock circuit (CL ₁ ) is input to the CK (clock) input of this D flip-flop, as shown in FIG.
Immediately after the "1" signal is input to the D input, the Q output of the D flip-flop (DF ₁ ) becomes "1" at the falling edge of the reference clock pulse, and the flip-flop (FF ₀ ) is reset and opened. The AND circuit (AN ₁ ) or (AN ₂ ) that had been used is closed, and the flip-flops (FF ₁ ) to (FF ₆ ) in the transfer clock pulse generation block (10) are reset, and their Q outputs (Q ₁ ) Through (Q ₆ ) all become “0”. Then, when the AND circuit (AN ₁ ) or (AN ₂ ) is closed in this way, the D flip-flop (D
The Q output of F ₁ ) returns to "0", and eventually 2 from that Q output.
This means that a positive pulse with a time width of μ seconds has been output. This positive pulse is the reset pulse. On the other hand, the Q output of the D flip-flop (DF ₂ ) is “1” at the falling edge of the reference clock pulse from the clock circuit (CL ₁ ) immediately after the Q output of the D flip-flop (DF ₁ ) becomes “1”. Then, immediately after the Q output of the D flip-flop (DF ₁ ) returns to "0", the Q output returns to "0" at the falling edge of the reference pulse of the same clock circuit. Therefore, a positive pulse having a time width of 2 μsec which rises in synchronization with the falling edge of the reset pulse is generated at the Q output of the D flip-flop (DF ₂ ), which is a shift pulse. This shift pulse is input to the terminal (T ₂₁ ) of the microcomputer (30) and also to the shift gate (SG) of the image sensor in the photoelectric conversion block (1) via the terminal (T ₇ ). Brightness judgment circuit (40) terminal (T
It is also entered in ₁₃ ).

The above is a description of the entire circuit configuration of FIG. 1 and the circuit blocks constituting the same. Prior to describing the overall operation, refer to FIG. 7, FIG. 8 and FIG. The signals in each section will be described.

FIG. 7 shows that the outputs of the flip-flops (FF ₁ ) to (FF ₆ ) immediately after being reset by the reset pulse generated at the Q output of the D flip-flop (DF ₁ ) are also transferred clock pulses (φ
₁ ) and the shift pulse which is the Q output of the D flip-flop (DF ₂ ) is shown. As described above, the flip-flops (FF ₁ ) to (FF ₆ ) are reset at the rising edge of the reset pulse, and their Q outputs (Q ₁ ) to (Q ₆ ) are all “0”. As a result, the output of the OR circuit (OR ₂ ) becomes “0”, so that the transfer clock pulse (φ ₂ ) falls to “0” and conversely the transfer clock pulse (φ ₁ ) rises to “1”. . Then, after 2 μs has elapsed, the reset pulse falls, and at the same time, the shift pulse rises to “1”,
This shift pulse falls to “0” after another 2 μsec.
Next, the output of the OR circuit (OR ₂ ) becomes “1” when the Q output (Q ₃ ) of the flip-flop (FF ₃ ) becomes “1”, which means that the reset pulse is “0”. After falling to "8
After μ seconds, the transfer clock pulse (φ ₁ ) is 10
The microsecond is kept at "1". The shift pulse is generated and disappears while the transfer clock pulse (φ ₁ ) is in the “1” state. Thus, the transfer clock pulse generation block (10) is reset immediately after the time point (t ₂ ) or (t ₃ ),
The shift pulse is generated while the newly output transfer clock pulse (φ ₁ ) continues, because the photodiode array (P ₂ ) (P ₂ ) (P ₂ )
₃₎ it is _{··· (Pn- 2) (Pn- 1} ) charge accumulation (Pn) (to avoid the end of the integration) is delayed unnecessarily. If this is
(t ₂₎ or that caused a shift pulse in synchronism with the transfer clock pulses occurring 1st after time point _{(t 3) (φ 1)} , from the time of (t ₂₎ or (t ₃₎ About one cycle of transfer clock pulse at maximum Photodiode (P ₁ ) (P ₂ ) (P ₃ )
_{··· (Pn- 2) (Pn- 1} ) (Pn) may charge accumulation is performed unnecessarily, and when the object is very bright saturated charge storage, correct image signal is obtained There is a risk of disappearing. Further, since it is not always constant at which time point after the time point (t ₂ ) or (t ₃ ) the shift pulse is generated, the problem that the image signal level is not constant may occur. On the other hand, in FIG. 7, since there is always a shift pulse within two cycles (4 μsec) of the reference clock pulse from the time point (t ₂ ) or (t ₃ ), there is no such fear.

Figure 8 shows the transfer clock pulse (φ ₁ ) during idle driving.
And the output from the terminals (T ₁₇ ) (T ₂₂ ) of the microcomputer (30). When the power is turned on, the clock circuit (CL ₁ ) outputs a clock pulse with a period of 2 μs and the flip-flop ( clock pulse period 8μ seconds from the Q output (Q ₂₎ of the FF ₂₎ is outputted. When a focus detection start signal is given to the microcomputer (30) in this state, a signal of "1" is output from the terminal (T ₂₂ ), the AND circuit (AN ₅ ) is opened, and the flip-flop (FF ₂ ) Q output (Q
₂ ) is output as a transfer clock pulse (φ ₂ ) via the AND circuit (AN ₅ ) and the OR circuit (OR ₃ ), and the transfer clock pulse (φ ₁ ) is output from the inverter (IN ₂ ). To be done. Therefore, the period of (φ ₁ ) (φ ₂ ) is 8 μs, and the CCD shift register (SR) is set at each falling edge of (φ ₁ ).
Charge transfer is performed. Meanwhile, a microcomputer
(30) outputs a signal of "1" from the terminal (T ₂₂ ), and at the same time, causes an internal timer to drive the idle drive clock cycle Tx at a predetermined high speed
(8 μs × (SR) number of cells N × number of high-speed idle driving), and within the idle driving time Tx, generation of integral clear pulse from terminal (T ₁₇ ) and output from terminal (T ₁₉ ). The generation of the shift pulse generation enable signal is prohibited and the data bus
The signal from the A / D conversion circuit (ADC) received via (DB ₁ ) is not calculated, or the calculated result is used for driving the shooting lens (TL) or for focus detection display. Do not output. When the idle time Tx at high speed elapses, the terminal (T ₂₂ )
Output falls to “0”, which causes the AND circuit (A
The AND circuit (AN ₄ ) is opened instead of N ₅ ), and the output of the OR circuit (OR ₂ ) is transferred as a transfer clock pulse (φ ₂ ) via the AND circuit (AN ₄ ) and the OR circuit (OR ₃ ). Then, the transfer clock pulse (φ ₁ ) is output from the inverter (IN ₂ ) and inverted. Here, the output of the OR circuit (OR ₂ ) is the Q output of the flip-flops (FF ₃ ) (FF ₄ ) (FF ₅ ) (FF ₆ ).
₃ ) (Q ₄ ) (Q ₅ ) (Q ₆ ), which is (φ ₁ )
Becomes a pulse having a period of 128 μsec as shown in FIG.
On the other hand, at the same time when the output of (T ₂₂ ) is set to “0”, the microcomputer (30) resets the internal timer to the idle driving time Ty (128 μsec × the number of cells N of (SR)) at the normal speed. Then, when this idle drive time elapses, the integration clear pulse is output from the terminal (T ₁₇ ), and then the shift pulse generation enable signal is output from the terminal (T ₁₉ ). ).

Figure 9 shows the image signal output circuit (VS) after shifting to normal drive.
And output of amplifier (26) transfer clock pulse (φ ₁ )
(Φ ₂ ) and the output of the reference signal generation circuit (RS).

In FIG. 9, the accumulated charges of the photodiodes (P ₁ ) (P ₂ ) (P ₃ ) ... (Pn- ₂ ) (Pn- ₁ ) (Pn) due to the generation of the shift pulse are transferred to the CCD shift register (SR). In parallel, and the charge of the cell (R ₁ ) is transferred to the image signal output circuit (VS) at the trailing edge of the _first transfer clock pulse (φ ₁ ). As a result, the image signal output circuit (VS) outputs an output (Vos ₁ ) corresponding to the charge of the cell (R ₁ ) to the terminal (T ₃ ). Thereafter transfer clock pulse (phi ₁₎ is in each Tatsukudaru, cell (R ₂₎ (R ₃₎ output corresponding to the charge _{··· (Rn + 3) (Vos} 2) (Vos 3) ··· (Vos ( (n + 3) are sequentially output from the image signal output circuit (VS).
os ₁ ) (Vos ₂ ) (Vos ₃ ) is the output corresponding to the charge of the empty feed cells (R ₁ ) (R ₂ ) (R ₃ ), and (Vos ₄ )-(Vos ₁₃ ) are aluminum. The output corresponds to the charge of the coated photodiodes (P ₁ ) to (P ₁₀ ), that is, the cells (R ₄ ) to (R ₁₃ ). Between these two types of output, as shown by ΔS,
There is a difference corresponding to the amount of accumulated charge based on the dark current generated in the photodiodes (P ₁ ) to (P ₁₀ ). The output of the calculation circuit (22) indicated by (V ₁ ) is V ₁ = Vref-Vos for each (Vos).
Of the output (Vos ₄ ) to (Vos ₁₃ ) corresponding to the output (Vos ₄ ) to (Vos ₁₃ ) of the output of the calculation circuit (22) corresponding to (Vos ₅ ) to (Vos ₁₂ ) Detection circuit (2
Taken into 4). Then, the one having the maximum value among them is output from the peak value detection circuit (24) as (V ₂ ). In FIG. 7, the broken line indicates this (V ₂ ), and therefore V = V ₁ -V ₂ corresponds to the output of the amplifier (26) represented by Vout = E + (V ₁ -V ₂ ) × A. To do.

Next, the operation of the microcomputer (30) shown in FIG. 1 and the operation of the entire circuit by the operation will be described with reference to the flow charts of FIGS.

First, when a start signal is given to the microcomputer (30) by operating a switch (not shown), the microcomputer (30) outputs “1” to the terminal (T ₂₂ ) in step # 1.
Signal to drive the image sensor at high speed. That is, the transfer clock pulse (φ ₁ ) (φ ₂ ) has a period of 8 μ from the Q output (Q ₃ ) of the flip-flop (FF ₂ ).
The second clock pulse is input to the CCD shift register (SR) via the terminals (T ₄ ) (T ₅ ). At this time, since the signal "0" that inhibits the generation of the shift pulse is output from the terminal (T ₁₉ ) and the shift pulse is not generated, the CCD shift register (SR) stores the accumulated charge from the image sensor array (PA). It sequentially discharges its accumulated charge without receiving. (In the step of # 2, the microcomputer (30) sets the timer to the high-speed idle driving time Tx, and in the step of # 3, it is determined whether or not the time of the Tx has elapsed. If judged, the process proceeds to step # 4 and the output of the terminal (T ₂₂ ) is set to “0”. Therefore, CC
The cycle of the transfer clock pulse (φ ₁ ) (φ ₂ ) input to the D shift register (SR) is switched to 128 μsec, and the idle driving at the normal speed starts. At the same time, the microcomputer (30) sets the timer to the idle driving time Ty at the normal speed, and when it determines that the time of Ty has elapsed, it terminates the idle driving and shifts to the next step # 7, Start normal drive. It is to be noted that the generation of the integration clear pulse from the terminal (T ₁₇ ) is also prohibited during the idling drive up to the step of # 6, and the microcomputer (30) has the AD conversion circuit (A
The signal from DC) is not calculated, or the calculation result is not output for driving the photographing lens (TL) or for focus detection display.

The microcomputer (30) is a terminal in step # 7.
A signal of "1" that permits the generation of a shift pulse is output from (T ₁₉ ) and the AND circuit (AN ₁ ) is opened. When the integration clear pulse is output from the terminal (T ₁₇ ) in step # 8, the flip-flop (FF ₀ ) is set and the AND circuit (AN ₂ ) is also opened. At the same time, the integration clear pulse is input to the integration clear gate (ICG) to clear the accumulated charge of each photodiode of the image sensor array (PA), while FET (Q ₁ ) (Q ₄ ) becomes conductive and the capacitor ( C ₁ ) (C ₂ ) is charged to the level of the power supply voltage. This integration clear pulse disappears at time (t ₀ ), which causes the photodiodes of the image sensor array (PA) to start accumulating charges, and depending on the subject brightness detected by the monitor photodetector (PM). Brightness monitor circuit (MC)
The output voltage (Vm) starts to drop as shown in FIG.
At the same time that the integration clear pulse disappears, the microcomputer (30) sets the internal programmable preset counter in step # 9, and this counter starts counting a predetermined time of 100 msec. Next, the microcomputer (30) advances the brightness monitor circuit (M
The output (e) of the brightness judgment circuit (40) that is input to the terminal (T ₂₀ ) to see if the amount of decrease in the output voltage (Vm) of C) has reached 2.8V.
Based on the above, the output (e) is "1".
When it is determined that the case is shown by (l ₅ ), the process proceeds to step # 14, the output of the terminal (T ₁₉ ) is set to “0”, and the shift pulse generation is prohibited. However, when the output (e) becomes "1", as shown in FIG.
A reset pulse continues from the flip-flop (DF ₁ ) to D
A shift pulse is generated from the flip-flop (DF ₂ ), and the reset pulse resets the flip-flop (FF ₀ ) to close the AND circuits (AN ₁ ) (AN ₂ ). The pulse is # 15 described later.
This is a shift pulse that may be newly generated after the step. On the other hand, if the output (e) is "0" at the step of # 10, which is one of the cases shown by (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) in FIG. If judged, the microcomputer
(30) subtracts "1" from the contents of the programmable preset counter described above in step # 11, and determines in step # 12 whether the contents of the counter have become "0". Then, if the content cannot be "0", #
Returning to step 10, it is judged again whether the content of the programmable preset counter becomes "0" in step # 12 after step # 11. Where # 10 and # 1
If the time required for the step cycle of 1 · # 12 is ts,
ts × N = 100 msec. Therefore, if the steps # 10, # 11, and # 12 are repeated N times, the contents of the programmable preset counter become “0”. That is, when 100 msec has elapsed from the setting of this counter in step # 9, the microcomputer (30) outputs the signal "1" from the terminal (T ₁₈ ) in step # 13, and this signal is ANDed. It is input to the D input of the D flip-flop (DF ₁ ) via the circuit (AN ₁ ) (OR ₁ ). Therefore,
A reset pulse is output from the D flip-flop (DF ₁ ), the flip-flop (FF ₀ ) is reset and the AND circuits (AN ₁ ) (AN ₂ ) are closed, while the D flip-flop continues.
A shift pulse is generated from (DF ₂ ).

The shift pulse generated as described above is input to the terminal (T ₂₁ ) of the microcomputer (30) and
Input to shift gate (SG) via (T ₇ ). As a result, the charge accumulated in each photodiode of the image sensor array (PA) is transferred to the corresponding cell of the CCD shift register (SR), and the transfer clock pulse (φ ₁ ) (φ ₂ ) with a cycle of 128 μs is used to sequentially register the charges. The charge accumulated in each cell of (SR) is transferred to the image signal output circuit (VS). Then, the image signal (Vos ₁ ) (Vos ₂ ) ... (Vos (n + 3)) is sequentially output from the output terminal (T ₃ ) of the image signal output circuit (VS), and the amplifier (26) outputs The signal represented by Vout = E + (V ₁ -V ₂ ) A is sequentially output. These signals are sequentially converted into digital signals by the A / D converter (ADC) and input to the microcomputer (30) via the data bus (DB ₁ ).

On the other hand, when the above-mentioned shift pulse is input to the terminal (T ₂₁ ), the microcomputer (30) outputs the terminal (T ₁₇ ) at the step # ₁₅ .
Outputs an integration clear pulse from. Therefore, the accumulated charge of each photodiode of the image sensor array (PA) is cleared, and the charge accumulation of each photodiode is restarted at the same time when the integration clear pulse disappears. of course,
The output of the brightness monitor circuit (MC) also begins to drop at a speed according to the subject brightness detected by the monitor light receiving element (PM) as described above. That is, the second charge accumulation cycle is started, but the microcomputer (30) causes the internal programmable preset counter to count the number of cells of the CCD shift register (SR) at the same time when the integration clear pulse disappears. Set to. This is step # 16. The microcomputer (30) receives a digital signal corresponding to the accumulated charge of each cell from the A / D converter (ADC) and stores it in the internal random access memory (step # 17), and each time it receives it. Then, 1 is subtracted from the contents of the programmable preset counter (step # 18), and it is determined in step # 19 whether or not the contents have become "0". When the contents of the programmable preset counter set in step # 16 become "0", the process proceeds to the next step # 20. In this step, the microcomputer (30) performs, for example, the following calculation to calculate the focus adjustment state of the taking lens (TL), that is, the defocus amount and the defocus direction with respect to the planned focal plane (F). That is, the photodiodes (P ₁ ) (P ₂ ) (P ₃ ) ... (Pn) of the image sensor array (PA)
- ₂₎ (Pn- ₁₎ (from Pn) (P ₁₎ to one of those except for the (P _10),
In FIG. 4, what is included in the area where the first image is formed is the photodiode of the reference portion, and what is included in the area where the second image is formed is the photodiode of the reference portion. Partial photodiodes from one side of the image sensor array (PA) (A ₁ ) (A ₂ ) ...
(Am), (B ₁ ) (B ₂ ) ... (Bm + k- ₁ ), the digital signals from the A / D converter (ADC) corresponding to the charges accumulated in them are respectively ( a ₁ ) (a ₂ ) ・ ・ ・ (am), (b ₁ ) (b ₂ ) ・ ・ ・ (bm + k- ₁ ), Is performed, and the minimum _{one of} C ₁ , C ₂ ... Ck- ₁ , Ck is obtained. For example, if the value of C ₂ is the minimum, the reference portion photodiodes (B ₂ ) (B ₃ ) ... (are included in the image formed on the reference portion photodiodes (A ₁ ) (A ₂ ) ... (Am). The image formed in (Bm) (Bm + ₁ ) is the best match. Therefore, in this case, the photodiode (A
The distance between ₁ ) and (B ₂ ) is the distance between the first and second images described above. Compare this with the predetermined distance between the first and second images when focusing is determined by the focus detection optical system. For example, the defocus amount and the defocus direction of the taking lens at that time can be calculated. Note that the calculation method described here is an example, and in order to determine the defocus amount more accurately, for example, the present applicant has proposed it in Japanese Patent Application No. 58-2622 and Japanese Patent Application No. 58-113936. The same calculation method may be used.

After the above-mentioned calculation in step # 20, the microcomputer (30) outputs the calculation result data for driving the photographing lens and focus detection display, and again outputs the brightness determination circuit (40) (e). Brightness monitor circuit (MC) based on
In step # 21, it is determined whether or not the voltage drop amount of the output (Vm) has reached 2.8 V in the period from step # 16 to # 20. It is assumed that it takes, for example, 50 ms to execute the steps from # 16 to # 20. If the output (e) is “1” and the voltage drop of the output (Vm) has reached 2.8V, then # 2
In step 2, the integration clear pulse is output again from the terminal (T ₁₇ ) to clear the charge accumulated in each photodiode of the image sensor array (PA) during execution of steps # ₁₇ to # 20, and then again. Let them start to accumulate charge. This is done when the judgment is made in step # 21.
This is because if (e) is “1”, the charge accumulation of each photodiode of the image sensor array (PA) may already be saturated. In this case, the microcomputer
In (30), at the same time as the integration clear pulse disappears, the internal programmable preset counter is set to 100 m in step # 22.
It is set so as to count seconds, and then in the step of # 23, a signal of "1" which permits the generation of the shift pulse is output from the terminal (T ₁₉ ). After that, the process returns to step # 10 and the above steps are repeated. On the other hand, the output (e) is “0” in the step of # 21, and the output
If the voltage drop amount of (Vm) has not reached 2.8V, the microcomputer (30) sets the programmable preset counter to count 50 ms in the step of # 24, and then the step of # 24. Move to. At this time, the counter is set to count 50 ms because about 50 ms have already passed since the integration clear pulse output in step # 15 disappeared as described above, and the remaining 50 ms. If the counter is counted, the charge accumulation for a total of 100 msec will be accumulated in the image sensor array.
This is because the (PA) photodiodes are allowed. That is, in this case, the step cycle of # 10, # 11, and # 12 is repeated 50 / ts times at the maximum. Of course, if the pull-programmable preset counter can be used for other purposes without being combined with other purposes, the programmable preset counter should be set to 100 m after the step # 15.
It may be set so as to count seconds, and step # 25 is unnecessary.

The operation of the microcomputer (30) and the operation of the entire circuit by the operation have been described above with reference to FIGS. 10 and 11. However, in this embodiment, after a plurality of idle driving with a cycle of 8 μs, Same period as normal drive before drive 12
The idle drive is performed once for 8 μsec (steps # 4 to # 6). Immediately after the idle driving at the cycle of 128 μs is finished, there is a charge accumulated in each cell of the CCD shift register (SR) for a time corresponding to the position of the cell by its own photosensitivity. The time until it is output in the first normal drive is constant regardless of the cell position. Therefore, the sensitivity of the image sensor array (PA) is not affected by the photosensitivity of each cell of the CCD shift register (SR). ) An image signal that correctly corresponds to the intensity distributions of the first and second images above is obtained.

Further, in this embodiment, a new pulse is generated until the calculation of the defocus amount and the defocus direction in the microcomputer (30) is completed after the transfer of the accumulated charge of the photodiode of the image sensor array (PA) is started by the shift pulse. Generation of shift pulses is prohibited, and charge accumulation is started in each photodiode of the image sensor array (PA) immediately after the generation of the previous shift pulse without waiting for the completion of the calculation. The reason for this is as follows.

In other words, drive the shooting lens based on focus detection,
When performing the focus adjustment, the photographing lens can be focused in a shorter time as the number of focus detection operations performed within a fixed time increases. Therefore, considering the time required for one focus detection operation, the charge accumulation (photocurrent integration) time Ti in the image sensor array (PA) of the CCD and the charge accumulated in the image sensor array are calculated by the CCD shift register ( The time Td required to transfer the image signal to the image signal output circuit (VS) via (SR) and subsequently calculate the signal processing and defocus amount and defocus direction (this is called data processing time for convenience). (Ti + Td), and when the focus detection operation is repeatedly performed continuously, if the next detection operation is performed after the previous detection operation is completed,
The time required to perform the detection operation n times is (Ti + T
d) × n. However, the speed of charge accumulation (photocurrent integration) in the image sensor array (PA) of the CCD depends on the intensity of light incident on it, and if the incident light intensity is low, the speed becomes slow, and charge accumulation for a long time occurs. Must be done. For this reason, the time required for one focus detection operation becomes long, and the number of focus detection operations that can be performed within a fixed time is limited, and it becomes impossible to focus the taking lens in a short time. On the other hand, in the case of CCD, the image sensor array (PA) is used when the accumulated charge is being transferred from the shift register (SR) to the image signal output circuit (VS).
There is no problem even if the charge is stored in. Therefore,
When the integration clear pulse can be generated immediately after the shift pulse is generated, and the image sensor array (PA) accumulates new charges during the above-described data processing time Td, the incident light intensity is low. However, the time required for one focus detection operation is shortened, the number of focus detection operations performed within a fixed time is increased, and the taking lens can be focused in a short time. However, on the other hand, if new accumulated charges are transferred to the CCD shift register (SR) while the accumulated charges of the CCD shift register (SR) are being transferred to the image signal output circuit (VS) (this is due to the structure of the CCD). The above is possible), CCD
Old and new accumulated charges are mixed in the shift register (SR), and an erroneous image signal is output. Also, the microcomputer (30) cannot hold a new signal because it must hold the data in the random access memory during the calculation in step # 26. Therefore, the shift pulse is prohibited during the above-mentioned data processing time Td.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. For example, as a self-scanning image sensor, not only CCD but also BBD (Bucket Brigade Device), CID (Charge Injecti
on Device), a MOS (Metal Oxide Semiconductor) type image sensor, etc. can be used. Further, the focus detection method is not limited to the one using the focus detection optical system shown in FIG. 4, but is disclosed in, for example, JP-A-54-159259 and JP-A-57-7050.
No. 4, JP-A-57-45510, etc.,
Both the defocus amount and the defocus direction are calculated as the focus adjustment state of the taking lens by placing the lenslet on the planned focal plane of the taking lens or a plane conjugate with it and placing the self-scanning image sensor behind it. Method, or JP-A-55-155308 and JP-A-5-155308.
As disclosed in 7-72110, JP-A-57-88418, etc., a self-scanning image sensor is arranged on the planned focal plane of the photographing lens or on a plane conjugate therewith and before and after it, respectively. The present invention is also applicable to a method of detecting only the defocus direction as the focus adjustment state of the photographing lens.

Further, in the above-described embodiment, the case where the CCD transfers the accumulated charges from the CCD shift register which is the transfer unit to the image signal processing circuit by the two sets of transfer clock pulses φ ₁ and φ _{2 has} been described. The present invention can be applied to the case where the charge transfer is performed by the clock pulse.

Furthermore, in the above embodiment, the generation of the integral clear pulse is prohibited during the idling of the image sensor, but this is not always necessary, and it may be generated appropriately.
In addition, as a condition of idle driving, the microcomputer (30) does not calculate the signal from the A / D converter (ADC) during that period, or even if the calculation is performed, the calculation result is driven by the photographing lens (TL) or Although the example of not outputting for focus detection display was described, during that period, the microcomputer (30)
The signal from the D / D converter (ADC) may not be accepted, or the gate means opened for the period by the signal from the microcomputer (30) may be provided at the output part of the circuit (22). Good.

Effects As described above, according to the focus detection device of the present invention,
As in the case where the image sensor is driven at high speed in the air and then immediately after normal drive, the charge accumulation due to its own photosensitivity in the charge transfer section of the image sensor causes a change in the image signal corresponding to the intensity distribution of the subject image. It is possible to avoid adversely affecting the formation even in the first normal driving.

[Brief description of drawings]

1 is an overall circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing details of the photoelectric conversion block (1) in FIG. 1, and FIG. 3 is a photodiode constituting each pixel of the image sensor array. And an equivalent circuit diagram of the integration clear gate, FIG. 4 is a diagram showing the focus detecting optical system in the above-mentioned embodiment, FIG. 5 is a diagram showing a temporal change of the output of the monitor circuit, and FIG.
Circuit diagrams showing specific examples of the brightness determination circuit (40) and the block (20) in the figure, FIGS. 7, 8, and 9 are diagrams showing output waveforms at respective parts of the circuit of FIG. 1, and FIG. And FIG. 11 is a flow chart showing the operation of the microcomputer in the above embodiment. (PA) (ICG) (SG) (SR) ... Self-scanning image sensor, (S
R) ... shift register (accumulated charge transfer section), (VS) ... image signal output circuit, (ADC) ... A / D converter, (φ ₁ ) (φ ₂ ) ...
Transfer clock pulse, (10) ... Transfer clock pulse generation circuit.

Claims (1)

[Claims] 1. A charge storage type comprising a plurality of charge storage units for storing charges according to the intensity of incident light and a charge transfer unit for receiving and storing and discharging the charges stored in the charge storage units. A sensor; a clock pulse output means for outputting a clock pulse of a predetermined cycle; and an ejecting means for ejecting charges accumulated in the plurality of charge accumulating portions by the clock pulse in order through the charge transfer portion. An image sensor, comprising: a second clock pulse output means for outputting a high-speed clock pulse having a cycle shorter than the clock pulse; a start signal output means for outputting a start signal for starting the charge accumulation; and the start signal for output. Then, the charge remaining in the charge transfer section is discharged by the high-speed clock pulse,
An image sensor characterized by further comprising: an initializing means for discharging the electric charge remaining in the electric charge transfer section by a clock pulse of the predetermined cycle, and starting the electric charge accumulation after the operation of the initializing means is completed. .