JPH0775402B2 - Image processing device using self-scanning image sensor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which processes an image signal of a self-scanning image sensor having a charge storage section and a transfer section for charge storage, and which is useful for a focus detection apparatus of a camera, for example.

[0002]

2. Description of the Related Art Conventionally, a focus detecting device for a camera as described above is a CCD (Charge Coupled De).
It is known that the image sensor array is used as a self-scanning image sensor, and when a positive pulse called an integration clear pulse is input to the CCD, each photodiode constituting the image sensor array of the CCD once reaches the power supply voltage level. The battery is charged, and then the integration clear pulse disappears to start discharging (hereinafter, this is considered to be accumulation of negative charges and referred to as charge accumulation). After that, when a positive pulse called a shift pulse is input to the CCD, the charge accumulated in each photodiode between the disappearance of the integration clear pulse and the input of the shift pulse is transferred to the corresponding cell of the CCD shift register, Each time a transfer clock pulse is input to this CCD shift register, the accumulated charges are sequentially transferred from there to the image signal output circuit. The image signal output circuit sequentially outputs the accumulated charges transferred from the CCD shift register as a voltage signal, and the voltage signals output one after another are the light intensity distribution on the image sensor array, that is, the additional voltage formed thereon. The intensity distribution of The voltage signal output from the image signal output circuit is converted into a digital signal by the A / D converter and then processed and calculated by, for example, a microcomputer according to a predetermined program, and as a result, the focus adjustment state of the photographing lens is determined. .

[0003]

By the way, conventionally, the charge accumulation of each photodiode is configured to be started after the end of the focus detection operation described above, that is, after the end of the signal processing operation by the microcomputer. Was normal. That is, the next integral clear pulse was generated when the processing calculation was completed. However, the charge storage speed of each photodiode changes depending on the subject brightness, and when the subject brightness becomes low, it is necessary to continue charge storage for a relatively long time, and the timing of generation of the shift pulse is controlled according to the subject brightness. Therefore, when the subject brightness is low, the charge accumulation time becomes long, the time required for one focus detection operation also becomes long, and the number of focus detection operations that can be performed within a fixed time decreases.

Now, when focus detection is performed continuously and the focus is adjusted by driving the taking lens based on the focus detection results of each time, the shorter the number of focus detection operations performed within a certain time, the shorter the time. Since the photographic lens can be focused with, the charge accumulation is started in each photodiode at the time when the previous focus detection operation ends in this way, the photographic lens is focused when the subject brightness is low. It will take some time and miss the opportunity to shoot.

Therefore, the present invention is to provide an image processing apparatus that shortens the time required for one focus detection process and shortens the time until the photographic lens comes into focus even if the charge accumulation time is long. .

[0006]

An image processing apparatus according to the present invention uses an image signal output circuit based on accumulated charges sequentially transferred from a self-scanning image sensor having a charge accumulation unit and a transfer unit for transferring accumulated charges. In an image processing apparatus that obtains an image signal and performs focus detection processing by a processing circuit, start signal output means for outputting a start signal for starting the charge storage operation of the charge storage section, and charge stored in the charge storage section. Shift pulse generating means for generating a shift pulse for transferring the charge to the transfer section, and transfer clock pulse generating means for generating a transfer clock pulse for sequentially transferring the charges transferred to the transfer section to the image signal output circuit. , By restarting the operation of the start signal output means before the end of the focus detection processing by the processing circuit,
Control for controlling so that the accumulated charge is read out by the shift pulse generating means and the transfer pulse generating means, and the restarted charge accumulating operation in the image accumulating section is performed in parallel during the focus detection processing period by the processing circuit. Means and are provided.

[0007]

The accumulated charges are sequentially output to the image signal output circuit by the shift pulse and the transfer clock pulse, and the focus detection process is performed by the processing circuit. In parallel with this processing, the restart of the start signal output means is controlled so that the next charge storage in the charge storage section of the image sensor is performed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS.

First, in FIG. 1 showing the entire circuit of this embodiment, (1) is a self-scanning image sensor such as a CCD, an image signal output circuit, a light receiving element for brightness monitor, as will be described later. It is a photoelectric conversion block including a brightness monitor circuit and a reference signal generation circuit.
(10) is a transfer block pulse generation block, (20)
Is a circuit block that forms a digital signal which is the basis for the focus adjustment state determination of the taking lens based on the signal from the photoelectric conversion block (1). Reference numeral (30) is a microcomputer for discriminating the focus adjustment state of the photographing lens based on the digital signal from the circuit block (20) and controlling each circuit block.

Reference numeral (40) controls the amplification factor of the amplifier in the circuit block (20) on the basis of the output of the brightness monitor circuit in the photoelectric conversion block (1), while controlling the amplification factor in the photoelectric conversion block (1). It is a brightness discrimination circuit that controls the charge accumulation time (photocurrent integration time) of the self-scanning image sensor. (AN ₁ ) and (AN ₂ ) are AND circuits that form gate means together with an OR circuit (OR ₁ ), and (DF ₁ ) is a flip-flop (FF ₀ ) (FF ₁ ) to (F ₁ ) described later.
The D flip-flop that generates a reset pulse that resets F ₆ ), and the (DF ₂ ) is a D flip-flop that generates a shift pulse that transfers the charge accumulated in the charge accumulating unit to the transfer unit in the image sensor. (CL
₁ ) is a clock circuit for generating a reference clock pulse,
(FF ₀ ) is an RS flip-flop.

FIG. 2 shows the above-mentioned photoelectric conversion block (1), which includes photodiode rows (P ₁ ) (P ₂ ) (P).
₃ ) ... (P _n-2 ) (P _n-1 ) (P _n ) The image sensor array (PA), the integration clear gate (ICG), the shift gate (SG), and the CCD shift register (SR) are used to perform the above operations. A self-scanning image sensor is configured. Here, the CCD shift register (S
The number of cells of R) is 3 more than the number of photodiodes (the number of pixels) of the image sensor array (PA) which is the charge storage unit, and the cells (R ₁ ) (R ₂ ) (R ₃ ) are used for the below-described blank feeding. And each photodiode array (P ₁ ) (P ₂ ) (P ₃ ) ... (P _n-2 ) of the image sensor array (PA)
The accumulated charge of (P _n-1 ) (P _n ) is the cell (R ₄ ) (R ₅ ) (R
₆ ) ... (R _{n + 1} ) (R _{n + 2} ) (R _{n + 3} ).

As shown in FIG. 3, each photodiode has an integral clear gate (ICG) with respect to a power source (+ V).
FET and a pair of diodes (D ₁ ) (D ₂ ) connected in parallel with each other via a switch (S) corresponding to
(Q _{1 0} ) and one diode (D ₁ ) is installed so as to receive light. FET _{(Q 1 0)} keeps the voltage across the diode _{(D 1)} substantially constant, which was provided to negligible capacitance of the diode _{(D 1),}
Its gate is grounded. Now, when the switch (S) is closed, charges are accumulated between the anode and cathode of the diode (D ₂ ), and the cathode voltage becomes equal to the power supply voltage. Then, when the switch (S) is opened next, the diode (D ₂ ) is driven by the photocurrent of the diode (D ₁ ) to F
It discharges through ET (D _{1 0} ) and its cathode voltage drops over time. That is, this may be considered that negative charges are accumulated in the anode of the diode (D ₂ ) at a speed according to the intensity of the light incident on the diode (D ₁ ), and therefore each photodiode is The description will be made assuming that the charges are accumulated at a corresponding speed.

The switch (S) is actually composed of a semiconductor analog switch which is rendered conductive by an integral clear pulse input to an integral clear gate (ICG) and becomes non-conductive when the pulse disappears. Shift gate (SG)
Is a photodiode (P ₁ ) (P ₂ ) (P ₃ ) ...
The accumulated charges of (P _n-2 ) (P _n-1 ) (P _n ) receive a shift pulse to be described later and the cells (R ₄ ) (R ₅ ) (R ₆ ) ... (R) of the CCD shift register (SR) _{n + 1} ) (R _{n + 2} ) (R _{n + 3} )
Transfer in parallel to. Photodiode (P ₁ )
The charge accumulation of (P ₂ ) (P ₃ ) ... (P _n-2 ) (P _n-1 ) (P _n ) is terminated by the input of the shift pulse to the shift gate (SG). In addition, the CCD shift register (SR) sequentially accumulates charge for one cell at the trailing edge of the transfer clock pulse (φ ₁ ) before the transfer clock pulse (φ ₁ ) (φ ₂ ) described later is input. Output to the image signal output circuit. Note that a predetermined number (10) of photodiodes (P ₁ ) (P ₂ ) are counted from one end of the image sensor array (PA).
(P _{1 0} ) is covered with an aluminum film and is used for dark output correction as described later. (T ₈ ) of FIG.
(T ₉ ) is the above image sensor, circuit (MC) (R
S) (VS) is a power supply terminal for supplying power (+ V).

By the way, the image sensor array (P
The position of A) in the camera depends on
It depends on the focus detection method. FIG. 4 shows an example of a focus detection optical system to which the present invention can be applied. (TL) is a taking lens, (CL) is a condenser lens, and (L ₁ )
(L ₂ ) is a pair of re-imaging lenses symmetrically arranged with respect to the main optical axis (1) of the imaging lens (TL), (M) is a mask, and (F) is a taking lens equivalent to the film surface of the camera ( TL) is a planned image forming plane.

According to this optical system, the taking lens (TL)
When a subject image is formed on or before and after the predetermined image plane (F) by the re-imaging lens (L ₁ ) (L ₂ ), the subject image is first formed on the image sensor array (PA). , The second image is re-formed, but the image sensor array (P
In A), the distance between the first and second images is the taking lens (TL).
Of the focus adjustment state, that is, the state of deviation of the subject image formed thereby with respect to the planned image formation plane (F). Therefore, if the distance between the first and second images is detected based on the output of each pixel of the image sensor array (PA), the defocus amount and the defocus method indicating the focus adjustment state of the taking lens (TL) can be determined. The output processing method required for this will be described later. In FIG. 4, the image sensor array (PA) includes a condenser lens (CL) and a pair of re-imaging lenses (L ₁ ) (L).
₂ ) is arranged at a position conjugate with the planned image formation plane (F) or in the vicinity thereof.

Referring again to FIG. 2, (MP) is a photodiode which is a light receiving element for brightness monitoring, (MC) is a brightness monitoring circuit, (RS) is a reference signal generating circuit, and (V
S) is an image signal output circuit. Brightness monitor circuit (M
C) is composed of FETs (Q ₁ ) (Q ₂ ) (Q ₃ ) and a capacitor (C ₁ ). The gate of the FET (Q ₁ ) is connected to the integral clear gate (ICG) of the image sensor, and the FET (Q ₁ ) is turned on by the integral clear pulse passing through the integral clear gate (ICG), whereby the capacitor (C ₁ ) is turned on. It is charged to the level of the power supply voltage (+ V). The connection point (J ₁ ) of the FET (Q ₁ ) and the capacitor (C ₁ ) is connected to the anode of the photodiode (MP) via the FET (Q _{1 2} ), while the FET (Q ₂ ) is connected.
Is connected to the gate. The gate of the FET (Q _{1 2} ) is grounded, and the FET (Q _{1 2} ) is provided so that the voltage across the photodiode (MP) can be kept substantially constant and the influence of its capacitance can be ignored. FET (Q ₂ )
(Q ₃ ) are connected in series to the power source, form a buffer with low output impedance and high input impedance, and since FET (Q ₃ ) is used as a source follower, FET (Q ₂ ) From the output terminal (T ₁ ) drawn from the connection point of (Q ₃ ), the connection point (J
_The voltage (Vm) corresponding to the potential of ₁ ) is output. When the integration clear pulse disappears, the FET (Q ₁ ) becomes non-conductive and the capacitor (C ₁ ) becomes the photodiode (M 1
P) is discharged by the photocurrent, and accordingly, the terminal (T
The output voltage of ₁ ) drops. FIG. 5 shows the change over time in the output voltage of this terminal (T ₁ ), which is (l ₁ ).
(L ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) indicates that the speed of the voltage drop changes depending on the brightness. The trailing edge indicated by (RN) represents the noise induced by the integration clear pulse.

The reference voltage generator (RS) is a FET (Q
₄ ) (Q ₅ ) (Q ₆ ) and a capacitor (C ₂ ), which are the above-mentioned FETs (Q ₁ ) (Q ₂ ) (Q ₃ ).
And the capacitor (C ₁ ) have the same characteristics,
The circuit connection is also FE in the brightness monitor circuit (MC).
This is the same as the circuit connection of T (Q ₁ ) (Q ₂ ) (Q ₃ ) and capacitor (C ₁ ). However, the gate of the FET (Q ₅ ) is only connected to the connection point (J ₂ ) of the FET (Q ₄ ) and the capacitor (C ₂ ).
Like (Q ₂ ) and (Q ₃ ), the output impedance is low,
FE that constitutes a buffer with high input impedance
An output terminal (T) drawn from the connection point of T (Q ₅ ) (Q ₆ )
_The voltage signal output from ( ₂ ) is kept constant as shown in FIG. 5 even after the integration clear pulse disappears. That is, immediately after the integration clear pulse disappears (t ₀ ), the connection point (J
₁ ) (J ₂ ) has a potential of FET (Q ₁ ) as described above.
(Q ₂ ) (Q ₃ ) and capacitor (C ₁ ) and FET (Q
₄ ) (Q ₅ ) (Q ₆ ) and the capacitor (C ₂ ) have the same characteristics, so they are equal to each other, so that the terminal (T
₂ ) is a reference voltage (Vre) for obtaining the amount of drop of the voltage signal output from the terminal (T ₁ ).
It can be used as f).

The image signal output circuit (VS) is an FET
It is composed of (Q ₇ ) (Q ₈ ) (Q ₉ ) and a capacitor (C ₃ ), and preferably FET (Q ₁ ) (Q ₂ ).
(Q ₃ ) and the capacitor (C ₁ ) having the same characteristics are used. However, in circuit connection, FET (Q ₇ )
The gate is adapted to transfer clock pulse (phi ₁₎ is applied, Moreover, FET _{(Q 7)} and the connection point of the capacitor _{(C 3) (J 3)} is and the gate of the FET _{(Q 8)} It is connected to the transfer terminal of the CCD shift register (SR) of the image sensor.

Therefore, every time one transfer pulse (φ ₁ ) is input, the FET (Q ₇ ) becomes conductive and the capacitor (C
₃ ) is charged to the level of the power supply voltage (+ V) and the image signal output circuit (VS) is reset, but depending on the accumulated charge of the CCD shift register (SR) transferred by each transfer pulse (φ ₁ ). And repeatedly discharge. After all, from the output terminal (T ₃ ) drawn out from the connection point of the FETs (Q ₈ ) and (Q ₉ ) forming the buffer of low output impedance and high input impedance, each photodiode which is a pixel of the image sensor is connected. The outputs corresponding to the accumulated charges of are sequentially output as a voltage signal (Vos), and they collectively form an image signal.

The above circuit (MC) (RS) (V
Although (C ₁ ) (C ₂ ) (C ₃ ) in S) is described as a capacitor for convenience of description, the PN of the diode is used.
They can be replaced by junctions, and when these circuits are integrated, they are made as diodes. The photodiode (MP), which is a light receiving element for monitoring, is arranged near the image sensor array (PA) so as to receive a part of the light that has passed through the taking lens.

Next, referring again to FIG. 1, an example of the circuit configuration of the transfer clock pulse generation block (10) for generating the transfer clock pulses (φ ₁ ) (φ ₂ ) will be described. (FF
₁ ) (FF ₂ ) ... (FF ₆ ) are flip-flop circuits that form a frequency dividing circuit, and the first-stage flip-flop (F
The clock pulse (cycle 2 μsec) from the clock circuit (CL ₁ ) is input to the T input of F ₁ ). Flip-flop _{(FF 3) (FF 4)} (FF 5) Q output (FF ₆₎ are respectively input in an OR circuit (OR _2), the output of the OR circuit (OR ₂₎ AND circuits (AN ₄ ) is input to one input. The other input of the AND circuit (AN ₄ ) is connected to the terminal (T _{2 2} ) of the microcomputer (30) via the inverter (IN ₁ ),
When the terminal (T _{2 2} ) outputs a signal of “0”, the AND circuit (AN ₄ ) outputs “1” of the OR circuit (OR ₂ ).
Signal is output. On the other hand, the AND circuit (AN ₅ ) has one input connected to the clock circuit (CL ₂ ) and the other input connected to the above-mentioned terminal (T _{2 2} ), and thus the above-mentioned terminal (T _{2 2} ). Outputs a signal of "1", the clock pulse from the clock circuit (CL ₂ ) is output. Here, the cycle of the clock pulse output from the clock circuit (CL ₂ ) is several tens of times the cycle of the output (Q ₆ ) of the flip-flop FF6 obtained by dividing the frequency of the clock pulse output from the clock circuit (CL ₁ ). It is set to be short. The OR circuit (OR ₃ ) is an AND circuit (AN ₄ )
"1" when any output signal of (AN ₅ ) is "1"
Is output to the CCD shift register (SR) in the photoelectric conversion block (1) as a transfer clock pulse (φ ₂ ). Further, the OR circuit (OR ₃ ) has an inverter (I
N ₂ ) is connected, and the inverter (IN ₂ ) uses a signal having a phase opposite to that of (φ ₂ ) as a transfer clock pulse (φ ₁ ) and a CCD shift register (SR) in the photoelectric conversion block (1) and Output to the image signal output circuit (VS) (see FIG. 2). The microcomputer (3
0 signal "1" from the terminal (T 2 ₂₎ of) is a signal for causing initializing operation to the image sensor.

FIG. 6 shows an example of the brightness determination circuit (40) and the circuit block (20). In this figure (T _{1 0} )
(T _{1 1} ) and (T _{1 2} ) are the terminals (T ₁ ) in FIG.
(T ₂ ) (T ₃ ) is a terminal connected to the terminal (T _1
3 ) (T _{1 5} ) and (T _{1 6} ) are input with a latch pulse, a sample designating pulse, and a sample designating reset pulse from the microcomputer (30) via the data bus (DB ₁ ) as described later. Further, the terminal _{(T 1 4)} is connected to one input of the AND circuit FIG 1 (AN _2).

First, the brightness determination circuit (40) will be described. This circuit is for stepwise determining the extent of the drop of the output voltage (Vm) of the brightness monitor circuit (MC) after the disappearance of the integrated clear pulse. Comparator (AC ₁ ) (AC ₂ )
(AC ₃ ) (AC ₄ ) are provided. The inverting inputs of these comparators are coupled to the terminal (T _{1 0} ) via the buffer (B1). On the other hand, these comparators (AC ₁ )
The non-inverting inputs of (AC ₂ ) (AC ₃ ) (AC ₄ ) are connected to the connection point (J ₄ ) of the resistor (R ₁ ) and the constant current source (I ₁ ), the resistor (R ₂ ) and the constant current source (I ₁ ). ₂ ) connection point (J ₅ ), resistance (R ₃ ) and constant current (I ₃ ) connection point (J ₆ ), resistance (R ₃ ).
₄ ) and the constant current source (I ₄ ) are connected to a connection point (J ₇ ) respectively, and the resistors (R ₁ ) (R ₂ ) (R ₃ ) (R ₄ ) are connected via a buffer (B ₂ ). It is connected to the terminal (T _{1 1} ).

With such a circuit connection, the connection point (J
₄ ) (J ₅ ) (J ₆ ) (J ₇ ) the voltage (Vr) of the above-mentioned reference voltage generation circuit (RS) applied to the terminal (T _{1 1} ).
ef) and resistances (R ₁ ) (R ₂ ) (R ₃ ) (R ₄ ), respectively.
The voltage generated by subtracting the voltage drop at
_{1) (R 2) (R} 3) ( the resistance value of _{R 4)} and a constant current source _{(I 1) (I 2)} (I 3) ( by selecting the current value of _{I 4),} the terminal _{(T 1 0} ), The comparator (AC ₁ ) (AC ₂ ) (AC ₃ ) (AC
The output of ₄ ) is sequentially inverted from "0" to "1". (DF
₃ ) (DF ₄ ) and (DF ₅ ) each have a D input with a comparator (AC
₁ ) (AC ₂ ) (AC ₃ ) connected to the outputs of the D flip-flops, and these CP inputs have latch pulses from the microcomputer (30) of FIG.
If a shift pulse occurs after a predetermined time (100 msec) from the falling edge of the integration clear pulse or before the predetermined time elapses via _{1 3} ), the shift pulse is input in synchronization therewith. When the latch pulse is input, the D flip-flops (DF ₃ ) (DF ₄ ) (D
F ₅ ) is the immediately preceding comparator (AC ₁ ) (AC ₂ ) (A
The output of C ₃ ) is output to the Q output, and the inverted Q output outputs the inverted output.

(AN ₆ ) is an AND circuit in which one input is connected to the Q output of the D flip-flop (DF ₃ ) and the other input is connected to the Q output of the D flip-flop (DF 4), and (AN ₇ ) is One input is a D flip-flop (D
F ₄ ) is an AND circuit having the output of the inverted Q and the other input connected to the inverted Q output of the D flip-flop (DF ₅ ), and the output (b) of the AND circuit (AN ₆ ) (AN ₇ ).
(C), the inverted Q output (a) of the D flip-flop (DF ₃ ), the Q output (d) of (DF ₅ ), and the comparator (A
The output (e) of C ₄ ) becomes the output of the brightness determination circuit (40). That is, their outputs are the light receiving elements for monitoring (P
It becomes a signal indicating the brightness level detected in M).

This will be described in more detail with reference to FIG. 5. In FIG. 5, (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) is the above-mentioned predetermined value from the instant (t ₀ ) when the integration clear pulse disappears. If the voltage drop that occurs by the time (t ₃ ) after the lapse of time (100 msec) is less than 0.35 V, 0.35 V to 0.7 V
Less than 0.7V to less than 1.4V, 1.4
Brightness monitor circuit (MC) from V to less than 2.8V
Of the output voltage of ( ₁₀ ) and (I ₅ ) is the predetermined time (100) from the time (t ₀ ) when the integration clear pulse disappears.
It shows a change in the output voltage of the monitor circuit (MC) when a voltage drop of 2.8 V occurs at a time point (t ₂ ) before elapse of m seconds). (L ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ )
As described above, which of the voltage drops is caused by the magnitude of the photocurrent of the monitor light receiving element (DM), and the output voltage change of the brightness monitor circuit (MC) is (l ₁ ) (l
₂ ) The case of (l ₃ ) (l ₄ ) is low brightness, and the case of (l ₅ ) is high brightness.

Now, terminals (J ₄ ) (J ₅ ) (J ₆ )
The voltage of (J ₇ ) is greater than the output voltage (Vref) of the reference voltage generation circuit (RS) input to the terminal (T _{1 1} ), respectively.
The above resistances (R ₁ ) (R ₂ ) (R ₃ ) are set so that they are lowered by 0.35V, 0.7V, 1.4V and 2.8V, respectively.
(R ₄ ) resistance value and constant current source (I ₁ ) (I ₂ )
When the current value of (I ₃ ) (I ₄ ) is set, (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l
₅ ) corresponding to the D flip-flop (DF ₃ ) (D
F ₄ ) (DF ₅ ) Q output, inverted Q output, and brightness monitor circuit (MC) output (a) (b) (c) (d)
(E) is as shown in Table 1 below.

[0028]

[Table 1]

In the case of (l ₅ ), the comparator (AC ₄ )
The output of (d) are set to "0" to "1" in the integration clear pulse disappearance time _{(t 0)} from a predetermined time point before (100m seconds) has elapsed _{(t 2).} The remaining circuits of FIG. 6 form the circuit block (20) of FIG. (22) is the output voltage (Vos) of the image signal output circuit (VS) input from the terminal (T _{1 2} ) via the buffer (B ₃ ) and the terminal (T _{1 1} ) via the buffer (B ₂ ). Is a subtraction circuit that generates an output (V ₁ ) corresponding to the difference from the output voltage (Vref) of the reference signal generation circuit (RS) that is input from (24) is an aluminum film in the image sensor array (PA). It covered predetermined number (10) minutes of the photodiode _{(P 2)} from the peak value across the diode _(P 2) the image signal corresponding to the accumulated charge but excluding _{(P 9)} of the _{(P 9)} ( V
₂ ) A peak value detection circuit that detects (the lowest level pixel signal), latches them, and outputs them.
First and second, not covered with aluminum coating
A signal V ₂ for so-called dark output correction is formed with respect to the pixel signal corresponding to the accumulated charge of the photodiode in the image sensor array (PA) receiving the image. That is, in the microcomputer (30), accumulated charges are sequentially accumulated from the CCD shift register (SR) by the transfer clock pulse (φ ₁ ) (φ ₂ ) in the image signal output circuit (VS).
In the case of being transferred to the cell (R ₅ ), the sample designation pulse is output to the terminal (T _{1 5} ) via the data bus (DB ₁ ) at the same time when the transfer of the accumulated charge of the cell (R ₅ ) is started, and then the cell (R _{1 2} )
Simultaneously with the completion of the transfer of the accumulated charge of, the sample designating reset pulse is output to the terminal (T _{1 6} ) via the data bus (DB ₁ ). Accordingly, incorporation of the corresponding image signal charges accumulated in the peak value detection circuit (24) is accumulated charge of the cell from _{(R 5) (R 1 2),} the photodiode _{(P 2)} in other words _{(P 9),} The peak value of them will be detected.

(26) is an amplifier for differentially amplifying the output signals (V ₁ ) (V ₂ ) of the circuits (22) and (24),
The amplification factor is the output (a) of the brightness determination circuit (40) described above.
(B) (c) (d) is an amplifier configured to be controlled. In this amplifier, (OP) is an operational amplifier, and its input terminals (f) and (g) are connected to circuits (22) and (24) through input resistors (R ₅ ) and (R ₆ ), respectively. . (R ₇ ) to (R _{1 4} ) are resistors provided for setting the amplification factor of the operational amplifier (OP), and are (R ₅ ) (R ₆ ) (R ₇ ) (R ₈ ) (R _{1 1} ) (R
_When the resistance value of _{1 2} ) is r, (R ₉ ) (R _{1 3} ) has a resistance value of 2r and (R _{1 0} ) (R _{1 4} ) has a resistance value of 4r. (AS ₁ ) to (AS ₈ ) are analog switches, of which (AS ₁ ) to (AS ₄ ) are resistors (R ₇ ) to (R ₇ ) depending on the outputs (a) (b) (c) (d). R _{1 0} ) is selectively enabled to set the feedback resistance value of the operational amplification (OP), while (AS ₅ ) to (A ₅ )
S ₈ ) selectively enables the resistors (R _{1 1} ) to (R _{1 4} ) according to the outputs (a), (b), (c), and (d) to set the bias resistance value of the amplifier (OP). To do. That is, the states of the analog switches and the activated resistances when the voltage drops of (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) (l ₅ ) described above occur are as shown in Table 2 below. Becomes

[0031]

[Table 2]

In the above table, A is the amplification factor of the operational amplifier (OP), and the output voltage of this amplifier (OP) is Vout =
It is represented by E + (V ₂ −V ₁ ) × A, which is input to the A / D converter (ADC). However, E is the voltage of the low voltage source (E), and is set appropriately according to the input level range of the A / D converter (ADC). Then, the data bus (D to the terminal _{(T 2 2)} of each output is a microcomputer of FIG. 1 of each pixel signal A / D converter corresponding to (ADC)
Incorporated via the B _1), by digital calculation based on a predetermined program, the focus adjustment state of the photographic lens is detected. As described above, the amplifier (26) in FIG. 1 changes the amplification factor according to the output of the brightness determination circuit (50), and
Since a signal suitable for the processed signal in the / D converter (ADC) is output, the focus state of the taking lens can be adjusted in a wide luminance range.

[0033] Referring to FIG 1 again, the terminal of the microcomputer _{(30) (T 1 7)} is an output terminal of the integrating clearing Paris. In addition, a microcomputer (3
0) of the terminal (T 1 ₉₎ is output signal when "1" to permit the generation of shift pulses, accumulated charges from the image sensor array (PA) as described below to the CCD shift register (SR) During transfer of the signal, a signal "0" for inhibiting the generation of shift pulse is output. Further from the terminal (T 1 ₈₎ of the microcomputer (30), the predetermined time described above from the disappearance time (t ₀₎ of the accumulation clear pulse has passed, or if the shift pulse occurs before the elapse of the predetermined time that A signal of "1" is output in response to the generation of the shift pulse. This signal becomes a latch pulse for the brightness determination circuit (40). Terminal _{(T 1} 7)
The integration clear pulse output from the terminal is input to the integration clear gate (ICG) of the image sensor in the photoelectric conversion block (1) via the terminal (T ₆ ), while the flip-flop (FF ₀ ) is set and its Q Output is "1"
Then, the AND circuit (AN ₁ ) is opened. Also, with the flip-flop (FF ₀ ) set, the terminal (T ₁
When the signal of permitting the generation of shift pulse "1" is outputted from the _9), an AND circuit (AN ₂₎ is also opened.

From the output terminal (T _{1 4} ) of the brightness determination circuit (40), only when the subject brightness is high as shown by (l ₅ ) in FIG. 5, the disappearance time (t ₀ of the integration clear pulse) ), A signal (e) of "1" is output at a time point (t ₂ ) before a predetermined time (100 msec) has elapsed. In contrast, in FIG. _{5 (l 1) (l 2} ) (l 3) as in the case shown by _{(l 4),} when the subject brightness is low, the terminal of the microcomputer _{(30) (T 1} 8) Output becomes "1" at the time of (t ₃ ) and the brightness determination circuit (40)
The output (e) of the output terminal (T _{1 5} ) of is kept at "0". Therefore, when the subject brightness is high, the output of the AND circuit (AN ₂ ) becomes “1” at the time point (t ₂ ), and when the subject brightness is low, the AND circuit (A ₂ ) outputs at the time point (t ₃ ).
The output of N ₁ ) becomes “1”, and one of the outputs of “1” is input to the D input of the D flip-flop (DF ₁ ) via the OR circuit (OR ₁ ). A clock circuit (C
Since the reference clock pulse (cycle 2 μs) from L ₁ ) is input, as shown in FIG. 6, D is input at the trailing edge of the reference clock pulse immediately after the “1” signal is input to the D input. The Q output of the flip-flop (DF ₁ ) becomes “1”, the flip-flop (FF ₀ ) is reset, the opened AND circuit (AN ₁ ) or (AN ₂ ) is closed, and the transfer clock pulse generation block ( Flip-flops (FF ₁ ) to (FF ₆ ) in 10) are reset, and their Q outputs (Q ₁ ) to (Q ₆ ) are all “0”. The AND circuit (AN ₁ ) or (A
When N ₂ ) is closed in this way, the Q output of the D flip-flop (DF ₁ ) returns to “0” at the next falling edge of the reference clock pulse, and eventually the Q output has a positive width of 2 μsec. The pulse has been output. This positive pulse is the reset pulse. On the other hand, D flip-flop (DF
₂ ), the Q output of the D flip-flop (DF ₁ ) is “1”
Just after the reference clock pulse from the clock circuit (CL ₁ ) has fallen, the Q output becomes “1”, and the Q output of the D flip-flop (DF ₁ ) returns to “0”. Q output is "0" at the falling edge of the reference pulse of the circuit
Return to. Therefore, the Q of the D flip-flop (DF ₂ )
The output rises in a cycle with the falling edge of the reset pulse.
A positive pulse having a time width of μsec occurs, which is a shift pulse. This shift pulse is input to the terminal (T _{2 1} ) of the microcomputer (30) and also to the shift gate (SG) of the image sensor in the photoelectric conversion block (1) via the terminal (T ₇ ).

The above is a description of the entire circuit configuration of FIG. 1 and the circuit blocks constituting it. Before explaining the overall operation, referring to FIGS. 7 and 8, signals in each part are described. Will be explained.

FIG. 7 shows the Q of the D flip-flop (DF ₁ ).
The outputs of the flip-flops (FF ₁ ) to (FF ₆ ) immediately after being reset by the reset pulse generated in the output, the transfer pulse (φ ₁ ) and the D flip-flop (DF
The relationship of the shift pulse which is the Q output of ₂ ) is shown.
As described above, the flip-flops (FF ₁ ) to (FF ₆ ) are reset at the rising edge of the reset pulse, and their Q outputs (Q ₁ ) to (Q ₆ ) are all “0”. As a result, the output of the OR circuit (OR ₂ ) becomes “0”, so that the transfer clock pulse (φ ₂ ) falls to “0” and conversely the transfer clock pulse (φ ₁ ) rises to “1”. . Then, after 2 μsec has elapsed, the reset pulse falls, and at the same time, the shift pulse rises to “1”, and this shift pulse falls to “0” after another 2 μsec. Next, the output of the OR circuit (OR ₂ ) becomes “1” when the Q output (Q ₃ ) of the flip-flop (FF ₃ ) becomes “1”, which means that the reset pulse is “0”. 8 μs after it falls to “”, and eventually the transfer clock pulse (φ ₁ )
Is held in the state of "1" for 10 microseconds. The shift pulse is generated and disappears while the transfer clock pulse (φ ₁ ) is in the state of “1”.

As described above, the transfer clock pulse generation block (10) is reset immediately after the time (t ₂ ) or (t ₃ ) and the newly output transfer clock pulse (φ ₁ ) continues. The shift pulse is generated between the photodiode arrays (P ₁ ) (P ₂ ) (P ₃ ) ... (P _n-2 ) in the image sensor array (PA).
This is to prevent the end point of the charge accumulation (integration) of (P _n-1 ) (P _n ) from being unnecessarily delayed. This is temporarily (t ₂ ).
Or (t ₃₎ after the time point in synchronization with the transfer clock pulses generated in the first-th (phi ₁₎ when to generate a shift pulse, substantially transmit at the highest from the time of (t ₂₎ or (t ₃₎ Time photodiode of one cycle of clock pulse (P
₁ ) (P ₂ ) (P ₃ ) ... (P _n-2 ) (P _n-1 ) (P _n ) may be stored unnecessarily, and when the subject is extremely bright May be saturated and a correct image signal may not be obtained. Further, since the shift pulse is generated at any time point after the time points (t ₂ ) or (t ₃ ), the shift pulse is not always constant, which may cause a problem that the image signal level is not constant. On the other hand, in FIG. 7, since there is always a shift pulse within two cycles (4 μsec) of the reference clock pulse from the time point (t ₂ ) or (t ₃ ), there is no such fear.

As shown in FIG. 7, the next transfer clock pulse (φ ₁ ) is output (Q ₃ ) (Q ₄ ) (Q ₅ ).
After 120 μs when all of (Q ₆ ) becomes “0”, it becomes “1”, and the time for maintaining this state is 8 μs. All transfer clock pulses after this transfer clock pulse are 8
The state is “1” for μ seconds, and then the state is “0” for 120 seconds. Therefore, the cycle of the transfer clock pulse (φ ₁ ) is 128 μs, its duty cycle is not 1/2, and the duration ratio between the “1” state and the “0” state is 1
/ 15. With this arrangement, the transfer of the accumulated charge from one cell of the CCD shift register (SR) to the image signal output circuit (VS) is performed at the falling edge of the clock pulse, so that signal processing, particularly A / D conversion, is performed. Since the A / D time in the converter (ADC) can be secured sufficiently and an inexpensive A / D converter with a slow conversion speed can be used as the (ADC), the cost of the camera using this can be reduced. Can be achieved.

FIG. 8 shows the output of the image signal output circuit (VS) and the amplifier (26) after the shift pulse of the image sensor is generated, and the output of the transfer clock pulse (φ ₁ ) (φ ₂ ) and the reference signal generation circuit (RS). It shows with. In the case of FIG. 7, it is assumed that the CCD shift register (SR) is in an empty state when the shift pulse is generated. To create this empty state, a photodiode (P
₁ ) (P ₂ ) (P ₃ ) ... (P _n-2 ) (P _n-1 ) (P _n ) without transferring the charge accumulation of CCD shift register (SR) to CCD shift register (SR) Transfer clock pulses (φ ₁ ) (φ ₂ ) may be applied to the register by the number of cells. For example, the number of cells in the register (SR) is 1
When it is 00, 100 transfer clock pulses (φ
_{If 1} ) and (φ ₂ ) are given, all the accumulated charges in the register are discharged. However, it is the fact that the charge accumulated in the CCD shift register (SR) is not completely discharged in one charge discharging operation when the image sensor is activated, so in this case, the discharging operation is usually repeated several times. Therefore, create a completely empty state. Such a series of operations is called an initialization operation of the image sensor.

In FIG. 8, the photodiodes (P ₁ ) (P ₂ ) (P ₃ ) ... (P _n-2 ) are generated by the generation of the shift pulse.
The charge accumulation of (P _n-1 ) (P _n ) is stored in the CCD shift register (S
R) in parallel, and the accumulated charge of the cell (R ₁ ) is transferred to the image signal output circuit (VS) at the trailing edge of the _first transfer clock pulse (φ ₁ ). As a result the image signal output circuit (VS) outputs a terminal _{(T 3)} to the output corresponding to the accumulated charge of the cell _{(R 1)} (Vos1). Thereafter, every time the transfer clock pulse (φ ₁ ) falls, the cell (R ₂ ) (R
₃ ) ... Output (Vos ₂ ) corresponding to the accumulated charge of (R _{n + 3} ).
(Vos ₃ ) ... (Vos _{n + 3} ) are sequentially arranged in the image signal circuit (V
It is output from S). Of those outputs, (Vo
s ₁ ) (Vos ₂ ) (Vos ₃ ), the output corresponding to the accumulated charge of the empty feed cells (R ₁ ) (R ₂ ) (R ₃ ), and (Vos ₄ )-(Vos _{1 3} ). Is a dark output corresponding to the accumulated charges of the photodiodes (P ₁ ) to (P _{1 0} ) coated with aluminum, that is, the cells (R ₄ ) to (R _{1 3} ). Between these two types of output, as shown by ΔS, the photodiode (P ₁ )
Through (P _{1 0} ) causes a difference corresponding to the accumulated charge amount based on the dark current generated. Arithmetic circuit shown in _{(V 1)} (2
The output of 2) is V ₁ = Vref− for each (Vos).
(Vos ₅ ) to (Vos _{1 2} ) out of the outputs of the arithmetic circuit (22) corresponding to the dark outputs (Vos ₄ ) to (Vos _{1 3} ).
Corresponding to the above are taken into the above-mentioned peak value detection circuit (24). Then, the one having the maximum value is output from the peak value detection circuit (24) as (V ₂ ). In FIG. 8, the broken line indicates this (V ₂ ), and therefore V ′ = V ₁ −V ₂ is Vout = E + (V ₁ −
It corresponds to the output of the amplifier (26) represented by V ₂ ) × A.

Next, the operation of the microcomputer (30) shown in FIG. 1 and the operation of the entire circuit by the operation will be described with reference to the flowchart of FIG. First, when a start signal is given to the microcomputer (30) by operating a switch (not shown), the microcomputer (30) causes the terminal (T ₂
The signal of "1" is output to ₂ ) to initialize the image sensor. That is, inputted to the CCD shift register (SR) via a fast clock pulses of the period of from the transfer clock pulse (φ ₁₎ (φ ₂₎ as a clock circuit (CL ₂₎ the terminal _(T 4) _{(T 5)} . At this time, the terminal (T 1 ₉₎ from being output signal "0" to prohibit the generation of shift pulses accumulated since the shift pulse is not generated from the CCD shift register (SR) is an image sensor array (PA) It sequentially discharges its accumulated charge without receiving the charge. (Alternatively, the generation of the shift pulse is not prohibited, the integration clear pulse is generated as in the normal CCD drive, and then the shift pulse is immediately generated so that the accumulated charges can be ignored, and then the transfer clock pulse is used to generate the CCD shift register. The accumulated charge may be discharged.) This discharging operation is repeated several times as described above, whereby the CCD shift register (SR) becomes empty. Here, one discharge operation corresponds to the number of transfer clock pulses (φ) of the number of cells of the CCD shift register (SR).
₁ ) (φ ₂ ) is given to finish.

After a predetermined time for guaranteeing the discharging operation for several times has passed, the microcomputer (30) causes the terminal (T
The output of _{2 2} ) is set to “0” and the clock circuit (CL ₁ )
A pulse having a duration ratio of 1/15 between the "1" state and the "0" state, which is formed based on the reference clock pulse from, is set as a transfer clock pulse (φ ₁ ), and a pulse having an opposite phase to the transfer clock pulse (φ ₁ ). φ ₂ ) is input to the CCD shift register (SR). Then the microcomputer (30) is pin step # 2 _{(T 1} 9)
Outputs a signal of permitting the generation of shift pulse "1", thereby AND circuit (AN ₂₎ is opened. When the accumulation clear pulse is outputted from the terminal _{(T 1 7)} in # 3 step, the flip-flop (FF ₀₎ is set, the AND circuit (AN ₁₎ is also opened. At the same time, the integration clear pulse is input to the integration clear gate (ICG) to clear the accumulated charge of each photodiode of the image sensor array (PA), while the FET
(Q ₁ ) (Q ₄ ) conducts and the capacitor (C ₁ ) (C
₂ ) is charged to the level of the power supply voltage. This integration clear pulse disappears at time (t ₀ ), whereby each photodiode of the image sensor array (PA) starts to accumulate electric charges, and at the same time, depending on the subject brightness detected by the monitor light receiving element (PM). The output voltage (Vm) of the brightness monitor circuit (MC) starts to drop at a high speed as shown in FIG. At the same time when the integration clear pulse disappears, the microcomputer (30) sets the internal programmable preset counter at step # 4, and this counter starts counting a predetermined time of 100 ms.

Next, the microcomputer (30) goes to # 5.
In the step of, the output voltage (V of the brightness monitor circuit (MC)
It is determined whether or not the drop value of m) has reached 2.8 V based on the output (e) of the brightness determination circuit (40) input to the terminal (T _{2 0} ) and the output (e) is “1”. Then, when it is determined that the case is shown by (l ₅ ) in FIG.
Go to step _{9 and set} the output of the terminal (T _{1 9} ) to “0”.
To prohibit the generation of shift pulses. However, at the output (e) is "1", as shown in FIG. 6, the shift pulse from the D flip-flop followed by a reset pulse from a very short time D flip-flop within the (DF ₁₎ (DF ₂₎ Then, the reset pulse resets the flip-flop (FF ₀ ) and closes the AND circuits (AN ₁ ) (AN ₂ ). It is a shift pulse that may be newly generated thereafter. On the other hand, in step # 5, the output (e) is "0".
Then, in the case where any of the cases indicated by (l ₁ ) (l ₂ ) (l ₃ ) (l ₄ ) in FIG. 5 occurs, the microcomputer (30) performs the above-mentioned programmable preset in step # 6. "1" is felt from the contents of the counter, and it is judged in step # 7 whether the contents of the counter have become "0". If the content is not "0", the process returns to step # 5, and after step # 6, #
In step 7, it is determined again whether the contents of the programmable preset counter have become "0". here,
The time required for the step cycles # 5, # 6, and # 7 is t
If s, it is set so that ts × N = 100 msec. Therefore, if the steps of # 5, # 6, and # 7 are repeated N times, the content of the programmable preset counter becomes “0”. . That is, when the counter # 4 in step elapses 100m seconds since the set, the microcomputer (30) outputs a signal of "1" from the terminal (T 1 ₈₎ in step # 8, the signal A reset pulse is output from the D flip-flop (DF ₁ ) via the AND circuit (AN ₁ ) (OR ₁ ) and input to the D input of the flip-flop (DF ₁ ). Therefore, the D flip-flop (FF ₀ ) is reset and the AND circuits (AN ₁ ) (AN ₂ ) are closed, while D
A shift pulse is generated from the flip-flop (DF ₂ ). However, also in this case, the amount of decrease in the output voltage (Vm) of the brightness monitor circuit (MC) is 2.8 as the time further elapses.
Prohibited reaches the V, becomes an output (e) is "1" in the picture judging circuit (40), since it is determined at step # 5, the occurrence of shift pulses later from the terminal (T 1 ₉₎ Signal of "0" is output.

The shift pulse generated as described above is input to the terminal (T _{2 1} ) of the microcomputer (30), and also the shift gate (S ₇ ) is passed through the terminal (T ₇ ).
It is input to G). As a result, the accumulated charge of each photodiode of the image sensor array (PA) is transferred to the corresponding cell of the CCD shift register (SR), and further the transfer clock pulses (φ ₁ ) (φ ₂ ) of the register (SR) sequentially. The accumulated charge of each cell is transferred to the image signal output circuit (VS). Then, the image signal (Vo) is output from the output terminal (T ₃ ) of the image signal output circuit (VS).
s ₁ ) (Vos ₂ ) ... (Vos _{n + 3} ) are sequentially output, and the signal represented by Vout = E + (V ₁ −V ₂ ) A is sequentially output from the amplifier (26). These signals are sequentially A /
The signal is converted into a digital signal by a D converter (ADC) and is sent to a microcomputer (3) via a data bus (DB ₁ ).
0) is input.

On the other hand, when the above-mentioned shift pulse is input to the terminal (T _{2 1} ), the microcomputer (30) outputs # 1.
0 step for outputting an integration clear pulse from a terminal _{(T 1 7).} Therefore, image sensor array (PA)
The accumulated charge in each photodiode is cleared, and the charge accumulation in each photodiode is restarted at the same time when the integration clear pulse disappears. Of course, the output of the brightness monitor circuit (MC) also begins to drop at a speed corresponding to the brightness of the subject detected by the monitor light receiving element (PM) as described above. That is, although the second charge accumulation cycle is started, the micro-computer (30) counts the number of cells of the CCD shift register (SR) this time by the internal programmable preset counter at the same time when the integration clear pulse disappears. To set. This is # 1
This is step 1. Micro Computer (30)
Receives the digital signal corresponding to the accumulated charge of each cell from the A / D converter (ADC) and stores it in the internal random access memory (step # 12). By subtracting 1 from the content (step # 13), it is determined in step # 14 whether or not the content has become "0". When the contents of the programmable preset counter set in step # 11 become "0", the process proceeds to step # 15. In this step, the microcomputer (30) performs, for example, the following calculation to calculate the focus adjustment state of the taking lens (TL), that is, the defocus amount and the defocus direction with respect to the planned focal plane (F). That is, the image sensor array (P
Photodiode (P ₁ ) (P ₂ ) (P ₃ ) ...
_{(P n-2) (P} n-1) (P n) from (P ₁₎ to one of (P 1 ₀₎ minus the, what is included in the region where the first image described above in FIG. 4 is formed The reference part of the photodiode,
What is included in the area where the second image is formed is the photodiode of the reference portion, and the photodiodes of the reference portion and the reference portion are respectively (A ₁ ) (A ₂ ) from one side of the image sensor array (PA). … (A _m ), (B ₁ ) (B ₂ )…
(B _{m + k-1} ), digital signals from the A / D converter (ADC) corresponding to the charges accumulated in them are (a ₁ ) (a ₂ ) ... (a _m ), (a _m ), b ₁ ) (b ₂ ) ... (b
_{m + k-1} ),

[0046]

[Equation 1]

, K sets of C ₁ , C ₂ , ..., C are performed.
_{Find the} smallest of _k-1 and C _k . For example, C
_If the value of ₂ is the minimum, the photodiode (A
₁ ) (A ₂ ) ... (A _m ), the image formed on the reference photodiodes (B ₂ ) (B ₃ ) ... (B _m ) (B _{m + 1} ) best matches the image formed on (A _m ). ing. Therefore, in this case, the distance between the photodiodes (A ₁ ) and (B ₂ ) on the image sensor array (PA) is the distance between the above-mentioned first and second images, which is determined by the focus detection optical system. By comparing the predetermined distance between the first and second images at that time, the defocus amount and the defocus direction of the taking lens at that time can be calculated. Note that the calculation method described here is an example, and in order to determine the defocus amount more accurately, for example, the present applicant has proposed it in Japanese Patent Application Nos. 58-2622 and 58-113936. The same calculation method may be used.

When the above-mentioned calculation in step # 15 is completed, the microcomputer (30) again outputs the output (Vm) of the brightness monitor circuit (MC) based on the output (e) of the brightness determination circuit (40). Voltage drop is step # 11
It is determined in the step # 16 whether or not the voltage reaches 2.8 V in the period from # 15 to # 15. It is assumed that, for example, 50 msec is required to execute the steps from # 11 to # 15. If the output (e) is "1" and the voltage drop amount of the output (Vm) has reached 2.8 V, the integration clear pulse is again output from the terminal (T17) in step # 17,
The charge accumulated in each photodiode of the image sensor array (PA) during the execution of steps # 12 to # 15 is cleared, and the charge accumulation is restarted in them. This is because if the output (e) is "1" at the time of the determination in step # 16, the image sensor array (P
This is because the charge storage of each photodiode in A) may already be saturated. In this case, the microcomputer (30) sets the internal programmable preset counter to count 100 ms in step # 17 at the same time when the integration clear pulse disappears, and then shifts from the terminal (T19) in step # 18. It outputs a signal of "1" that permits the generation of pulses. And
After that, the process returns to step # 5 and the above steps are sequentially repeated. On the other hand, if the output (e) is “0” in the step of # 16 and the voltage drop amount of the output (Vm) has not reached 2.8 V, the microcomputer (30) causes the above in the step of # 20. Set the programmable programmable counter to count 50 ms,
Then, the process proceeds to step # 19 above. At this time,
The counter is set to count 50 msec because about 50 msec has already passed after the integration clear pulse output in the step # 10 disappears as described above, and the remaining 50 msec is counted by the counter. This is because, if it is counted by, the charge accumulation for a total of 100 msec is allowed in each photodiode of the image sensor array (PA). That is, in this case, # 5, # 7, #
8 step cycles are repeated up to 50 / ts times.
Of course, if the programmable preset counter can be used exclusively for other purposes, use # 1
After the step 0 is completed, the programmable preset counter may be set so as to count 100 ms, and the step # 20 is unnecessary.

The operation of the microcomputer (30) and the operation of the entire circuit by the operation have been described above with reference to FIG. 9. However, as can be understood from the above description, in this embodiment, an image is obtained by the shift pulse. The generation of a new shift pulse is prohibited from the start of the transfer of the charges accumulated in the photodiodes of the sensor array (PA) to the end of the calculation of the defocus amount and the defocus direction in the microcomputer (30). In addition, each photodiode of the image sensor array (PA) starts charge accumulation immediately after the generation of the previous shift pulse without the end of the calculation. The reason for this is as follows. In other words, drive the shooting lens based on focus detection,
When performing the focus adjustment, the photographing lens can be focused in a shorter time as the number of focus detection operations performed within a fixed time increases. Therefore, considering the time required for one focus detection operation, the charge accumulation (photocurrent integration) time Ti in the image sensor array (PA) of the CCD and the charge accumulated in the image sensor array are calculated by the CCD shift register ( The time Td required to transfer the image signal to the image signal output circuit (VS) via the SR and subsequently calculate the signal processing and the defocus amount and the defocus direction (this is referred to as data processing time for convenience). (Ti + Td), and when the focus detection operation is repeatedly performed continuously, if the next detection operation is performed after the previous detection operation is completed,
The time (Ti + T) required to perform the detection operation n times
d) × n. However, the speed of charge accumulation (photocurrent integration) in the image sensor array (PA) of the CCD depends on the intensity of light incident on it, and if the incident light intensity is low, the speed becomes slow, and charge accumulation for a long time occurs. Must be done. For this reason, the time required for one focus detection operation becomes long, and the number of focus detection operations that can be performed within a certain period of time is restricted, so that the taking lens cannot be focused in a short time. On the other hand, in the case of CCD, the image sensor array (PA) is used when the accumulated charge is being transferred from the shift register (SR) to the image signal output circuit (VS).
There is no problem even if the charge is stored in. Therefore,
When the integration clear pulse can be generated immediately after the shift pulse is generated, and the image sensor array (PA) accumulates new charges during the above-described data processing time Td, the incident light intensity is low. However, the time required for one focus detection operation is shortened, the number of focus detection operations performed within a fixed time is increased, and the photographing lens can be chorused in a short time. However, on the other hand, if new accumulated charges are transferred to the CCD shift register (SR) while the accumulated charges of the CCD shift register (SR) are being transferred to the image signal output circuit (VS) (this is due to the structure of the CCD). The above is possible), CCD
Old and new accumulated charges are mixed in the shift register (SR), and an erroneous image signal is output. Further, the microcomputer (30) cannot hold a new signal because it must hold the data in the random access memory during the calculation in step # 15. Therefore, the shift pulse is prohibited during the above-mentioned data processing time Td.

10A and 10B show how the focus detection operation is repeated in the above embodiment. FIG. 10A shows the case of Ti <Td, and FIG. 10B shows the case of Ti> Td. . In FIG. 10A, the points indicate the charge accumulation period after the disappearance of the integration clear pulse generated in the step # 10, but the charges accumulated during this time are generated by the integration clear pulse generated in the step # 17 as described above. Cleared. In contrast, FIG. 11A and FIG.
As shown in FIG. 11, B is the case where the photodiode of the image sensor array (PA) is made to start the charge accumulation after the data processing is completed, as shown in FIG.
A shows the case of Ti <Td, and FIG. 11B shows the case of Ti> Td. Comparing FIG. 11B with FIG. 10B, it can be clearly seen that the number of focus detection operations within a fixed time increases in the above-described embodiment.

Although the present invention has been described with reference to one embodiment, the present invention is not limited to the above embodiment. For example, as a self-scanning image sensor, C
Not only CD but also BBD (Bucket Bridge)
e Device), CID (Change Injec)
function device, MOS (Metal Ox)
An image sensor (ide semiconductor) type image sensor or the like can be used. Moreover, the focus detection method is also shown in FIG.
It is not limited to those using the focus detection optical system of
For example, JP-A-54-159259 and JP-A-57-57
No. 70504, Japanese Patent Application Laid-Open No. 57-45510, etc., a lenslet is arranged on a planned focal plane of a photographing lens or a plane conjugate therewith, and a self-scanning image sensor is arranged behind it. In this way, the focus adjustment state of the taking lens, the defocus amount, and the defocus direction are calculated, or the method described in JP-A-55-155.
As shown in Japanese Patent Application Laid-Open No. 308, Japanese Patent Application Laid-Open No. 57-72110, Japanese Patent Application Laid-Open No. 57-88418, and the like, self-scanning is performed on the planned focal plane of the taking lens, the plane conjugate therewith, and the front and back thereof. The present invention is also applicable to a method in which a mold image sensor is arranged and only the defocus direction is detected as the focus adjustment state of the photographing lens.

[0052]

As described above, in the image processing apparatus of the present invention, the charge of a new image is stored in parallel with the focus detection processing in the readout processing circuit, so that the charge of a new image is stored once. The detection cycle from one focus detection to the next focus detection can be shortened. By shortening the focus detection cycle, the time required to focus the shooting lens is also shortened, and even if it takes time to accumulate charges on a subject with low brightness, the time to focus can be shortened. Less chances to miss.

[Brief description of drawings]

FIG. 1 is an overall circuit diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing details of a photoelectric conversion block (1) in FIG.

FIG. 3 is an equivalent circuit diagram of a photodiode and an integral clear gate that configure each pixel of the image sensor array.

FIG. 4 is a diagram showing a focus detection optical system of a camera.

FIG. 5 is a diagram showing a temporal change of the output of the monitor circuit.

FIG. 6 is a circuit diagram showing a specific example of a brightness determination circuit (40) and a block (20) of FIG.

FIG. 7 is a diagram showing output waveforms at various parts of the circuit of FIG.

FIG. 8 is a diagram showing output waveforms at various parts of the circuit of FIG.

FIG. 9 is a flowchart showing the operation of the microcomputer.

FIG. 10 is a time chart showing a repeated focus detection operation.

FIG. 11 is a time chart showing a repeated focus detection operation when charge accumulation is started in each photodiode forming the image sensor array of the image sensor after the data processing.

[Explanation of symbols]

1 Self-scanning image sensor VS Image signal output circuit # 3 Start signal output means DF ₂ Shift pulse generation means 10 Transfer clock pulse generation means 30 Control means

Claims (1)

[Claims] 1. An image signal output circuit obtains an image signal based on accumulated charges sequentially transferred from a self-scanning image sensor having a charge accumulation unit and a transfer unit for transferring accumulated charges, and a focus detection process is performed by a processing circuit. In the image processing device, a start signal output unit that outputs a start signal for starting the charge accumulation operation of the charge accumulation unit, and a shift pulse for transferring the charge accumulated in the charge accumulation unit to the transfer unit. Shift pulse generating means for generating, transfer clock pulse generating means for generating a transfer clock pulse for sequentially transferring the charges transferred to the transfer section to the image signal output circuit, and before the focus detection processing by the processing circuit ends. By restarting the operation of the start signal output means, the accumulated charge is generated by the shift pulse generating means and the transfer pulse generating means. And a control means for controlling such that the restarted charge storage operation in the image storage unit is performed in parallel during the focus detection processing period by the processing circuit. .