JPH067682B2 - Integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit formed of a PN junction.

[Conventional technology]

Conventionally, in a bipolar type semiconductor integrated circuit formed by a PN junction, a capacitor is easily discharged. Therefore, when an ACC circuit (automatic chroma control circuit) of a color television receiver is formed by this type of semiconductor integrated circuit. For example, as described in Japanese Patent Publication No. S57-14072 (H04N 9/46), a peak hold capacitor is externally attached.

Further, when a low-frequency or wide-band amplifier is formed by this kind of semiconductor integrated circuit, the level shift using a coupling capacitor cannot be performed, so that it is formed as a DC coupling type.

[Problems to be Solved by the Invention]

In the conventional semiconductor integrated circuit, as described above, the peak hold capacitor must be externally attached,
There is a problem that the ACC circuit and the like cannot be easily manufactured.

Further, since a low-frequency or wide-band amplifier has to be formed as a DC coupling type, there is a problem that circuit design and the like cannot be easily performed.

It is an object of the present invention to provide an integrated circuit in which a peak hold capacitor formed by a PN junction is prevented from discharging and a peak hold capacitor and a coupling capacitor are built in.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, in the integrated circuit of the present invention, a peak hold portion of a transistor structure is provided by forming a PN junction, and is intermittently charged by an input signal of the peak hold portion and is in a non-charge period. Has a main capacitor that discharges at a substantially constant current through the PN junction of the peak hold section, and a sub-capacitor formed by the PN junction in substantially the same manner as the main capacitor. Of the transistor structure, which holds the circuit state almost the same as the non-charging period, and the constant voltage control of the main capacitor and the sub capacitor for the constant voltage control following the discharge decrease of the potential of the sub capacitor from the reference potential. The technical means is provided by including a constant voltage circuit section of a transistor configuration that injects each of the main and sub compensation currents.

[Work]

The integrated circuit of the present invention configured as described above detects the discharge decrease of the main capacitor of the peak hold part formed by the PN junction from the discharge decrease of the sub capacitor of the discharge simulation part, and discharges the sub capacitor. The main and sub-compensation currents of the constant voltage circuit that follow the drop are injected into the main and sub-capacitors respectively to prevent discharge during the non-charging period of the main capacitor and hold the main capacitor at the charged potential.

Therefore, the main capacitor is the peak hold capacitor,
As a coupling capacitor, the input signal peak hold and level shift can be performed with the built-in capacitor.

〔Example〕

An embodiment will be described below with reference to FIGS. 1 to 3.

First Embodiment First, one embodiment will be described with reference to FIGS. 1 and 2.

Fig. 1 shows the main condenser A of a color television receiver.
The figure shows the case where it is used for the peak hold capacitor of the CC circuit. In the figure, (1) is the power supply terminal of the voltage Vcc, (2) is the input terminal of the demodulation color burst signal, and (3) and (4) are the burst period. It is an input terminal for a pair of burst gate pulses having opposite phases, which are inverted to high level and low level.

(Q1) is an NPN type input transistor whose base is connected to the input terminal (2) through a resistor (R1), and (Q2) and (Q3) are base input terminals (3) and (4) respectively. A pair of NPN type transistors of differential pair configuration connected to each other, (Q4) for NPN type constant current source provided between the emitters of the transistors (Q2) and (Q3) and the resistor (R2) Is a transistor.

(Q5) and (Q6) are transistors for NPN type input buffer directly connected between the emitter of the transistor (Q1) and the input terminal of the ACC amplifier (5), and (Q7) is a transistor.
It is a transistor for NPN type constant current source provided between the emitter (Q6) and the resistor (R3).

(C1) is a small-capacity (several tens of PF) main capacitor formed of a PN junction, one end of which is connected to the emitter of the transistor (Q1) and the base of the transistor (Q5), and the other end of which is grounded. (6) is a peak hold unit for ACC detection formed by the transistors (Q1) to (Q7) and the main capacitor (C1).

(Q8), ..., (Q14) are seven NPN-type transistors, which are almost the same as the transistors (Q1) to (Q7) respectively. The base circuits of the transistors (Q8) to (Q10) and the transistor (Q13)
Except for the collector circuit of, the transistors (Q1) to (Q7) are connected in almost the same circuit configuration.

(E1) is a bias power supply connected to the base of the transistor (Q8) via a resistor (R4), and (E2), (E3), and (E4) are three bias power supplies connected in series. The voltage of E2) is applied to the bases of transistors (Q4), (Q7), (Q11), and (Q14), and the series bias voltage of power supplies (E2) and (E3) is applied to the transistors.
A series bias voltage of the power supplies (E2) to (E4) is applied to the base of (Q9) and is applied to the base of the transistor (Q10). (R5) and (R6) are two resistors connected to the emitters of the transistors (Q11) and (Q14), respectively.

(C2) has the same area and shape as the main capacitor (C1)
Sub capacitor formed by N junction, (Q15) is a transistor
An NPN transistor that forms a differential pair with (Q13), (Q1
6) is an NPN type transistor which applies a bias voltage to the base of the transistor (Q15), and which is a resistor (R
The reference voltage divided in 7) and (R8) is applied to the base. (7) is the transistor (Q8) to (Q16) and the sub capacitor (C
It is a discharge simulation part formed by 2).

(Q17), (Q18), and (Q19) are three PNP-type transistors forming a current mirror circuit.
According to the collector current of 13), the collector current of the transistor (Q19) changes. (Q20), (Q21), (Q22), (Q23) and (R9) are four PNP-type transistors and resistors that form a current mirror circuit, and are transistors according to the collector current of the transistor (Q15). The collector currents of (Q22) and (Q23) change.

(Q24), (Q25), (Q26), (Q27), and (R10) are four NPN-type transistors and resistors that form a current mirror circuit, and reduce the collector current of the transistor (Q19). Then, the collector currents of the transistors (Q26) and (Q27) connected to the collectors of the transistors (Q22) and (Q23) decrease by the same amount. (8) is a transistor (Q17) to (Q27) and a resistor (R
9), a constant voltage circuit formed by (R10).

In addition, each transistor (Q1) to (Q27), each resistor (R1) to (R1
0) and both capacitors (C1) and (C2) are formed by each PN junction of the semiconductor integrated circuit together with the amplifier (5) and the like.

Further, in order to make the main and sub compensation currents ID and ID 'injected into the capacitors (C1) and (C2) the same, the transistor (Q2
2) and (Q23) are formed in substantially the same area and shape, and the transistors (Q26) and (Q27) are formed in substantially the same area and shape.

Then, based on the burst gate pulse at the input terminals (3) and (4), the transistors (Q2) and (Q3) are turned on and off at each burst period, and the demodulated color burst signal at the input terminal (2) is inverted. Flows through the transistor (Q1) to the base of the transistor (Q5) and the capacitor (C1),
(C1) is charged.

At this time, the base input impedance of the transistor (Q6) seen from the emitter of the transistor (Q1) is high due to the direct connection circuit of the transistors (Q5) and (Q6) with the collector grounded, and the capacitor (C1) almost completely demodulates the burst signal. Hold the peak.

During the period excluding the burst period, the transistor (Q
2) and (Q3) are turned off and on respectively
(Q1) is turned off, and the hold voltage of the capacitor (C1) is applied to the amplification unit (5) via the transistors (Q5) and (Q6).

At this time, the charge stored in the capacitor (C1) is
2), discharge current IA, IB to the base of (Q5) and discharge as discharge current IC flowing through the capacitor (C1), and simulate section
(7) Without the constant voltage circuit section (8), the electric potential of the capacitor (C1) drops and the peak hold cannot be performed.

Then, the discharge currents IA and IC become substantially constant reverse saturation currents IS equal to or lower than the breakdown point voltage VS of FIG. 2 showing the current characteristics of the PN junction.

Further, since the collector current IK of the transistor (7) is held constant and the current IL flowing from the emitter of the transistor (Q6) to the amplifier (5) is set to IL << IK, the discharge current IB is almost constant. Forward current.

Therefore, the discharge current of capacitor (C1) (= IA + IB
+ IC) becomes a substantially constant current independent of voltage.

On the other hand, based on the setting of the base bias voltage of the transistors (Q8) to (Q10), the transistors (Q8) and (Q9) are kept off, the transistor (Q10) is kept on, and the transistor (Q8)
~ (Q14) keeps the capacitor (C2) in almost the same circuit state as the capacitor (C1) during the discharging period, and discharge current I
A, IB, and IC have almost the same discharge current IA ',
The capacitor (C2) is discharged by IB 'and IC'.

Also, a constant reference voltage divided and set by resistors (R7) and (R8) is applied to the base of the transistor (Q16),
The collector current of (Q14) becomes 2IK which is twice the collector current IK of the transistor (Q7).

Then, as the base voltage of the transistor (Q12) is increased or decreased from the reference voltage, the collector current of the transistor (Q13) changes and the collector current of the transistor (Q16) changes vice versa.

Further, the collector current of the transistor (Q19) changes according to the collector current of the transistor (Q13), and the collector current of the transistor (Q24) and the base current of the transistor (Q25) are adjusted.

Then, according to the base current of the transistor (Q25), the base currents of the transistors (Q24), (Q26), (Q27) change, and the base voltage of the transistor (Q12) increases and decreases.
Transistor (Q2) for charge / discharge adjustment of capacitors (C1) and (C2)
7), (Q26) collector current changes.

In addition, the collector currents of the transistors (Q22) and (Q23) change according to the collector current of the transistor (Q15).

Therefore, the base voltage of the transistor (Q13) becomes the reference voltage by the main and sub compensation currents ID and ID 'based on the collector currents of the transistors (Q23) and (Q22).
The main and sub capacitors (C1) and (C2) are charged to control the constant voltage.

At this time, the compensation current ID 'becomes equal to the discharge current (= IA' + IB '+ IC') of the capacitor (C2).

Further, the discharge currents IA ', IB' and IC 'are the discharge currents I
Since the currents are substantially the same as those of A, IB, and IC and do not depend on the voltage, the following formula is established no matter how the reference voltage is set.

IA + IB + IC = IA '+ IB' + IC 'Further, transistors (Q22) and (Q23), a transistor (Q2
Since 6) and (Q27) are formed to have substantially the same area and the same shape, the compensation current ID becomes substantially the same as the compensation current ID '.

Then, based on the charging of the compensation current ID, the capacitor (C
The discharge of 1) is canceled and prevented, and apparently the input impedance of the transistor (Q5) becomes infinite, the demodulation color burst signal is peak-held by the capacitor (C1), and the capacitor (C1) is the peak-hold capacitor. To work as.

(Other Embodiment) Next, another embodiment will be described with reference to FIG.

Fig. 3 shows the case where the main capacitor is used as a coupling capacitor. In the same figure, the same symbols as those in Fig. 1 show the same or corresponding ones, (9) is a video signal input terminal, and (10) is a video signal. This is a signal output terminal and is connected to the input terminal (9) via a resistor (R11). (11) is a high-level burst gate pulse input terminal.

(Q28) and (Q29) are two NPN-type transistors forming a differential pair, and the video signal of the input terminal (9) via the resistor (R11) is connected to the resistor (R13) and the capacitor (C3). A voltage Vcc, which is input to the base of the transistor (Q28) through a low-pass filter and divided by the resistors (R13) and (R14), is applied. (R16) is a collector load resistor provided between the power supply terminal (1) and the collector of the transistor (Q28).

(Q30) is the transistor (Q28) and (Q29) emitter and resistor (R1
It is a transistor for an NPN type constant current source provided between the input terminal (11) and the gate pulse of the input terminal (11).

(Q31) is a PNP type emitter grounded transistor whose base is connected to the collector of the transistor (Q28). The emitter is connected to the power supply terminal (1) via the resistor (R17) and the collector is the resistor (R18). Is grounded through.

(Q32) is an NPN collector grounded transistor whose base is connected to the collector of the transistor (Q31), whose collector is connected to the power supply terminal (1) and whose emitter is a capacitor.
It is connected to (C1).

(Q33) and (Q34) are two directly connected two-stage NPN-type collector-grounded transistors. The transistor (Q33)
Is connected to the transistor (Q32) in Darlington connection, and the collector and the emitter of the transistor (Q34) are connected to the output terminal (10) and the resistor (R19).

(6) ′ is a transistor (Q28) to (Q34) and a resistor (R11) to (R1
9) It is the peak hold part for level shift formed by the capacitor (C1).

(9) is a constant current source provided in the common emitter path of the transistors (Q13) and (Q15) of the simulation section (7), which corresponds to the transistor (Q14) and the resistor (R6) of FIG. It consists of resistance.

In FIG. 3, transistors (Q8), (Q12),
(Q13) is formed substantially the same as each of the transistors (Q32), (Q33), (Q34), and the transistors (Q9) to (Q1) shown in FIG.
The bias of transistor (8) due to 1), power supplies (E1), (E3), and (E4) is omitted.

Transistors (Q28) to (Q34), resistors (R11) to (R19), capacitors (C3), etc. are also transistors (Q8) to (Q27), resistors (R4), (R7) to (R10), capacitors. Similar to (C1) and (C2)
It is formed by a PN junction of an integrated circuit.

Then, the DC component of the video signal at the input terminal (9) is
2), extracted by the capacitor (C3) and supplied to the base of the transistor (Q28).

Further, the transistor (Q30) is turned on only during the input period of the burst gate pulse of the input terminal (11).

Then, when the transistor (Q30) turns on, the differential pair of the transistors (Q28) and (Q29) operates, and the transistor (Q28)
Collector current changes with the increase and source of the DC component.

Furthermore, the collector current of the transistor (Q31) changes as the collector current of the transistor (Q28) increases and decreases, and the emitter current of the transistor (Q32) changes as the collector current of the transistor (Q31) increases and decreases. Changes.

Therefore, during the charging period when the transistor (Q30) is turned on, the capacitor (C1) is charged by the emitter current of the transistor (Q32) proportional to the DC component, and the capacitor (C1)
Then, the DC component is peak-held.

Next, during the non-charging period when the transistor (Q30) is turned off, the transistor (Q31) is turned off and the transistor (Q32) is held off.

At this time, the charge charged in the capacitor (C1) is
33) Forward discharge current IB to the base and capacitor
It discharges as a reverse discharge current IC passing through (C1).

And because the capacity of the capacitor (C1) is small and the direct impedance of the transistor (Q33) seen from the base of the transistor (Q33) is high due to the direct connection two-stage connection of the transistors (Q33) and (Q34), The discharge current IB becomes an extremely small, almost constant current in the forward direction of FIG.

Therefore, the capacitor (C1) in the non-charging period is discharged by the substantially constant discharge current IB, IC that does not depend on the voltage.

Meanwhile, the transistor (Q8) is held off and the capacitor
(C2) is a discharge current IB, a discharge current IB 'corresponding to IC,
Discharge at IC '.

Then, in the same manner as in the case of FIG. 1, the compensation current ID,
ID 'is formed and the compensation currents ID and ID' are used to form a capacitor.
Each of (C1) and (C2) is charged, and discharge of the capacitor (C1) is prevented.

Furthermore, the emitter current of the transistor (Q33) changes according to the hold voltage of the capacitor (C1), and the transistor
The impedance between the collector and the emitter of (Q34) changes opposite to the hold voltage.

Then, the video signal of the input terminal (9) is divided by the resistor (R11), the collector of the transistor (Q34), the impedance between the emitter and the series circuit of the resistor (R19), and the output terminal (10) is divided.
Is output from.

Therefore, the video signal output from the output terminal (10) is level-shifted and clamped in reverse to the increase and decrease of the DC component of the video signal of the input terminal (9).

Therefore, in FIG. 3, the capacitor (C1) operates as a capacitor equivalent to, for example, the coupling capacitor of the wide band amplifier, and the video signal shifted to a desired level is supplied from the output terminal (10) to the subsequent circuit section. To be done.

Although the input signals are demodulated color burst signals and video signals respectively in the above-mentioned embodiments, the input signals are various signals such as audio signals, and the capacitor (C1) is a peak hold capacitor for various signals. Of course, it can be used as a coupling capacitor.

Further, it goes without saying that the peak hold (6), (6) ', the simulation part (7), the constant voltage circuit part (8) and the like may be formed with a transistor configuration different from those of the above-mentioned embodiments.

〔The invention's effect〕

Since the present invention is configured as described above, it has the following effects.

The decrease in discharge of the main capacitor in the peak hold section formed by the PN junction is detected from the decrease in discharge of the sub capacitor in the discharge simulating section, and the main and sub compensation currents of the constant voltage circuit section follow the discharge decrease in the sub capacitor. Is injected into each of the main and sub capacitors to prevent discharge during the non-charging period of the main capacitor and to keep the main capacitor at the charged potential, so that the peak hold capacitor and the coupling capacitor, which could not be built in the past, are bipolar type. It is possible to provide a peak hold integrated circuit with a built-in capacitor and a capacitor-coupled low frequency or wide band amplifier integrated circuit, etc.

Since the peak hold capacitor does not have to be externally attached, the ACC circuit and the like can be easily manufactured.

Further, a low-frequency or wide-band amplifier integrated circuit can be formed in a capacitor-coupled type to facilitate circuit design and the like.

[Brief description of drawings]

1 to 3 show an embodiment of an integrated circuit of the present invention. FIG. 1 is a connection diagram of one embodiment, FIG. 2 is a current characteristic diagram of a PN junction, and FIG. 3 is another embodiment. It is a connection diagram. (6), (6) '... Peak hold part, (7) ... Discharge simulation part, (8)
… Constant voltage circuit, (C1), (C2)… Main and sub capacitors.

Claims (1)

[Claims] 1. A P in a peak hold portion of a transistor structure.
A main capacitor which is formed by an N-junction, is intermittently charged by an input signal of the peak-hold section, and is discharged at a substantially constant current through the PN-junction of the peak-hold section during a non-charging period; A sub-capacitor formed by joining to be substantially the same as the main capacitor, and a discharge simulating unit having a transistor configuration for holding the sub-capacitor in a circuit state substantially the same as the non-charging period of the main capacitor; And a constant voltage circuit section having a transistor configuration for injecting substantially the same main and sub compensation currents for constant voltage control into the main and sub capacitors, respectively, in accordance with a decrease in discharge of the capacitor potential from the reference potential. Characterized integrated circuit.