JPH03246469A - Peak level detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the error of an output signal due to the input offset voltage of a 2nd differential amplifying circuit by feeding the output signal back directly to the opposite-phase input terminal of a 1st differential amplifying circuit. CONSTITUTION:When the input signal potential of an input terminal 1 becomes higher than the potential of a capacitor C1, the 2nd differential amplifying circuit 4 which is connected in a voltage follower circuit state and an emitter follower circuit provide the feedback to the opposite-phase input terminal of the 1st differential amplifying circuit 3 and the capacitor C1 is charged up to the potential of the input at the terminal 1. When the input signal potential at the terminal 1 falls, the emitter follower circuit Q13 is cut off and the maximum potential is held with charges accumulated in the capacitor C1. The output signal at an output signal terminal 2 is equal in level to the peak level of the input signal at the terminal 1. Namely, the error of the output signal 2 is affected only by the input offset voltage of the 1st differential amplifying circuit 3 and the influence of the input offset voltage of the 2nd differential amplifying circuit 4 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak level detection circuit that maintains the peak level of a signal.

[Conventional technology]

As shown in FIG. 10, the conventional peak level detection circuit includes a differential amplifier circuit 3 consisting of transistors Qll and Q12 connected in a differential manner with the positive phase input terminal 1 as the signal input terminal.
A peak level output 2 was obtained by charging the capacitor C1 with the output signal from the emitter follower circuit through the transistor Q13. Furthermore, as shown in Figure 11,
In order to take out the output signal of the peak level detection circuit shown in FIG. 10 with low impedance, a second differential amplifier circuit 4 was added as a voltage follower connection.

[Problem to be solved by the invention]

In the conventional peak level detection circuit shown in FIG. 11, the peak value of the input signal input to the positive phase input terminal is compared with the potential of the capacitor C1 connected to the negative phase input terminal, and the output signal is is further output through the second differential amplifier circuit, so the disadvantage is that the input offset voltage in the first differential amplifier circuit and the second differential amplifier circuit appears as an error in the output signal. There is. Furthermore, since the input impedance of the second differential amplifier circuit is finite, the charge accumulated in the voltage holding capacitor C1 is discharged as the base current of the transistor Q14 of the second differential amplifier circuit, and the output It also has the disadvantage that it becomes a second source of error in the signal.

It is an object of the present invention to prevent errors caused by the input offset voltage of the second differential amplifier from affecting the output signal, and to suppress the discharge of charges in the voltage holding capacitor. An object of the present invention is to provide a peak level detection circuit that can also reduce errors caused by input offset voltage of a differential amplifier circuit.

[Means to solve the problem]

The peak level detection circuit according to the present invention includes a first differential amplifier circuit connected as a voltage follower with a positive phase input terminal as a signal input terminal, and an output signal of the first differential amplifier circuit that is connected to a first differential amplifier circuit as a signal input terminal.
In the peak level detection circuit, the capacitor is charged through the emitter follower circuit of the first differential amplifier circuit, and the same signal is inputted to the positive phase input terminal of the second differential amplifier circuit connected as a voltage follower. is not connected as a voltage follower, and the output signal of the second differential amplifier circuit is fed back to the negative phase input terminal of the first differential amplifier circuit, and the second differential amplifier circuit A transistor having the same polarity as the input stage transistor is inserted between the collector of the positive phase input stage transistor and the collector load, and the base current of the transistor is used as a reference current source, and the output current is input to the second differential amplification. The circuit is characterized by providing a current mirror circuit that feeds back to the positive-phase input terminal of the circuit, and further comprising a current mirror circuit that feeds back to the positive-phase input terminal of the circuit, and further includes a current mirror circuit that feeds back to the positive-phase input terminal of the circuit, and further includes a current mirror circuit that is connected to the input-stage transistor between the collector of the positive-phase input stage transistor of the first differential amplifier circuit and the collector load. It is characterized by the insertion of transistors with the same polarity.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram for explaining a first embodiment of the present invention. The first differential amplifier circuit 3 includes a constant current source IEEI,
Input stage NPN) transistor Q11°Q21 and PNP as active load) transistor Q12. Q22, whose positive phase input terminal 1 is used as a signal input terminal. The base of NPN transistor Q13 (as an emitter follower circuit) is connected to the output terminal of the 10th differential amplifier circuit 3, the collector is connected to the high potential power supply VCC, and the emitter is connected to the voltage holding capacitor CI.
connected to. The second differential amplifier circuit 4 includes a constant current source IE
E2, input stage NPN) Lancistor Q14゜Q24, PNP as active load) Consists of Lancissistor Q15, Q25, whose positive phase input terminal is connected to emitter follower circuit Q13
connected to the emitter of

An emitter follower circuit consisting of an NPNh transistor Q16 and a constant current source IEE3 is connected with the output signal of the second differential amplifier circuit as input, and outputs an output signal 2 which is the peak level detection signal of this circuit, and at the same time outputs the output signal 2 which is the peak level detection signal of this circuit. It is connected to the anti-phase input terminal of the second differential amplifier circuit.

Next, the operation will be explained with reference to FIG. Input terminal 1
When the potential of the signal input to Q13 becomes higher than the potential held in the capacitor CI, the output signal of the first differential amplifier circuit 3 tends to have a high potential, and therefore the output of the emitter follower circuit, that is, the emitter of Q13 becomes Since the potential is about to become high, the capacitor C1 is charged. However, this potential is
Since the voltage is fed back to the negative phase input terminal of the first differential amplifier circuit by the second differential amplifier circuit and the emitter follower circuit connected to the voltage follower circuit, the capacitor CI has the potential input to input terminal 1 and the first differential amplifier circuit. are charged until the potentials of the negative phase input terminals of the differential amplifier circuit, that is, the potentials of the output terminal 2 of this circuit become equal. Furthermore, when the potential of the input signal at input terminal 1 decreases, the potential at the negative phase input terminal of the first differential amplifier circuit becomes higher than the potential at the positive phase input terminal, and the output signal of the first differential amplifier circuit becomes Although the potential becomes low, the emitter follower circuit Q13 is cut off and the highest potential up to that point is maintained by the charge accumulated in the capacitor C1. In this way, the signal output to the output signal terminal 2 has a potential equal to the highest potential of the signal input to the input signal terminal 1, that is, the peak level of the input signal. In this circuit, since the output signal 2 is directly fed back to the negative phase input terminal of the first differential amplifier circuit, the error due to the input offset voltage of the second differential amplifier circuit is
The error corrected by the first differential amplifier circuit and resulting in the output signal 2 is affected only by the input offset voltage of the first differential amplifier circuit, and is affected by the input offset voltage of the second differential amplifier circuit. is significantly reduced.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram for explaining a second embodiment of the present invention. The first differential amplifier circuit 3 includes a constant current source IEEI,
Input stage NPN) transistor Qll.

Q21 and PNP as active load) transistor Q1
2. Q22, whose positive phase input terminal 1 is used as an input signal terminal. The base of the NPN transistor Q13 as an emitter follower circuit is connected to the output terminal of the first differential amplifier circuit 3, the collector is connected to the high potential power supply CC, and the emitter is connected to the voltage holding capacitor C1. The second differential amplifier circuit 4 includes a constant current source IEE2, an input NPN) transistor Q1
4゜Q24, PNP as active load) transistor Q
15, Q25, and an NPN (NPN) transistor Q17 inserted between the input stage transistor Q14 and the active load transistor Q15, and its positive phase input terminal is connected to the emitter of the emitter follower circuit Q13 described above. NPN)
An emitter follower circuit consisting of a transistor Q16 and a constant current source IEE3 is connected with the output signal of the second differential amplifier circuit as an input, and outputs an output signal 2 which is the peak level detection signal of this circuit, and at the same time outputs the output signal 2 which is the peak level detection signal of this circuit. is connected to the negative phase input terminal of the differential amplifier circuit. The current mirror circuit 5 includes a PNP) transistor Q18. an NPN transistor Q28 inserted in the second differential amplifier circuit;
17 base current is connected to the reference N current,
The collector of transistor Q18 (PNP) is the output terminal of this current mirror circuit and is connected to the base of transistor Q14.

Here, a component different from the first embodiment, that is, the current mirror circuit 5 will be explained. As described above, a base current of 1/Hfe of the collector current flowing through the input stage transistor Q14 of the second differential amplifier circuit flows into the base of the Q14, and the charge accumulated in the capacitor C1 is discharged and becomes the output signal 2. This will result in an error. Therefore, by inserting a transistor Q17 having the same characteristics as the transistor Q14, the collector currents of Q14 and Q17 become almost equal, and the base currents of Q14 and Q17 become almost equal. Therefore, transistor Q18. By returning a current approximately equal to the base current of transistor Q17 to the base of transistor Q14 by the current mirror circuit 5 composed of Q28, it is possible to significantly reduce the error occurring in the output signal 2 due to the base current flowing to Q14. Become.

Next, a third embodiment of the present invention will be described.

FIG. 3 is a circuit diagram for explaining a third embodiment of the present invention. The first differential amplifier circuit 3 includes a constant current source IEEI,
Input stage NPN) transistor Qll.

Q21 and PNP as active load) transistor Q12
．． Q22, whose positive phase input terminal 1 is used as an input signal terminal. The base of the NPN transistor Q13 (as an emitter follower circuit) is connected to the output terminal of the first differential amplifier circuit 3, the collector is connected to the high potential power supply vCC, and the emitter is connected to the voltage holding capacitor C1. Second differential amplifier circuit 4
is constant current source IEE2, input NPN) transistor Q14
゜Q24, PNP as active load) transistor Q1
5, 'Q25, and an NPN) run transistor Q17 inserted between the input stage transistor Q14 and the active load transistor Q15, and its positive phase input terminal is connected to the emitter of the emitter follower circuit 013 described above. An emitter follower circuit consisting of an NPN transistor QI6 and a constant current source IEE3 is connected to receive the output signal of the second differential amplifier circuit, and outputs an output signal 2, which is the peak level detection signal of this circuit, and at the same time outputs the output signal of the first and second differential amplifier circuits. It is connected to the anti-phase input terminal of the second differential amplifier circuit. The current mirror circuit 5 includes a PNP) transistor Q18. Q28 is connected so that the base current of the NPN transistor Q17 inserted in the second differential amplifier circuit described above becomes a reference current;
PNP) The collector of the transistor Q18 becomes the output terminal of the current mirror circuit 5. PNP ) transistor Q19 has an emitter connected to the output terminal of the current mirror circuit 5 described above, a base connected to the collector of Q14, and a collector connected to Q14.
Connected to 14 bases.

In this embodiment, a component different from the second embodiment is inserted between the collector of the output terminal Q18 of the current mirror circuit 5 and the base of the Q140 connected to the input terminal of the second differential amplifier circuit. The transistor Q19 is a PNP
) transistor Q18. This is to improve the current ratio accuracy of the current mirror circuit 5 composed of Q28, and the voltage EEV between the collector emitter of transistor 018 and Q28 is
ce are made equal, that is, transistors Q18. Q
The current error due to the early voltage effect of 28 is reduced.

Next, a fourth embodiment of the present invention will be described.

FIG. 4 is a circuit diagram for explaining a fourth embodiment of the present invention. This embodiment is based on the positive phase side input stage transistor Q of the first differential amplifier circuit 3 in the first embodiment shown in FIG.
A transistor Q31 (NPN) is connected between the transistor Q12 which is the collector load of the NPN transistor Q31, the emitter is the collector of Qll, the collector is the collector of Q12, and the base is the collector of Q12.
The difference is that it is connected to and inserted into the collector of No. 21.

In this embodiment, the different parts from the first embodiment, namely,
The NP, N) run transistor Q31 inserted between the input stage transistor Qll of the first differential amplifier circuit 3 and the transistor Q12 which is its collector load reduces the input offset voltage of the first differential amplifier circuit 3. This is to change the collector potential of transistor Qll to transistor Q21.
The base of transistor Q31 is always lower than the collector potential of
Keep the potential as low as the emitter potential, and
l 1. The input offset voltage of the first differential amplifier circuit caused by the 7-Lee voltage effect of Q21 is reduced.

Next, a fifth embodiment of the present invention will be described.

FIG. 5 is a circuit diagram for explaining a fifth embodiment of the present invention. This embodiment is based on the positive phase side input stage transistor Q of the first differential amplifier circuit 3 in the second embodiment shown in FIG.
An NPN (NPN) transistor Q31 is connected between the collector load of Qll and the transistor Q12, the emitter of which is the collector of Qll, the collector of Q12, and the base of the transistor Q12.
The difference is that it is connected to and inserted into the collector of No. 21.

This embodiment is an application of the fourth embodiment to the second embodiment, and reduces the error due to the input base current of the second differential amplifier circuit and the error due to the input offset voltage of the first differential amplifier circuit. This makes it possible to reduce errors.

Next, a sixth embodiment of the present invention will be described.

FIG. 6 is a circuit diagram for explaining a sixth embodiment of the present invention. This embodiment is based on the third embodiment shown in FIG.
A transistor Q31 (NPN) is connected between the transistor Q12 which is the collector load of the NPN transistor Q31, the emitter is the collector of Qll, the collector is the collector of Q12, and the base is the collector of Q12.
The difference is that it is connected to and inserted into the collector of No. 21.

This example is an application of the fourth example to the third example, and reduces the error due to the base current of the input stage transistor of the second differential amplifier circuit even more than the fifth example. This is what I did.

Next, a seventh embodiment of the present invention will be described.

FIG. 7 is a circuit diagram for explaining a seventh embodiment of the present invention. This embodiment is based on the positive phase side input stage transistor Q of the first differential amplifier circuit 3 in the first embodiment shown in FIG.
An NPN) run transistor Q31 is connected between ll and its collector load, the transistor Q12, the emitter is the collector of Qll, the collector is the collector of Q12, and the base is Q12.
22, the input stage transistor Q21 on the negative phase side, and the PNP as its collector load.
) NPN connected with a diode between transistor Q22
) The difference is that the transistors are inserted in the forward direction.

In this embodiment, the different parts from the first embodiment, namely,
Positive-phase side input stage transistor Ql of the first differential amplifier circuit 3
NPN transistor Q31 inserted between the input stage transistor Q21 on the negative phase side of the first differential amplifier circuit and the transistor Q22 as its collector load. The inserted transistor Q32 is connected to the first differential amplifier 1 [circuit 3
This is to reduce the input offset voltage of the transistor Qll, and the collector potential of the transistor Qll is set to approximately the same potential as the collector potential of the transistor Q21, that is, both potentials are set to be lower than the collector potential of the transistor Q22, which is the output voltage of the first differential amplifier circuit. The base-emitter potential drop is maintained at a lower potential by a step, thereby significantly reducing the input offset voltage of the first differential amplifier circuit caused by the Early voltage effect of the transistors Q11 and Q21.

Next, an eighth embodiment of the present invention will be described.

FIG. 8 is a circuit diagram for explaining an eighth embodiment of the present invention. This embodiment is based on the positive phase side input stage transistor Q of the first differential amplifier circuit 3 in the second embodiment shown in FIG.
An NPN transistor Q31 is connected between Qll and its collector load transistor Q12, the emitter is the collector of Qll, the collector is the collector of Q12, and the base is 0.
22, the input stage transistor Q21 on the negative phase side, and the PNP as its collector load.
) NPN connected with a diode between transistor Q22
) The difference is that the transistors are inserted in the forward direction.

This embodiment is an application of the seventh embodiment to the second embodiment, and reduces the error caused by the input base current of the second differential amplifier circuit and the error caused by the input offset voltage of the first differential amplifier circuit. This makes it possible to further reduce errors.

Next, a ninth embodiment of the present invention will be described.

9 is a circuit diagram for explaining a ninth embodiment of the present invention. This embodiment is the third embodiment shown in FIG.
Positive-phase side input stage transistor Ql of the first differential amplifier circuit 3
An NPN) run transistor Q31 is connected between the transistor Q12 which is the collector load of the NPN transistor Q31, the emitter is the collector of Qll, the collector is the collector of 012, and the base is the collector of Q2.
(NPN with a diode connected between the point connected and inserted to the collector of 2 and the negative phase side input stage transistor Q21 and the PNP transistor Q22 as its collector load)
The difference is that the Runcisor is inserted in the forward direction.

This embodiment is an application of the seventh embodiment to the embodiment shown in FIG. 3, and the error caused by the base current of the input stage transistor of the second differential amplifier circuit can be reduced even more than the eighth embodiment. It has been reduced.

〔Effect of the invention〕

As explained above, according to the present invention, by applying feedback directly to the negative phase input terminal of the first differential amplifier circuit from the output signal of the output terminal of the circuit, the input offset voltage of the 20th differential amplifier circuit is This has the effect of reducing errors in the output signal caused by. In addition, by adding a circuit that detects the input current of the positive-phase input terminal of the second differential amplifier circuit and a current mirror circuit that outputs a current equal to this, the positive-phase input terminal of the second differential amplifier circuit The error occurring in the output signal due to the input current of the current mirror circuit is significantly reduced, and the current accuracy of the current mirror circuit is significantly improved by the transistor inserted between this current mirror circuit and the positive phase input terminal of the second differential amplifier circuit. This has the effect of further enhancing the canceling effect of the input current flowing to the positive phase input terminal of the second differential amplifier circuit. Furthermore, by inserting a transistor between the positive-phase input stage transistor of the first differential amplifier circuit and its collector load transistor, the positive-phase input stage transistor and the negative-phase input stage transistor of the first differential amplifier circuit are By keeping the collector potentials in a constant relationship, the input offset voltage of the first differential amplifier circuit can be significantly reduced, and a diode can be connected between the anti-phase input stage transistor of the first differential amplifier circuit and its collector load transistor. By adding a connected transistor, the collector potentials of both the positive and negative input stage transistors of the first differential amplifier circuit can be made almost equal, and the output caused by the input offset voltage of the first differential amplifier circuit can be made almost equal. It becomes possible to further reduce signal errors.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram for explaining a first embodiment of the present invention, FIG. 2 is a circuit diagram for explaining a second embodiment of the present invention, and FIG. 3 is a circuit diagram for explaining a third embodiment of the present invention. A circuit diagram for explaining the embodiment, FIG. 4 is a circuit diagram for explaining the fourth embodiment of the present invention, and FIG. 5 is a circuit diagram for explaining the fifth embodiment of the present invention. FIG. 6 is a circuit diagram for explaining the sixth embodiment of the present invention, FIG. 7 is a circuit diagram for explaining the seventh embodiment of the present invention, and FIG. 8 is a circuit diagram for explaining the seventh embodiment of the present invention. FIG. 9 is a circuit diagram for explaining the ninth embodiment of the present invention, and FIGS. 10 and 11 are circuit diagrams for explaining the conventional example. 1... Signal input terminal, 2... Signal output terminal, 3... First differential amplifier circuit, 4...
...Second differential amplifier circuit, 5...Current mirror circuit, Qll, C21°Ql 3. Ql 4. C24
, Ql 6. Ql 7. C31゜C32・・・・・・N
PN) transistor, C12, C22°Ql 5. C25
, Ql 8. C28, Ql 9...PNP) transistor, IEEE, IEEE2. IEE3...
Constant current source, C1... Capacitor, VCc...
...High potential voltage source, VER...Low potential voltage source.

Claims (1)

[Claims] 1. Supplying an input signal to the positive phase input terminal of a first differential amplifier circuit, and charging a capacitor with the output signal of the first differential amplifier circuit via a first emitter follower circuit. Then, in a peak level detection circuit that inputs the charge of this capacitor to the positive phase input terminal of a second differential amplifier circuit, the output signal of the second differential amplifier circuit is input to the second emitter follower circuit. A peak level detection circuit characterized in that feedback is fed back to the opposite phase input terminals of the first and second differential amplifier circuits. 2. A first transistor having the same polarity as the input stage transistor is connected between the positive phase input side input stage transistor constituting the second differential amplifier circuit and the collector load, and
The peak level according to claim 1, further comprising a current mirror circuit which uses the base current of the transistor as a reference current source and feeds back the output current to the positive phase input terminal of the second differential amplifier circuit. detection circuit. 3. Connect the emitter of the second transistor having the opposite polarity to the input stage transistor of the second differential amplifier circuit to the output terminal of the current mirror circuit, and connect the base to the input stage transistor of the second differential amplifier circuit. 3. The peak level detection circuit according to claim 2, wherein the collector is connected to the positive phase input terminal of the second differential amplifier circuit. 4. An emitter of a third transistor having the same polarity as the input stage transistor is connected to the collector of the input stage transistor between the positive phase input side input stage transistor constituting the first differential amplifier circuit and the collector load; A collector is inserted in a manner connected to the collector load, and a base of the third transistor is connected to a collector of an input stage transistor on the negative phase input side of the first differential amplifier circuit. The peak level detection circuit according to the first, second or third range. 5. A fourth transistor having the same polarity as the third transistor is diode-connected between the collector of the negative-phase input stage transistor constituting the first differential amplifier circuit and the collector load of the transistor, and A peak level detection circuit according to claim 4, characterized in that the peak level detection circuit is inserted in a direction polarity.