JPH067417B2 - Reel motor control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reel scan motor VTR reel motor control circuit, and more particularly to a reel motor control circuit for reproducing a tape at a speed different from that during recording. The present invention relates to a motor control circuit.

[Prior Art] Conventionally, by changing the rotation speed of the reel motor while the tape is wound around the basic head drum of this type of reel motor control system, the tape speed for normal recording / reproduction is improved. , When the tape is run at several times the speed, the playback head cannot trace the track on the tape accurately. That is, the reproducing head crosses the tracks recorded on the tape by the two recording heads having different azimuth angles, and reproduces the tracks. In this case, due to the azimuth angle, the signal output to the reproducing head becomes like the head amplifier output signal in FIG.
That is, the head amplifier output signal increases when the recording head when recorded on the tape and the reproducing head when reproducing are the same, and conversely decreases when they are different. For tape running speed control, this head amplifier output signal is envelope-detected, and the result is further compared by a comparator to be a binarized signal, and the pulse number of this binarized signal is set to the high level section (or low level) of the head switch signal. Level section)
The number of pulses to be generated is controlled by controlling the number of pulses to be generated. Specifically, the reel motor is controlled so that the number of pulses becomes a target value. Here, the number l of generated pulses can be determined as follows.

Where n: integer υT (1): tape speed during forward 1 × speed playback νH (n): playback head speed during n × speed playback θA: tape-playhead mounting angle θm (n): n × speed playback Track angle recorded on the tape with respect to the tape direction Δθm (n): Track angle difference for 1 × speed reproduction at n × speed reproduction W: Tape width of effective recording area Tw: Pitch of recording track.

FIG. 10 is a graph showing an example of the relationship between the multiple of the tape running speed and the number of reproduced envelope waveforms when the tape recorded in the SP mode by the VHS of the VHS standard is reproduced at the double speed.

FIG. 6 is a block diagram of a control system realized by applying the conventional basic principle described above. FIG. 8 is a diagram showing a processing flow in FIG. The head amplifier output signal input from the terminal 18 is amplified by the amplifier 12, and then is envelope-detected by the envelope detection circuit 13 and is converted into a binary signal by comparing the envelope wave. On the other hand, the drum phase signal input from the terminal 19 is input to the head switch signal generation circuit 14 and outputs a head switch signal. The counter 15 receives the binarized signal output from the envelope detection circuit 13 as a clock signal and starts counting from the count value preset in the latch register 25 by the processor 1 including the central processing unit 2, ROM 3 and RAM 4. The clock is counted between the edges of the switch signal, the data is latched in the latch register 16, and the interruption is performed (steps 200 and 201 in FIG. 8). Processor 1
Takes in the contents of the latch register 16 via the bus 17 and performs data processing by the addition and subtraction calculation processing (step 2
02) and then input to the D / A converter 5 (step 203) and converted to an analog value, which is then output to the terminal 22 as an external reel motor output signal by the sample hold circuit 6 and the value of the latch register 16 is changed. The number of rotations of the reel motor is controlled so that it is always constant.

On the other hand, the control of the drum motor speed was performed as follows. When the speed information signal of the drum motor input from the terminal 20 is input to the circuit 11 which requests an interrupt to the processor 1 (step 200), at the same time,
It is input to one of the latch register group circuits 10 for latching the value at that moment of the free-running 8 to 16-bit binary type free-run counter 9 (step 2
11), the value of the latch register group circuit 10 is taken into the processor 1 via the bus 17, and the error value expressed by the equation (7) is obtained. Is calculated (step 212), and this error value is processed (step 213) by addition and subtraction integration or the like, and then, through the D / A converter 5 (step 214), in the sample hold 7, in the motor control output signal. Is output to the terminal 23 and the speed is controlled so that the error signal becomes zero.

Further, regarding the phase control of the drum, the phase information signal of the drum input from the terminal 19 is a signal obtained by logically ORing the 30 Hz reference period signal input from the terminal 21 and the OR 28
When input to the circuit 11 which requests an interrupt to the processor 1 (step 200), at the same time, the instantaneous value of the free running counter 9 is latched by one of the latch register group circuits 10 (step 22).
1) Taken into processor 1 via bus 17
The error value shown in (8) is calculated (step 222), Further, this error value is processed (step 223) by adding / subtracting integration as in the drum speed control, and then D / A
Through the converter 5 (step 224), the sample and hold 8 outputs a motor control output signal to the terminal 24 and performs phase control so that the error signal becomes zero.

In particular, the counter 15 shown in FIG. 6 has a circuit diagram shown in FIG. An edge detection circuit that inputs the output of the head switch signal generation circuit 14 from a terminal 51 and detects the etching of this signal with a resolution of a system clock (0.125 to 2 μs), that is, a D-type flip-flop (hereinafter abbreviated as D-FF) 56, 57 and exclusive OR 59
(Hereinafter referred to as EXOR), the output of the EXOR 59 is the interrupt request signal to the processor 1 and the latch register 16
Strobe signal and a reset set flip-flop (hereinafter abbreviated as RS-FF) 60 are input to the reset, while the output of the 1-bit shift register D-FF65 is input to the set of RS-FF60.
The FF 60 controls the presetting (7) of the 7-bit counter 63. Further, a binarized signal obtained by envelope-detecting and comparing the head amplifier output signal in the envelope detection circuit 13 is input to the terminal 54, a synchronizing circuit for synchronizing the ▲ ▼ signal of the counter 63 and the system clock signal, that is, the inverter 61. And D-FF 58 and NOR 62, and counts the pulses input to the terminal 54. Terminal 52 is a system clock input terminal and terminal 53
Is a system reset terminal.

For example, when 100 times speed forward reel servo is performed in the SP mode of the VHS standard VTR, the number of envelope waveforms is 50 from FIG.
The preset value of is 50. When "0EH" is stored in the latch register 25 shown in FIG. 6, the counter 63 counts exactly 50 between the edges of the head switching signal when the servo is sufficiently applied and becomes stable. Has the value "00
H "will be latched.

When the number of magnetized drums is 20 and the clock of the free-run counter 9 is 2 μs, the value of the equation (7) Becomes

[Problems to be solved by the invention]

In the conventional reel motor control described above, the number of envelope waveforms varies between edges (1/60) of the head switch signal.
SEC), even at 200x speed, 140 pieces,
The resolution was only 1 / (60 * 140) Sec = 120 μs, which was not sufficient as compared with the resolution for normal reproduction (clock of free-run counter: 0.125 to 1 μs). Furthermore, this means that the resolution deteriorates as the double-speed playback becomes slower.Therefore, in the reel motor control, when moving from the stopped state to the high-speed double-speed playback, the low-speed playback → medium-speed playback is usually performed. When moving from playback to high-speed playback and several times of double-speed playback, the low resolution during low-speed playback is particularly noticeable.
When performing fast rewind, there was a problem in terms of accuracy.

It is an object of the present invention to provide a reel motor control circuit which has a resolution equivalent to that of a drum motor control and is highly stable during variable speed reproduction.

[Means for solving problems]

The reel motor control circuit of the present invention includes an interrupt processing circuit that issues an interrupt request to a processor in response to an external input signal, and a register that latches the value of a first free-running counter circuit simultaneously with the input of the external input signal. A reel motor control circuit in a magnetic tape recording / reproducing apparatus that has a group, and the processor performs a certain process on the value of the latch register group via a bus and then outputs a motor control signal via a D / A converter circuit. In the above, the output signal of the tape head amplifier is envelope-detected, the envelope binarization means for binarizing the detected signal, the second counter for counting the binarized signal, and the input drum phase information signal Means for generating a head switch signal from the Means for generating a count start pulse signal of the counter, and the carry signal and the count start pulse signal output after the second counter has counted a constant value are used as interrupt signals of the interrupt processing circuit. It is characterized in that the value of the free-run counter at the time of inputting a signal is latched in the latch register group, the latched value is data-processed via a processor, and is output as a reel motor control signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing a processing flow according to the present invention. The basic principle of reel motor control, drum speed control, and phase control are the same as those of the conventional method, and therefore a description thereof is omitted. The feature of the present invention is that the head amplifier output signal is supplied to the terminal 18
Input, amplified by the amplifier 12, envelope-detected by the envelope detection circuit 13 and binarized, and the counter 26 receives the binarized signal, counts from the value of the latch register 25, and starts the counting. It is performed at the edge portion of the head switch signal generated in the head switch signal generation circuit 14 from the drum phase information signal input from 19. The output of the counter 26 is characterized in that a logical sum of the count start signal and the carry signal output for full counting of the counter is calculated and input to the interrupt processing circuit 11 as an interrupt signal.

FIG. 4 is a block section showing an embodiment of the counter 26. The output of the head switch signal generation circuit 14 is connected to terminal 5
Input from 1 and detect the edge of this signal at the resolution of the system clock (0.125 to 2 μs), that is, the edge detection circuit, that is, D-FF 56, 57 and EXOR59, the output of EXOR59 is input to the set of RS-FF60. The RS-FF 60 controls the preset (LOAD signal) of the counter of the 7-bit counter 63. Further, the head amplifier output signal is envelope-detected in the envelope detection circuit 13 and the binarized signal obtained by the comparison is input to the terminal 54 to synchronize the LODA signal of the counter 63 with the system clock signal. , Inverter 61, D-FF58 and NO
It is composed of R62 and is adapted to count the pulses of the terminal 54. The carry signal of the counter 63 is used as the reset signal of the RS-FF 60, and the carry signal (NOR6) is added to the carry signal and the output of the EXOR 59.
4) The output signal is output to the terminal 55 and
It is input to the interrupt processing circuit 11 as an interrupt signal (see FIG. 2).

Regarding the control method, the drum speed and phase control (steps 111 to 114, 121 to 124) are exactly the same as those of the conventional one shown in FIGS. 6 and 8. Regarding the control of the reel motor, when the output signal of the counter 26 is input to the circuit 11 for requesting the interrupt to the processor 1 (step 100), at the same time, the free running counter 9 of the binary type free-running counter 9 is running. Latch the instantaneous value in one of the latch register group circuits 10 (step 10
1), this value is taken into the processor 1 via the bus 17, and an error value is calculated in the same manner as in the above equation (7) (step 102), and this error value is processed by addition and subtraction integration (step 102). After 103), it is output to the terminal 22 as a motor control output signal in the sample hold 6 via the D / A converter 5 (step 104), and control is performed so that the error value becomes zero. For example, VHS
No. 10 in 100x normal speed playback in standard SP mode
From the figure, if the number of envelope waveforms is 50, and the carry of the counter 63 counts this envelope wave and sets the carry output to the 32nd one, the target value of the previous equation (7) is (However, the clock of the free-run counter 9 is set to 2 μs).

FIG. 5 is a block diagram showing a second embodiment of the counter 26 in FIG. This embodiment is characterized in that the data preset of the counter 63 can be performed several times between the edges of the head switch signal. That is, the counter 6
This is carried out by taking the exclusive OR of the carry signal of No. 3 and the Q signal of RS-FF60.

As a result, in the embodiment of FIG. 4, the error value was obtained only once during the etching of the head switching signal, whereas in the second embodiment, the counter 63 was used.
By setting the preset value of, that is, the value of the latch register 25 appropriately, an error value can be obtained several times between edges, and it is possible to perform control with adaptability to sudden changes in the motor. There is.

〔The invention's effect〕

As described above, the reel motor control circuit of the present invention is similar to the circuit conventionally used for drum motor control, that is, the interrupt processing circuit 11, the free-run counter 9, the latch register group circuit 10 in FIG. , Etc., the resolution up to the clock of the free-run counter (0.12
It has become possible to improve the accuracy up to 5 to 2 μs. As a result, high-accuracy and high-speed access becomes possible during sequential access to the tape by high-speed fast forward and fast rewind, and the effect is significant.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the present invention, FIG. 3 is a diagram showing a processing flow of the present invention, and FIG. First of the counter 26
FIG. 5 is a block diagram showing a second embodiment of the counter 26 shown in FIG. 1, FIG. 6 is a block diagram showing a conventional embodiment, and FIGS. FIG. 9 is a block diagram showing an example of a conventional counter 15, and FIG. 10 is a graph showing an example of the relationship between the tape running speed and the number of envelope waveforms. 1 is a processor, 2 is a central processing unit, 3 is a ROM,
4 is a RAM, 5 is a D / A converter, 6, 7 and 8 are sample and hold circuits, 9 is a free-run counter, 10 is a latch register group, 11 is an interrupt processing circuit, 12 is an amplifier, 13 is envelope detection and binary. Circuit, 14 a head switch signal generating circuit, 15 a counter, 16 a latch register, 17 a bus, 18 a head amplifier signal input terminal, 19 a drum phase information signal input terminal, 20 a drum speed information signal input terminal, 21 is a 30 Hz reference period signal input terminal, 22, 23 and 24 are motor control signal output terminals, 25 is a latch register, 26 is a counter, 51 is a head switch signal input terminal, 52 is a system clock input terminal, and 53 is a system reset terminal. , 54 is an envelope wave binarization signal input terminal, 55 is an interrupt request signal output terminal, 56, 57 58,65 is DFF, 59,66
Is EXOR, 60 is RS-FF, 61 is an inverter, 6
2 is NOR, 63 is counter with preset, 64 is OR
Circuit.

Claims (1)

[Claims] 1. A processor having an interrupt processing circuit for issuing an interrupt request to a processor in response to an external input signal and a register group for latching the value of a first free running counter circuit simultaneously with the input of the external input signal. Then, in the reel motor control circuit in the magnetic tape recording / reproducing apparatus for outputting the motor control signal through the D / A converter circuit after performing a certain process on the value of the latch register group through the bus, the tape head Envelope detection of the output signal of the amplifier, and an envelope binarization means for binarizing the detection signal, a second counter for counting the binarized signal, and a head switch signal from the input drum phase information signal. Means for generating
A carry which is provided with means for detecting an edge of the head switch signal and generating a count start pulse signal of the second counter, and which is output after the second counter has counted from a value given in advance by the processor. A signal and the count start pulse signal are used as an interrupt signal of the interrupt processing circuit, the value of the free-run counter at the time of input of each signal is latched in the latch register group, and the latch value is passed through the processor. A reel motor control circuit, which processes data and outputs as a reel motor control signal.