JPH01317257A - Tape feed controller - Google Patents

Abstract

PURPOSE:To satisfactorily shorten the interruption processing time by decelerating the drive of a motor in the case it is detected with measurement of the FG pulse cycle that the tape speed is controller to a higher level as the shortage of the arithmetic processing time is increased. CONSTITUTION:A capstan motor 32 is prepared and the rotation detecting pulse (FG pulse) received from a rotation detector (frequency generator) 34 is inputted to a microcomputer 30. The microcomputer 30 outputs a control command of the motor 32 to a motor drive circuit 31 based on a command given from a system control circuit 33. In the case such a high speed that causes the shortage of the arithmetic processing time is detected by the speed information given from a speed detecting means 34, the multiplying process of the FG pulse is stopped and the filter arithmetic is omitted. Then a motor control command proportional to the speed error information or a deceleration command for a fixed degree is outputted to the circuit 31. The speed control is performs so as to perform the filter arithmetic again when the motor 32 is decelerated down to an arithmetic process enable state. As a result, the interruption processing time is extremely shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to tape feeding control in a tape device such as a VTR, and more particularly to a method of controlling tape feeding using a microcomputer.

2. Description of the Related Art As a method of controlling tape feeding using a microcomputer, there is a method as disclosed in, for example, Japanese Unexamined Patent Publication No. 178762/1983.

That is, as shown in FIG. 3, the microcomputer 30 performs
Controls tape feed speed. Its configuration is such that a rotation detection pulse (hereinafter referred to as FG pulse) from a rotation detector (for example, a frequency generator) 34 attached to a capstan motor 32 that feeds the tape is input to a microcomputer 30. is for outputting a motor control command to the drive circuit 31 for control. The microcomputer 30 uses the FG pulse as an interrupt input, and detects the speed at the time interval of the interrupt pulse. The speed error information obtained in this manner is subjected to filter processing to improve the performance of the control system, and the results are sent to the motor drive circuit 31.

Figure 2 shows its configuration. A cyclic counter 21 counts clock pulses that are sufficiently fast with respect to the FG pulse.
Count time. When the FG pulse comes in, the value of the cyclic counter 21 is latched into the latch register 24 at the edge of the change. At the same time, a signal requesting interrupt processing is generated to the CPU 20.

The ROM 27 is for storing processing programs of the CPU 20, and the RAM 27 is for storing processing results.

FIG. 6 is a flowchart showing the interrupt processing of the CPU 20. First, in process 60, the CPU 20 calculates the difference (interrupt cycle) between the value of the latch register 20 and the value of the memory B of the RAM 27. Next, in step 61, the difference between this difference and the reference value (memory C) is determined, and the result is stored in memory A.

This is the speed error. It is assumed that a reference value is stored in memory C in advance. Next, the process proceeds to step 62, where the value of the latch register 20 is stored in the memory B. Next, in process 63, in order to improve the performance of the control system, a digital filter calculation is performed to determine the motor control amount, and the result is sent to the D/A converter 28. Since the output of the D/A converter 28 is connected to the drive circuit 31 of the capstan motor 32, the signal output from the D/A converter 28 becomes a drive command for the capstan motor 32.

FIG. 4 is a diagram showing an example of the configuration of a digital filter. Here, a speed error signal is input from the input terminal 40,
The adder 41 and the delay device 42 perform cumulative addition. The delay time of the delay device 42 is set to the period of the FG pulse. Signals before and after the delay device 42 are extracted, multiplied by a fixed multiplier A or B, and an adder 45 calculates the difference. The result 46 is the output of the filter. FIG. 5 is a flowchart showing the processing of this filter.

First, in process 50, the speed error value and the cumulative addition value up to now are added, and the result is stored in the memo UD. The memo IJDO value becomes the updated cumulative addition value. Next, the process proceeds to step 51, where the value in the memory D is multiplied by the coefficient A, the cumulative addition value is multiplied by the coefficient B, and the difference between the respective multiplication results is determined. Finally, in step 52, the value of the memo IJD is stored as a cumulative addition value. The difference value of the multiplication results is the output value of the filter. Since the filter calculation uses multiplication at least twice, it takes a relatively long calculation time, and it is necessary to prevent the calculation time delay from having an adverse effect on the control system.

In addition to playback in which the tape is run at the same speed as when it was recorded, VTRs also include slow-motion playback and fast-forward playback as special playbacks. To perform fast-forward playback, the rotational speed of the capstan motor must be increased. Increasing the rotation of the capstan motor means increasing the frequency of the FG pulse, and if this continues, the microcomputer will have to interrupt processing very frequently, and sometimes the next command will be delayed before the motor drive command can be calculated. An FG pulse may be input. To avoid this situation, set the FG pulse in advance.
A method is used to divide the frequency and input it to the control circuit. Frequency division can be realized by the CPU 20 controlling the variable frequency divider 22 according to the mode, as shown in FIG.

For example, to realize reproduction at N times speed, the CPU 20 issues a command to the variable frequency divider 22 to divide the frequency by 1/N, and performs recording or
For double-speed playback, all you have to do is issue a command to the variable frequency divider to not divide the frequency. System control circuit 3 determines whether or not to perform high-speed playback.
3. Receive orders and make decisions. Furthermore, when performing low-speed reproduction, the period of the FG pulse becomes long, which may make stable speed control difficult. For this reason, as shown in FIG. 2, an EX-OR circuit 23 is used to invert the FG times signal each time an interrupt is accepted, multiply the interrupt frequency, and halve the period for obtaining the FG speed error. etc. are taken.

Let us consider a case where tape feed control is switched from high-speed control to low-speed control in a method that overcomes the problems that the invention aims to solve. That is, based on the system control command, the CPU switches from issuing a 1/N frequency division command to the variable frequency divider 22 to a command to stop frequency division.

In this way, even if the target values of the FG pulse periods from the perspective of the CPU 20 are the same, it is possible to switch from N times speed feeding to single speed feeding. When controlling the speed even further, a method may be used in which the above-mentioned EX-OR circuit 23 is used to multiply the actual FG frequency.

However, when controlling in this manner, it has been found that there are the following problems. In other words, when performing high-speed control, the variable frequency divider 22 is used to convert the pulse input to the CPU 20 to -11=1/N, and convert it to the same frequency as 1x speed. The FG pulse frequency is multiplied by N. Therefore, even if the variable frequency divider 22 is switched so as not to pass through, and a deceleration command can be issued, the feed motor 32 does not respond immediately, so the frequency of the FG pulse is set to a value close to N times. It becomes.

At this time, interrupt requests are frequently generated to the CPU 20, making it impossible for the CPU 20 to complete processing within the pulse cycle.

When switching to an even lower speed, the EX-OR circuit 23 is used and the interrupt period is doubled, so the actual interrupt frequency is multiplied by 2*N, making control even more difficult. In particular, when multiplying the interrupt frequency, in order to accurately detect the period, the timing of inverting the FG pulse edge must not be delayed from the arrival of the next edge. If there is a delay, the inverted timing will be erroneously detected as the FG pulse edge timing.

In order to prevent such a situation from occurring, when switching from high-speed playback to low-speed playback, a method may be considered in which the speed command given by the system control circuit 33 is gradually switched from high speed to low speed. For example, the speed is gradually lowered from N times speed playback to (N-1) times speed playback, (N-2) times speed playback, and so on. However, in this case, it is obvious that the drawback is that it takes time to reach the final goal of slowing down.

Means for Solving the Problems In the present invention, in order to overcome the conventional drawbacks, when it is detected that the speed information by the speed detection means is so high that the calculation processing time is insufficient, the FG pulse is Stop the multiplication process, omit the filter calculation, output a motor control command proportional to the speed error information or a fixed amount of deceleration command to the motor drive circuit, and once the speed is reduced to a state where calculation processing is possible, perform the filter calculation again. Perform speed control.

The active CPU measures the FG pulse period as an interrupt process, compares it with a reference value, and performs a speed comparison calculation. the result,
If it is detected that the speed is such a high-speed transfer control that the calculation processing time is insufficient, the multiplication process of the FG pulse is stopped, the filter calculation is omitted, and the motor control command is set proportional to the speed error information or constant. A deceleration command of the amount is output to the motor drive circuit, and when the motor is decelerated to a state where calculation processing is possible, speed control is performed again to perform filter calculation. By stopping the multiplication process of the FG pulse, the interrupt frequency of the FG pulse is halved, and furthermore, by omitting the filter process, the interrupt processing time is significantly reduced. Therefore, the interrupt processing can be completed before the next FG pulse arrives, and normal speed error detection can always be performed.

Embodiment An embodiment of the present invention will be described based on the drawings. FIG. 2 is a circuit block diagram showing a configuration example of the present invention, and the hardware configuration is the same as that of the conventional example.

That is, a cyclic counter 21 that counts high-speed clock pulses is provided to repeatedly count the clock pulses. Variable frequency dividing circuit 22 for FG pulse of capstan motor 32
The signal is then input to the latch register 24 through the EX-OR circuit 23 for multiplication.

The latch register 24 latches the count value of the cyclic counter 21 at the edge of the output signal of the EX-OR circuit 23. At the same time, at the edge of the output signal of the EX-OR circuit 23, a request is made to the CPU 20 for interrupt processing. The CPU 20 determines the rotational speed of the capstan motor 32 as an interrupt process, calculates a motor drive command value, and sends the D/A converter 2
Output the value to 8. The output signal of the D/A converter 28 becomes a drive command for the capstan motor 32 via a capstan motor drive circuit 31. The frequency division ratio of the variable frequency divider circuit 22 and the control of the EX-OR circuit 23 are controlled by software by the CPU 20.

FIG. 1 is a flowchart showing the contents of interrupt processing by the CPU 20. The CPU 20 first performs processing 1 as interrupt processing.
As shown in FIG. 2, the difference between the value in the latch register 24 and the value in memory B is determined, and that value is written into memory A. Next, proceed to process 2, find the difference between the value in memory A and the value in memory C, and store the result in memory A. It is assumed that the value of the reference period is stored in memory C in advance. Next, as shown in process 3, it is checked whether the current control mode is the low speed mode. If the mode is low speed mode, the process proceeds to process 4, and if the mode is high speed mode, the process proceeds to process 13.

Below, the case of low speed mode will be explained first. In process 4, it is determined based on a flag whether multiplication processing is currently being performed. If multiplication processing is being performed, the process proceeds to process 7; otherwise, the process proceeds to process 5. In process 7, it is checked whether the value in memory A is smaller than a constant value N2. If it is smaller, proceed to process 8; otherwise, proceed to process 9. In process 8, the flag for performing multiplication processing is cleared. Then, the process proceeds to process 9.

Similarly, in process 5, it is checked whether the value of memo IJA is smaller than the constant value N1, and if it is, the process proceeds to process 9; otherwise, the process proceeds to process 9 via process 6. In process 6, a flag for multiplication processing is set.

In process 9, it is checked whether the flag for multiplication processing is set. If it is set, the process proceeds to process I6-10; if not, the process proceeds to process 11. In process 10, a digital filter calculation is performed, the calculation result is output to the D/A converter 28, and the capstan motor 32 is controlled. Next, the process proceeds to step 12, where the value of the polarity switching register 25 is inverted. As a result, the output of the EX-OR circuit 23 is inverted, and the FG pulse is multiplied. Next, proceed to process 16, and latch register 2
The value of 4 is stored in the memo UB and the interrupt processing ends. On the other hand, when proceeding to process 11, the value proportional to the speed error (stored in memo IJA) is directly output to the D/A converter 28 without performing the filter calculation.
Finally, through process 16, the interrupt process ends.

On the other hand, in the high speed mode, the process proceeds to step 13, where it is first checked whether the speed error value (memo IJA) is smaller than the constant value N3. If it is smaller, the process proceeds to process 15; otherwise, the process proceeds to process 14. In process 14, a filter calculation is performed using the velocity error value, and after outputting the calculation result to the D/A converter 28, the process proceeds to process 16, and the interrupt process is ended. In addition, when proceeding to process 15, a value proportional to the speed error (stored in memory A) is directly output to the D/A converter 28 without performing the filter calculation, and the final process is 16, the interrupt processing ends.

Next, the constant value Nl, N2°N3 used in the above processing
．． Explain the relationship between First, N1 is a threshold value indicating permission for multiplication processing in low-speed mode. Also N
2 is a threshold value indicating whether or not multiplication processing is prohibited. Further, N3 is a threshold value for determining whether to omit filter processing in the high-speed mode. When ε, the speed corresponding to N1 must be slower than the speed corresponding to N2. This is because if the speed corresponding to N1 is fast, then N
The multiplication process can be started when the speed becomes slower than the speed corresponding to N2, but since it is still faster than the speed corresponding to N2,
This is because it also becomes a state in which multiplication processing is prohibited, resulting in a contradiction. The value of N1 is determined based on the cycle in which interrupt processing can be performed sufficiently even with multiplication processing, taking into account the interrupt processing time. Similarly, the value of N3 can be determined based on the interrupt processing period.

As described in detail, the present invention solves the problem that is difficult with conventional program processing, because when the frequency division ratio of the variable frequency divider is switched to 1, many FG pulses are input, and the processing time of the microcomputer is insufficient. This technology solves the problem of speed reduction, and has great effects in that it can speed up deceleration and does not require the addition of new circuits.

In addition, in this embodiment, as a method of decelerating the motor,
The D/A converter 28 calculates a value proportional to the speed error (stored in memory A) without performing any filter calculation.
Although the explanation has been given on the method of directly outputting the signal to the vehicle, there is also a method of decelerating the vehicle using a fixed deceleration command, which can achieve the same effect.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an interrupt processing procedure in an embodiment of the present invention, FIG. 2 is a block diagram of a microcomputer in an embodiment of the present invention, FIG. 3 is a block diagram of a control system in the same embodiment, and FIG. FIG. 4 is a block diagram of the digital filter in the same embodiment, FIG. 5 is a flowchart showing the calculation procedure of the digital filter, and FIG. 6 is a flowchart showing the interrupt processing procedure in the conventional example. 20...CPU121...Cyclic counter, 22...
・Variable frequency divider, 23...EX-OR circuit, 24...
Latch register, 2G...Polarity switching register, 2
6...Program memory, 27...Data memory,
28...D/A converter, 30...Microcomputer, 31...Drive circuit, 32...Capstan motor, 34...Frequency generator. Name of agent Patent attorney Toshio Nakao 1 person Figure 2 Figure 3 Figure 4 Figure Otsu 1 Figure 5 1R = - Hibiki N Figure 6 0 shout] "-Go-lens. -" -ReA −7 ■′ ro177;Harukaτ− ■

Claims (6)

[Claims] (1) A device that feeds and moves a tape by the rotational power of a motor, which includes means for executing arithmetic control according to a program, storage means for storing the arithmetic control results of the arithmetic control means, and counting means for repeatedly counting clock pulses. ,
means for variably frequency-dividing the rotation pulse signal of the motor or the rotation pulse signal of the rotating shaft by the calculation control means;
Means for requesting interrupt processing to the arithmetic control means by the output of the variable frequency dividing means; means for latching the count result of the repeat counting means by the output of the variable frequency divider; The arithmetic control means includes a means for converting into an analog signal and a means for driving a motor using the analog signal, and the arithmetic control means performs the interrupt processing by converting the latch result of the latch means and the latch result of the latch means when the previous interrupt occurred. A difference with the latch result is determined as a first difference, a second difference is determined by subtracting a reference value from the first difference, and a control command for the motor is determined based on a value based on the second difference. is calculated and output to the analog signal conversion means, and during the interrupt processing, the second difference value becomes the first difference value.
If the second difference value is larger than the first threshold value, a filter calculation is performed using the second difference value, the calculation result is output to the analog signal conversion means, and the second difference value is set to the first threshold value. When the difference is smaller than , the second difference value or a constant value is outputted to the analog signal converting means. (2) A device that feeds and moves a tape by the rotational power of a motor, comprising means for executing arithmetic control according to a program, a storage means for storing arithmetic control results of the arithmetic control means, and a counting means for repeatedly counting clock pulses. ,
Exclusive OR operation means and first and second registers controlled by operation control means are provided, and the pulse signal related to the rotation of the motor and the output of the first register are subjected to the exclusive OR operation. means for requesting interrupt processing from the arithmetic control means based on the output of the exclusive OR operation means; and means for latching the count result of the repeat counting means using the output of the exclusive OR operation means. and means for converting the calculation result of the calculation control means into an analog signal, and means for driving the motor using the analog signal, and the calculation control means is configured to latch the latch of the latch means as the interrupt processing. The difference between the result and the latch result of the latch means when the previous interrupt occurred is determined as a first difference, and a second difference is determined by subtracting a reference value from the first difference. Based on the value based on the difference, a control command for the motor is calculated and outputted to the analog signal converting means.
If the content of the register indicates that the first register is used, and the second difference value is greater than the first threshold, the value of the first register is changed to and performing a filter operation using the second difference value, outputting the operation result to the analog signal converting means, and the contents of the second register using the first register. When the second difference value is smaller than the first threshold value, the second difference value is output to the analog signal conversion means, and the second difference value is output to the analog signal conversion means, and The contents of the first
, and the content of the second register indicates that the first register is not used, and the second difference is If the value of When the second difference value is smaller than the first threshold, Outputting the second difference value or a constant value to the analog signal converting means, and performing a process of rewriting the contents of the second register to contents indicating a state in which the first register is not used. Characteristic tape feed control device. (3) The rotational pulse frequency corresponding to the first threshold is
3. The tape feeding control device according to claim 2, wherein the frequency is not higher than a rotation pulse frequency corresponding to a threshold value of . (4) Providing means for variably frequency-dividing a pulse signal related to the rotation of the motor by an arithmetic control means, and using the output of the variable frequency dividing means and the output of the first register as inputs to the exclusive OR operation means. The tape feed control device according to claim 2 or 3, characterized in that: (5) Providing means for variably frequency-dividing the pulse signal by the arithmetic control means, using the output of the exclusive OR arithmetic means as an input to the variable frequency dividing means, and interrupting the arithmetic control means by the output of the variable frequency dividing means. 4. The tape feeding control device according to claim 2, further comprising a step of requesting processing and latching the count result of the clock pulse counting means based on the output of the variable frequency dividing means. (6) When the frequency division ratio in the variable frequency dividing means is not 1, the value of the first register is fixed, and when the value of the second difference is smaller than the third threshold value, the value of the second difference is A filter calculation is performed using the value, and the calculation result is output to the analog signal conversion means, and if it is larger than the third threshold value, the second difference value or a constant deceleration command value is converted to the analog signal conversion means. 6. The tape feed control device according to claim 4, wherein the tape feed control device outputs the information to a means.