JPH0831060A - Phase control servo circuit for rotating body and vtr - Google Patents

Abstract

PURPOSE:To reset a software-wise constituted frequency dividing counter without interrupting by resetting the frequency dividing counter with a pulse signal to be positioned in a prescribed reference time at the time of nonoperation of phase control. CONSTITUTION:An output of a control (CTL) head 19 for regenerating a CTL signal is supplied via a terminal 12 to a servo IC 1. The center of PWM virtual output waveform to be formed in a phase control system is specified by a CPU 8 based on a counting output of a free running counter 3, and also so far as a nonoperation time of the phase control system immediately after a changeover to a search mode, the software-wise constituted frequency dividing counter 9 is reset by the pulse signal positioned in the prescribed reference time. In this case, the prescribed reference time is settled based on a prescribed output of the counter 3 which operates with a clock (CLK) inputted through a terminal 2. Consequently, the frequency dividing counter 9 can be reset without, performing interrupting processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotary phase control servo circuit and a VTR.

[0002]

2. Description of the Related Art FIG. 5 shows a circuit of a capstan servo among conventional digital servos in a VTR. This circuit consists of a speed control system and a phase control system. The speed control system has a speed system counter 71, a capture register 72, a processing circuit 73, a PWM circuit 74, and a low pass filter 75. The speed system counter 71 counts the clock CLK for free running, and the capture 72 latches the count output with a CFG pulse.

The CFG pulse is generated in association with the rotation of the capstan motor 92, amplified by the amplifier 93, and then supplied to the capture 72. The output of the capture 72 is processed by the processing circuit 73 and output as a PWM signal by the PWM circuit 74. This PWM signal is a low pass filter 7
It is smoothed by 5 and is given to the motor drive circuit 91 via the adder 90 as a speed control signal.

On the other hand, the phase control system has a phase system counter 81 which counts the clock CLK for free running, and a capture 82 which latches its output with a control pulse CTL reproduced from a magnetic tape through a CTL head.
And a processing circuit 83 for processing the output of the capture 82,
It is composed of a PWM circuit 84 and a low-pass filter 85 for smoothing the PWM signal.

The output (phase control signal) of the low-pass filter 85 is added by the adder 90 to the control signal of the speed control system described above, and the result is given to the motor drive circuit 91. The output of the motor drive circuit 91 is given to the motor 92 to control the speed and phase of the motor 92.

By the way, in the search mode, the tape speed (therefore, the speed of the capstan motor 92) is multiplied by 5 so that the search is carried out. Therefore, the control pulse CTL is applied to the terminal 94 with a pulse of 5 times the normal number. become.

Since it is difficult to control the phase by using all of these pulses, the frequency is divided into ⅕ by the frequency divider 86 so that the same phase control operation as in the normal reproduction mode is performed. In this case, as shown in FIG. 6, the frequency divider 86 is reset at the center A of the PWM virtual output waveform of the phase control system, and then the CTL pulse is counted.

When the mode is switched to the search mode, the speed does not increase to 5 times immediately. Therefore, the phase control system is not operated immediately after switching and the motor 92 is controlled only by the speed control system. When the speed becomes close to 5 times, for example, a signal is given from the speed processing circuit 73 to the phase processing circuit 83, and the phase control system also operates. By the way, the frequency divider 86 of the phase control system must be reset periodically even when the phase control system is inactive. This is done by using the output of, for example, a timer.

[0009]

Recently, in the VTR, as shown in FIG.
In place of the digital servo as described above, a microcomputer has been used to perform much of the servo control by software. In this way, there is an advantage that the hardware configuration can be simplified by introducing the software processing.

However, if the method shown in FIG. 5 is used as it is in software, the following problems occur in the phase control system. That is, although the frequency divider 86 is also configured by software, in that case, the frequency divider 86 is reset at the center A of the virtual PWM output waveform (a) of the phase control system as shown in FIG. 6 (b) shows a CTL pulse], the CPU monitors the output of the free-running counter 81 to identify its center A, and an interrupt is generated there to reset the frequency divider. However, in this way, one extra interrupt system is required in terms of hardware.

Moreover, when an interrupt is issued, the CPU saves the internal data to the stack, then processes the interrupt, and when the interrupt processing is completed, restores the saved data from the stack to the original. Since the normal processing is performed, it becomes a large-scale processing and the software load becomes large.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a phase control servo circuit which can be reset without interrupting a frequency dividing counter for dividing a control pulse. And

[0013]

In order to achieve the above object, according to the present invention, in a phase control servo circuit for a rotating body having a normal speed mode and an n (n is a natural number of 2 or more) multiple speed mode, the speed of the rotating body is increased. And a frequency dividing counter that divides the pulse signal used for phase control of the rotating body in the n-fold speed mode so as to have the same condition as in the normal operation, is configured by software with a microcomputer, and is switched to the n-fold speed mode. After that, the phase control system is deactivated until the speed reaches n times, and when the frequency division counter counts the pulse signals, the frequency division counter is reset by a pulse signal located within a predetermined reference time. I have to. In this case, the predetermined reference time is determined on the basis of a predetermined output of a free running counter operated by a clock.

Further, the VTR of the present invention has a search mode, and has a frequency dividing counter for dividing a control pulse obtained from a magnetic recording tape through a control signal reproducing head, and a free running counter for counting a clock. A capture register for latching the output of the free running counter with the output of the frequency dividing counter, a CPU for calculating the output of the capture register and outputting a phase control signal, and means for guiding the phase control signal to a capstan motor And the frequency dividing counter is configured by software, and the CPU obtains the frequency dividing counter based on the output of the free running counter when the phase control system is disabled in the search mode. If a control signal is input within the reference time, the control signal In so that resetting.

[0015]

According to the phase control servo circuit for such a rotating body, when the mode is switched to the n-fold speed mode, the n-fold speed is not immediately achieved, and it takes some time due to inertia of the rotating body. During that time, the phase control system is placed in the inactive state, but when the speed becomes n times, the frequency division counter is reset so that the frequency division counter does not operate randomly, even if the phase control system is in the inactive state. It is necessary to perform this reset, for example, by using a pulse signal existing within the reference time obtained based on the predetermined output of the free running counter, so that the correct frequency division operation is executed and the phase control system enters the operating state. Then, the phase control converges quickly. Moreover, since the frequency dividing counter can be reset without interrupt processing, the software load on the microcomputer is reduced and other processing is not delayed.

Further, according to the VTR of the present invention, the capstan servo can be a soft servo, and the operation of the frequency division counter (particularly the reset operation) can be performed easily and with less software load. You can

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG.
In the figure, reference numeral 1 denotes a VTR servo IC, which is composed of a microcomputer. Although a head servo circuit may be provided in this IC in addition to the capstan servo circuit, only the capstan servo circuit is shown in the figure.

The free running counter 3 counts the clock CLK input through the terminal 2 as free running. Reference numeral 6 denotes a speed control system capture register, which latches the count output of the free running counter 3 by the CFG pulse input through the terminal 4 and amplified by the amplifier 5.

On the other hand, 7 is a capture register of the phase control system, which outputs the count output of the free running counter 3 by the CTL signal which is input through the terminal 12, amplified by the amplifier 13 and given through the frequency dividing counter 9. This is a latched capture register.

The outputs of both capture registers 6 and 7 are respectively processed by the CPU 8 and then combined to produce PW.
It is given to the M circuit 10. The PWM signal output from the PWM circuit 10 as a servo control signal is supplied to the low-pass filter 14 through the terminal 11, smoothed therein, and then supplied to the capstan motor 16 via the motor drive circuit 15. The capstan motor 16 is thereby controlled in speed and phase.

Reference numeral 17 is a magnetic tape, which is moved in the longitudinal direction by a capstan 18 driven by a motor 16. 19 is a CT recorded on the magnetic tape 17
It is a CTL head that reproduces an L (control) signal (a control signal reproducing head if only focusing on reproduction, but it becomes a control signal recording head that records a control signal during recording), and its output is from the terminal 1
It is supplied to the inside of the IC 1 via 2.

The frequency division counter 9 is constructed as software. The CPU 8 inputs the count output of the free running counter 3, specifies the center A of the PWM virtual output waveform created by the phase control system based on the count output, and only when the phase control is released, When the control pulse CTL exists within a certain range W centered on the center A, the control pulse CTL existing within the range W resets the frequency divider 9 (0).
multiply.

In FIG. 2, (a) schematically shows the output of the free running counter, which increases as the count increases. When it reaches a predetermined value, it decreases and then increases again by counting up, but the decreasing point is not shown in the figure. (B) is a virtual output of PWM of the phase control system, and the center A of the inclined portion corresponds to a specific count value A ′ of the free running counter 3, so that the CPU 8 can recognize it.

In FIG. 3, (a) shows the control pulse CTL input to the frequency divider 9, and (b) shows the reference count value of the free running counter as the reference pulse, which corresponds to the center A. Is.

In FIG. 3, the left side of (k) is the phase control cancellation, and the right side of (k) is the phase control operation. That is, FIG. 3 shows a transitional state in the phase control of the capstan motor when the VTR is switched to the search mode (5-times speed mode). In this case, the phase control is released immediately after switching, only the speed control is operated, and the phase control is also operated at the time of (k) in FIG.

First, in the phase release state, with respect to the reference pulse of FIG. 3B, the control pulse CTL positioned within a predetermined range (predetermined reference time) W centered on the pulse.
Is set to 0 as shown in FIG. This means that the pulse resets the divider counter.

After the point (k) where the phase control is activated, the operation of resetting the reference pulse with the control pulse within the predetermined range W is not performed. Therefore, the frequency divider repeats division by 5.

FIG. 4 shows a CPU for the operation of FIG. 3 described above.
8 shows a flowchart of the control operation of No. 8. In the figure, first, in step # 5, it is determined whether or not the phase control system is in the operating state. When the phase control system is released,
In step # 10, it is determined whether the control pulse CTL is within a predetermined range with respect to the reference value. If it is within the predetermined range, the flow proceeds to step # 15 to reset the frequency divider. If it is not within the predetermined range, the control pulse is counted by the frequency divider at step # 20.

If the phase control system is in operation in step # 5, the process proceeds to step # 25, the frequency divider is operated normally, and the output is used for servo processing. That is, the output of the frequency dividing counter 9 latches the count output of the free running counter 3 in the capture 7, and the phase control processing is performed by the latch output.

In the case of the first and fourth control pulses shown in FIG. 3A, step # 5 → step # 10.
→ Step # 15 → Step # 40
At 40, the process returns to the main routine (not shown), and after the processing of the main routine, the subroutine of FIG. 4 is again entered.

In the case of the second and third control pulses and the fifth and sixth control pulses, step # 5 → step #
The sequence proceeds from 10 → step # 20 → step # 40. (K)
For control pulses after the point, step # 5 →
The process proceeds from step # 25 → step # 30 → step # 40.

As described above, in the present embodiment, interrupt processing is not performed in order to reset the frequency divider with the reference pulse value, and the reference pulse value is set to the predetermined value when the phase control is released. It is controlled so that it is reset by the control pulse within the range. Therefore, suitable phase control can be realized without increasing interrupt processing.

It goes without saying that the present invention can be applied not only to the above-mentioned VTR but also to the phase control of other rotating bodies. Further, in the VTR, at least a search mode other than the reproduction mode at the normal speed is targeted. In a general rotating body, at least n (n is a natural number) double speed mode is present in addition to the normal speed mode.

[0034]

As described above, according to the present invention, when the rotating body is switched to the n-fold speed mode and the phase control system is placed in the inactive state, the frequency division counter is reset based on a predetermined reference time. Since it is applied correctly, the phase control system can be quickly converged when the phase control system enters the operating state. Moreover, since it is possible to reset the frequency divider without interrupt processing, it is possible to avoid a processing time delay due to saving of a stack or the like and save a RAM area.

Also in the case of the VTR of the present invention, the capstan servo can be a soft servo, and the operation of the frequency division counter (particularly the reset operation) can be performed easily and with less software load. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a soft servo circuit for a capstan of a VTR according to the present invention.

FIG. 2 is a diagram illustrating reset control of a frequency division counter of the phase control system.

FIG. 3 is a diagram for explaining reset control of the frequency division counter of the phase control system.

FIG. 4 is a flowchart of operation control of the phase control system of the present embodiment.

FIG. 5 is a block diagram of a conventional digital servo.

FIG. 6 is an operation explanatory diagram of a part of a conventional phase control system.

[Explanation of symbols]

 1 Servo 1C 3 Free running counter 7 Phase control system capture register 8 CPU 9 Frequency divider counter 10 PWM circuit 16 Capstan motor 17 Magnetic recording tape 18 Capstan 19 CTL head CTL control pulse CLK clock

Claims (3)

[Claims] 1. A phase control servo circuit for a rotating body having a normal speed mode and an n (n is a natural number of 2 or more) double speed mode, wherein a pulse signal representing the speed of the rotating body and used for phase control of the rotating body. In the n-fold speed mode, a frequency dividing counter that divides the condition to be the same as in the normal operation is configured by a software with a microcomputer, and after switching to the n-fold speed mode, the phase control system is disabled until the n-fold speed is reached. A phase control servo circuit for a rotating body, wherein the frequency dividing counter is reset by a pulse signal located within a predetermined reference time when the frequency dividing counter counts the pulse signal when the frequency dividing counter does not operate. . 2. The phase control servo circuit for a rotating body according to claim 1, wherein the predetermined reference time is determined on the basis of a predetermined output of a free running counter operated by a clock. 3. In a VTR having a search mode, a frequency dividing counter for dividing a control pulse obtained from a magnetic recording tape via a control signal reproducing head, a free running counter for counting a clock, and a free running counter for the free running counter. A capture register for latching an output with the output of the frequency division counter; a CPU for computing the output of the capture register and outputting a phase control signal; and a means for guiding the phase control signal to a capstan motor. The frequency dividing counter is configured by software, and when the phase control system is inoperative in the search mode, the frequency dividing counter is controlled by a control signal within a reference time obtained by the CPU based on the output of the free running counter. , The control signal VTR, characterized in that it was set to make a bet.