JPH0669087A - Method for forming silicon substrate - Google Patents
Method for forming silicon substrateInfo
- Publication number
- JPH0669087A JPH0669087A JP22250092A JP22250092A JPH0669087A JP H0669087 A JPH0669087 A JP H0669087A JP 22250092 A JP22250092 A JP 22250092A JP 22250092 A JP22250092 A JP 22250092A JP H0669087 A JPH0669087 A JP H0669087A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- substrate
- silicon substrate
- substrates
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Recrystallisation Techniques (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はシリコン基板の形成方法
に関し、特にシリコンデバイス及びその集積回路作製に
用いるためのシリコン基板の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicon substrate, and more particularly to a method for forming a silicon substrate for use in manufacturing a silicon device and its integrated circuit.
【０００２】[0002]
【従来の技術】従来、シリコン基板とシリコン基板を貼
り合わせる方法には、(1)単結晶シリコン表面を有する
基板とシリコン酸化膜表面を有する基板の表面を洗浄し
て重ね合わせた後に高温熱処理により貼り合わせる方法
（例えば特開平１−２３２７５０号公報、特開平２−４
６７６８号公報、特開平２−４６７７０号公報）、ま
た、(2)単結晶シリコン表面を有する基板とシリコン酸
化膜表面を有する基板の表面を洗浄して重ね合わせた後
に電圧を印加することで静電接着する貼り合わせ方法
（例えば特開平２−９０５０８号公報）、また(3)単結
晶シリコン表面を有する基板と単結晶シリコン表面を有
する基板の表面を清浄な状態で親水性にし、水分子を付
着させて接合した後に高温熱処理により貼り合わせる方
法（特開平２−４６７２２号公報）等がある。上記(1)
及び(2)の方法は、単結晶シリコン表面側の基板研磨に
より必要な膜厚の単結晶シリコン膜のＳＯＩ（Ｓｉｌｉ
ｃｏｎ ｏｎ Ｉｎｓｕｌａｔｏｒ）基板を形成するも
のである。一方、上記(3)の方法は、単結晶シリコン基
板同士の貼り合わせ法であり、不純物濃度の異なるシリ
コン基板を貼り合わせて深い不純物拡散及びエピタキシ
ャル基板の代替とするものである。2. Description of the Related Art Conventionally, a method of bonding a silicon substrate and a silicon substrate is as follows. (1) A substrate having a single crystal silicon surface and a substrate having a silicon oxide film surface are washed and superposed and then subjected to a high temperature heat treatment. A method of laminating (for example, Japanese Patent Laid-Open Nos. 1-232750 and 2-4).
No. 6768, Japanese Patent Laid-Open No. 2-46770), and (2) a substrate having a single crystal silicon surface and a substrate having a silicon oxide film surface are washed and superposed, and then a voltage is applied to cause static A bonding method for electro-adhesion (for example, Japanese Patent Application Laid-Open No. 2-90508), and (3) a substrate having a single crystal silicon surface and a substrate having a single crystal silicon surface are made hydrophilic in a clean state to remove water molecules. There is a method of adhering and bonding, and then laminating by high-temperature heat treatment (JP-A-2-46722). Above (1)
The methods (2) and (2) are for the SOI (Silicon) of a single crystal silicon film having a required thickness by polishing the substrate on the surface of the single crystal silicon.
This is for forming a con on insulator substrate. On the other hand, the above method (3) is a method of bonding single crystal silicon substrates to each other, in which silicon substrates having different impurity concentrations are bonded to each other for deep impurity diffusion and substitution for an epitaxial substrate.
【０００３】[0003]
【発明が解決しようとする課題】従来の単結晶シリコン
基板同士の貼り合わせ法は、高濃度基板と低濃度基板の
貼り合わせによる深い不純物拡散を有する基板形成の代
替、あるいは厚いエピタキシャル成長基板の代替として
用いられるのが主であった。これらの基板の貼り合わせ
界面については、電気的接続が確認されている。しか
し、これらの貼り合わせ基板は長時間の高温処理を必要
とする基板形成法の時間短縮を目的とするものである。
この形成には高温熱処理を用いることが重要な因子とな
っているため、薄層の不純物層形成は困難であり、その
利用範囲も限られていた。従って、従来の単結晶シリコ
ン基板同士の貼り合わせ技術は、薄層の不純物層を有す
るシリコン基板の形成が困難であった。薄層の不純物層
を有する基板を形成するには、シリコン基板内の不純物
拡散が生じないように貼り合わせの熱処理温度を８００
℃以下にする必要がある。しかし、従来の貼り合わせ法
ではこの温度以下の熱処理では電気的接続に問題があ
る。The conventional method for bonding single crystal silicon substrates to each other is used as an alternative to forming a substrate having deep impurity diffusion by bonding a high-concentration substrate and a low-concentration substrate, or as an alternative to a thick epitaxial growth substrate. It was mainly used. Electrical connection has been confirmed at the bonding interface of these substrates. However, these bonded substrates are intended to shorten the time required for the substrate forming method which requires a high temperature treatment for a long time.
Since the use of high temperature heat treatment is an important factor for this formation, it is difficult to form a thin impurity layer, and its range of use is limited. Therefore, it has been difficult to form a silicon substrate having a thin impurity layer by the conventional technique for bonding single crystal silicon substrates to each other. To form a substrate having a thin impurity layer, the heat treatment temperature for bonding is set to 800 so that impurity diffusion in the silicon substrate does not occur.
It must be below ℃. However, in the conventional bonding method, there is a problem in electrical connection when heat treatment is performed at this temperature or lower.
【０００４】一方、シリコン基板表面を洗浄して重ね合
わせた後に高温熱処理する貼り合わせる方法は、シリコ
ン表面を親水性にし、更にシリコン基板間の重ねあわせ
時に水蒸気あるいは水分を用いることを必要とする。そ
のため、界面に酸化膜が形成されており、これを高温熱
処理で拡散し外部に放出することによって貼り合わせ
る。従って、低温熱処理で貼りあわせるには酸化膜中の
酸素を拡散によって放出することができないので、電気
的接続に問題が生じる。On the other hand, the bonding method in which the surfaces of the silicon substrates are washed and superposed and then heat-treated at a high temperature requires that the silicon surfaces be made hydrophilic and that steam or water be used when superposing the silicon substrates. Therefore, an oxide film is formed on the interface, which is bonded by being diffused by high temperature heat treatment and released to the outside. Therefore, the oxygen in the oxide film cannot be released by diffusion for bonding by low temperature heat treatment, which causes a problem in electrical connection.
【０００５】従って本発明の目的とするところは、この
シリコン基板の貼り合わせにおいて、シリコン基板内の
不純物拡散が生じない程度の低温熱処理によって貼り合
わせ界面の接着強度、電気的接続を確保する方法を提供
することにある。Therefore, an object of the present invention is to provide a method for securing the bonding strength and electrical connection at the bonding interface by low temperature heat treatment to such an extent that impurity diffusion in the silicon substrate does not occur in bonding the silicon substrates. To provide.
【０００６】[0006]
【課題を解決するための手段】従来のシリコン基板同士
の貼り合わせは、高温熱処理前の重ね合わせの時点で界
面を自然酸化膜間のＯＨ基の水素結合で接着させ、これ
に高温熱処理を行うことによって自然酸化膜の酸素がシ
リコン内部に拡散することで電気的接続が得られてい
た。In the conventional bonding of silicon substrates to each other, at the time of superposition before the high temperature heat treatment, the interfaces are bonded by hydrogen bonds of OH groups between natural oxide films, and then the high temperature heat treatment is performed. As a result, oxygen in the natural oxide film diffused into the silicon, and electrical connection was obtained.
【０００７】一方、本発明では、この高温熱処理による
自然酸化膜中の酸素拡散を用いない方法として、貼り合
わせるシリコン表面を有する二枚の基板の自然酸化膜を
完全に除去し、その表面に弗素を結合させる。この状態
で二枚のシリコン基板を重ねあわせ熱処理するものであ
る。On the other hand, in the present invention, as a method which does not use the oxygen diffusion in the natural oxide film due to the high temperature heat treatment, the natural oxide films of the two substrates having the silicon surfaces to be bonded are completely removed, and fluorine is applied to the surfaces. Combine. In this state, two silicon substrates are superposed and heat-treated.
【０００８】[0008]
【作用】自然酸化膜等の表面層を除去したシリコン表面
を有する二枚の基板を更に弗酸水溶液で処理することに
よって、基板のシリコン表面に弗素を結合させる。これ
によりシリコン表面は、空気中の酸素と結合することに
よってできる自然酸化膜の発生を防ぐことができる。こ
のシリコン表面に形成された弗素の層は数原子層以下で
あり、基板内あるいは貼り合わせ界面に残存しても微量
であるため貼り合わせ界面の電気的接続を妨げることは
ない。以下、本発明の実施例を、図面を参照してより詳
細に説明する。The two substrates having a silicon surface from which the surface layer such as the natural oxide film has been removed are further treated with an aqueous solution of hydrofluoric acid to bond fluorine to the silicon surface of the substrate. As a result, it is possible to prevent the formation of a natural oxide film on the silicon surface, which is caused by bonding with oxygen in the air. The fluorine layer formed on the silicon surface is a few atomic layers or less, and even if it remains in the substrate or at the bonding interface, it is a very small amount and does not hinder the electrical connection at the bonding interface. Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.
【０００９】[0009]
〈実施例１〉単結晶シリコン基板１を１０００℃の酸素
雰囲気中で熱処理することにより約５００ｎｍの酸化膜
２を形成した。次に、ジシラン（Ｓｉ2Ｈ6）の熱分解を
用いる低圧ＣＶＤ法により膜厚が約４００ｎｍの非晶質
シリコン膜３を堆積した。上記シリコン基板１及び通常
のＲＣＡ洗浄したシリコン基板４を弗酸水溶液（弗酸：
水＝１：１０）に２０秒間浸した。この処理によって、
シリコン表面が疎水性になる。その後、速やかに二枚の
シリコン基板を圧着した（図１参照)。次に、この基板
に接着した基板を水素雰囲気中で６００℃、４時間の熱
処理を行なった。この熱処理により、非晶質シリコン膜
３はシリコン基板４との貼り合わせ界面５から縦方向に
固相成長することによって単結晶シリコンになると共
に、二枚のシリコン基板は貼り付いた。この貼り合わせ
基板の形成方法では、シリコン基板１に形成した酸化膜
２上の非晶質シリコン膜３及びシリコン基板４の不純物
種、濃度及び膜厚を選択することによって、所望の二層
構造ＳＯＩ基板を得ることが可能である。Example 1 A single crystal silicon substrate 1 was heat-treated in an oxygen atmosphere at 1000 ° C. to form an oxide film 2 having a thickness of about 500 nm. Next, an amorphous silicon film 3 having a thickness of about 400 nm was deposited by a low pressure CVD method using thermal decomposition of disilane (Si 2 H 6 ). The silicon substrate 1 and the normal RCA-cleaned silicon substrate 4 are treated with an aqueous solution of hydrofluoric acid (hydrofluoric acid:
It was soaked in water = 1: 10) for 20 seconds. By this process,
The silicon surface becomes hydrophobic. Then, the two silicon substrates were quickly pressure bonded (see FIG. 1). Next, the substrate bonded to this substrate was heat-treated at 600 ° C. for 4 hours in a hydrogen atmosphere. By this heat treatment, the amorphous silicon film 3 was solid-phase grown vertically from the bonding interface 5 with the silicon substrate 4 to become single crystal silicon, and the two silicon substrates were bonded. In this method for forming a bonded substrate, a desired two-layer structure SOI is obtained by selecting the impurity species, the concentration and the film thickness of the amorphous silicon film 3 and the silicon substrate 4 on the oxide film 2 formed on the silicon substrate 1. It is possible to obtain a substrate.
【００１０】〈実施例２〉単結晶（１００）シリコン基
板１１及び単結晶（１００）シリコン基板１２を通常の
ＲＣＡ洗浄による表面クリーニング処理を行なった後、
更に弗酸水溶液（弗酸：水＝１：１０）に２０秒間浸し
た。この処理によって、シリコン表面が疎水性になっ
た。その後、直ちに二枚のシリコン基板を重ね合わせ
た。基板の重ね合わせは、双方の基板に形成されている
オリエンテーションフラットを合わせることによって、
面方位とその面方向も一致させた（図２参照）。次に、
８００℃の窒素雰囲気中で熱処理（２時間）を行なっ
た。この熱処理により単結晶シリコン基板１１と単結晶
シリコン基板１２をその貼り合わせ界面１３に絶縁体層
を生じることなく貼り合わせることができた。上記の様
に形成した基板の貼り合わせ界面１３については、基板
１１を低抵抗ｎ型単結晶シリコン、基板１２を低抵抗ｐ
型単結晶シリコンとして貼り合わせた後に電圧−電流特
性を調べることにより正常な接合特性が得られることを
確認した。<Embodiment 2> The single crystal (100) silicon substrate 11 and the single crystal (100) silicon substrate 12 were subjected to surface cleaning treatment by ordinary RCA cleaning, and then,
Further, it was immersed in an aqueous solution of hydrofluoric acid (hydrofluoric acid: water = 1: 10) for 20 seconds. This treatment rendered the silicon surface hydrophobic. Immediately thereafter, two silicon substrates were overlaid. Substrate superposition is achieved by aligning the orientation flats formed on both substrates.
The plane orientation and the plane direction were also matched (see FIG. 2). next,
Heat treatment (2 hours) was performed in a nitrogen atmosphere at 800 ° C. By this heat treatment, the single crystal silicon substrate 11 and the single crystal silicon substrate 12 could be bonded to each other at the bonding interface 13 without forming an insulating layer. Regarding the bonding interface 13 of the substrates formed as described above, the substrate 11 is a low resistance n-type single crystal silicon, and the substrate 12 is a low resistance p.
It was confirmed that normal bonding characteristics could be obtained by examining the voltage-current characteristics after bonding as type single crystal silicon.
【００１１】〈実施例３〉単結晶シリコン基板２１及び
単結晶シリコン基板２３にジシラン（Ｓｉ2Ｈ6）の熱分
解を用いる低圧ＣＶＤ法により膜厚が約３００ｎｍの非
晶質シリコン膜２２及び２３を堆積した。上記シリコン
基板２１及びシリコン基板２３を熱硝酸で洗浄した後に
弗酸水溶液（弗酸：水＝１：１０）に１５秒間浸した。
この処理によって、非晶質シリコン膜２２表面及び非晶
質シリコン膜２４表面は疎水性になった。その後、速や
かに二枚のシリコン基板を圧着した（図３参照)。次
に、二枚のシリコン基板を接着した基板に水素雰囲気中
で６００℃、４時間の熱処理を行なった。この熱処理に
より、非晶質シリコン膜２２及び２４はシリコン基板２
１及び２４との接触部から縦方向に固相成長することに
よって単結晶シリコンになると共に、二枚のシリコン基
板は貼り付いた。この時の非晶質シリコン膜２２の固相
成長はシリコン基板２１、非晶質シリコン膜２４の固相
成長はシリコン基板２３との接触部から同時に進行する
ので、二枚のシリコン基板の面方位と面方向を同一にす
ることが必要である。このシリコン基板の面方位及び面
方向が一致しないと、固相成長後のシリコン貼り合わせ
界面２５に結晶のズレが生じる原因になる。形成したシ
リコン基板の深さ方向の不純物プロファイルを調べる
と、ｐ型の単結晶シリコン基板２１及び単結晶シリコン
基板２３の間に約６００ｎｍの不純物を含まないシリコ
ン層が確認できた。なお、この貼り合わせ基板の形成方
法では、単結晶シリコン基板２１及び２３と非晶質シリ
コン膜２２及び２４の不純物種、濃度及び膜厚を選択す
ることによって、所望の四層構造シリコン基板を得るこ
とも可能である。<Embodiment 3> Amorphous silicon films 22 and 23 having a thickness of about 300 nm are formed on the single crystal silicon substrate 21 and the single crystal silicon substrate 23 by a low pressure CVD method using thermal decomposition of disilane (Si 2 H 6 ). Was deposited. The silicon substrate 21 and the silicon substrate 23 were washed with hot nitric acid and then dipped in a hydrofluoric acid aqueous solution (hydrofluoric acid: water = 1: 10) for 15 seconds.
By this treatment, the surfaces of the amorphous silicon film 22 and the amorphous silicon film 24 became hydrophobic. Then, the two silicon substrates were quickly pressure bonded (see FIG. 3). Next, the substrate to which the two silicon substrates were adhered was subjected to heat treatment at 600 ° C. for 4 hours in a hydrogen atmosphere. By this heat treatment, the amorphous silicon films 22 and 24 are formed on the silicon substrate 2
Single-crystal silicon was obtained by solid-phase growth in the vertical direction from the contact portions with 1 and 24, and the two silicon substrates were attached. At this time, the solid phase growth of the amorphous silicon film 22 proceeds simultaneously with the silicon substrate 21 and the solid phase growth of the amorphous silicon film 24 proceeds from the contact portion with the silicon substrate 23. And it is necessary to make the surface direction the same. If the plane orientation and the plane direction of the silicon substrate do not match, a crystal shift may occur at the silicon bonding interface 25 after solid phase growth. When the impurity profile in the depth direction of the formed silicon substrate was examined, a silicon layer containing no impurities of about 600 nm was confirmed between the p-type single crystal silicon substrate 21 and the single crystal silicon substrate 23. In this method for forming a bonded substrate, a desired four-layer structure silicon substrate is obtained by selecting the impurity species, concentration and film thickness of the single crystal silicon substrates 21 and 23 and the amorphous silicon films 22 and 24. It is also possible.
【００１２】〈実施例４〉単結晶（１００）シリコン基
板３１及び単結晶（１００）シリコン基板３２を通常の
有機、無機洗浄による表面クリーニングを行なった。次
に、シリコン基板３１を弗酸水溶液（弗酸：水＝１：１
０）に３０秒間浸した後、真空蒸着装置内で８００℃、
６０分の熱処理による試料の表面クリーニングを行ない
清浄な試料表面を形成した後に超高真空中（１×１０-7
Ｐａ以下）で電子ビーム蒸着により膜厚が約５００ｎｍ
の非晶質シリコン膜を堆積し、それに引き続き真空中で
４５０℃、１時間の熱処理による非晶質シリコン膜の緻
密化を行うことによって、緻密化した非晶質シリコン膜
３３を形成した。このシリコン基板３１は、引き続き真
空装置内に保存した。次に、シリコン基板３２を弗酸水
溶液（弗酸：水＝１：１０）に３０秒間浸した後に真空
蒸着装置内に搬送した。そして、真空中で非晶質シリコ
ン膜３３を堆積した基板３１表面にシリコン基板３２表
面を対向させて重ね合わせた（図４参照）。この二枚の
シリコン基板を重ね合わせる処理は真空蒸着装置内で行
なうことが重要であり、シリコン基板３２は真空蒸着装
置の予備排気室に搬送、排気した後に二枚の基板を同じ
処理室に搬送した。更に真空装置内で重ね合わせたシリ
コン基板に、引き続き真空中で６００℃、２０時間の熱
処理を行なった。この熱処理により、非晶質シリコン膜
３３はシリコン基板３１及びシリコン基板３２との貼り
合わせ界面３４から縦方向に固相成長することによって
単結晶シリコンになると共に、二枚のシリコン基板は貼
り付いた。この時の非晶質シリコン膜３３の固相成長は
シリコン基板３１及びシリコン基板３２との接触部から
同時に進行するので、二枚の面方位と面方向を同一にす
ることが必要である。形成したシリコン基板の深さ方向
の不純物プロファイルを調べると、ｐ型の単結晶シリコ
ン基板３１及び単結晶シリコン基板３２の間に約５００
ｎｍの不純物を含まないシリコン層が確認できた。な
お、この貼り合わせ基板の形成方法では、単結晶シリコ
ン基板３１、単結晶シリコン基板３２、及び非晶質シリ
コン膜３３の不純物種や濃度の組合せにより所望の三層
構造のシリコン基板を得ることが可能である。<Embodiment 4> The single crystal (100) silicon substrate 31 and the single crystal (100) silicon substrate 32 were subjected to surface cleaning by ordinary organic and inorganic cleaning. Next, the silicon substrate 31 is treated with an aqueous solution of hydrofluoric acid (hydrofluoric acid: water = 1: 1).
0) for 30 seconds, and then 800 ° C. in a vacuum evaporation system.
The surface of the sample is cleaned by heat treatment for 60 minutes to form a clean sample surface, and then in ultra-high vacuum (1 x 10 -7
Film thickness of about 500 nm by electron beam evaporation at less than Pa)
The amorphous silicon film was deposited, and then the amorphous silicon film was densified by heat treatment at 450 ° C. for 1 hour in vacuum to form a densified amorphous silicon film 33. This silicon substrate 31 was continuously stored in a vacuum device. Next, the silicon substrate 32 was immersed in a hydrofluoric acid aqueous solution (hydrofluoric acid: water = 1: 10) for 30 seconds and then transferred into a vacuum vapor deposition apparatus. Then, the surface of the silicon substrate 32 was opposed to the surface of the substrate 31 on which the amorphous silicon film 33 was deposited in a vacuum (see FIG. 4). It is important to perform the process of superposing the two silicon substrates in the vacuum vapor deposition apparatus. The silicon substrate 32 is transported to the preliminary exhaust chamber of the vacuum vapor deposition apparatus, and after being exhausted, the two substrates are transported to the same processing chamber. did. Further, the stacked silicon substrates in a vacuum apparatus were subsequently heat-treated in vacuum at 600 ° C. for 20 hours. By this heat treatment, the amorphous silicon film 33 becomes single crystal silicon by solid phase growth in the vertical direction from the bonding interface 34 between the silicon substrate 31 and the silicon substrate 32, and the two silicon substrates are bonded. . Since the solid phase growth of the amorphous silicon film 33 at this time proceeds simultaneously from the contact portion with the silicon substrate 31 and the silicon substrate 32, it is necessary to make the two plane orientations and the same plane directions. When the impurity profile in the depth direction of the formed silicon substrate is examined, about 500 between the p-type single crystal silicon substrate 31 and the single crystal silicon substrate 32 is detected.
A silicon layer containing no nm impurities was confirmed. Note that in this method for forming a bonded substrate, a desired three-layer structure of a silicon substrate can be obtained by combining impurity species and concentrations of the single crystal silicon substrate 31, the single crystal silicon substrate 32, and the amorphous silicon film 33. It is possible.
【００１３】[0013]
【発明の効果】本発明によれば、シリコン表面を有する
二枚の基板の貼り合わせ界面に絶縁体層の形成が無いの
で、電気的な接続も可能となる。更に基板の貼り合わせ
に用いる熱処理による不純物拡散が生じないので急峻な
不純物プロファイル及び濃度差を有する薄層をシリコン
基板内に形成することが可能である。従って、このシリ
コン基板の貼り合わせ法と研磨等の基板加工を行なうこ
とによって、基板深くに急峻な濃度差あるいは異なる不
純物を有するシリコン基板、また、濃度差あるいは異な
る不純物を有する多層構造のシリコン基板及びＳＯＩ基
板の形成も可能である。本発明の効果を用いて形成した
シリコン基板は、単体ＭＯＳトランジスタのみに限ら
ず、ＣＭＯＳ、ＤＲＡＭ、ＳＲＡＭの高集積メモリー、
高速演算回路等を合わせ持った半導体装置への適用が可
能である。According to the present invention, since no insulating layer is formed at the bonding interface between two substrates having silicon surfaces, electrical connection is possible. Further, since the impurity diffusion due to the heat treatment used for bonding the substrates does not occur, it is possible to form a thin layer having a steep impurity profile and a concentration difference in the silicon substrate. Therefore, by performing this silicon substrate bonding method and substrate processing such as polishing, a silicon substrate having a sharp concentration difference or different impurities deep in the substrate, and a silicon substrate having a multi-layer structure having a concentration difference or different impurities, It is also possible to form an SOI substrate. The silicon substrate formed by utilizing the effect of the present invention is not limited to a single MOS transistor, but may be a highly integrated memory such as CMOS, DRAM, SRAM,
It can be applied to a semiconductor device having a high-speed arithmetic circuit and the like.
【図１】本発明の実施例による製造工程を示す断面図で
ある。FIG. 1 is a cross-sectional view showing a manufacturing process according to an embodiment of the present invention.
【図２】本発明の実施例による製造工程を示す断面図で
ある。FIG. 2 is a cross-sectional view showing a manufacturing process according to an embodiment of the present invention.
【図３】本発明の実施例による製造工程を示す断面図で
ある。FIG. 3 is a cross-sectional view showing a manufacturing process according to an embodiment of the present invention.
【図４】本発明の実施例による製造工程を示す断面図で
ある。FIG. 4 is a cross-sectional view showing a manufacturing process according to an embodiment of the present invention.
１、４…単結晶シリコン基板、２…シリコン酸化膜、３
…非晶質シリコン膜、５…シリコン貼り合わせ界面、１
１、１２…単結晶シリコン基板、１３…シリコン貼り合
わせ界面、２１、２３…単結晶シリコン基板、２２、２
４…非晶質シリコン膜、２５…シリコン貼り合わせ界
面、３１、３２…単結晶シリコン基板、３３…非晶質シ
リコン膜、３４…シリコン貼り合わせ界面。1, 4 ... Single crystal silicon substrate, 2 ... Silicon oxide film, 3
... Amorphous silicon film, 5 ... Silicon bonding interface, 1
1, 12 ... Single crystal silicon substrate, 13 ... Silicon bonding interface, 21, 23 ... Single crystal silicon substrate, 22, 2
4 ... Amorphous silicon film, 25 ... Silicon bonding interface, 31, 32 ... Single crystal silicon substrate, 33 ... Amorphous silicon film, 34 ... Silicon bonding interface.
Claims (4)
シリコン基板を形成するにおいて、 単結晶シリコン表面を有する基板及び非晶質シリコン表
面を有する基板の表面自然酸化膜を除去することにより
清浄なシリコン表面を形成する工程と、 上記二枚のシリコン基板を弗酸水溶液処理を行う工程
と、 上記弗酸水溶液処理の後に二枚のシリコン基板の表面を
接触させることによって重ね合わせる工程と、 上記重ね合わせたシリコン基板を熱処理する工程とを含
むことを特徴とするシリコン基板の形成方法。1. When two silicon substrates are bonded to each other to form a new silicon substrate, cleaning is performed by removing a surface natural oxide film of a substrate having a single crystal silicon surface and a substrate having an amorphous silicon surface. A step of forming a simple silicon surface, a step of treating the two silicon substrates with an aqueous solution of hydrofluoric acid, and a step of superposing the surfaces of the two silicon substrates by bringing them into contact with each other after the treatment with the aqueous solution of hydrofluoric acid, And a step of heat-treating the superposed silicon substrates.
て、双方の基板表面を二枚の単結晶シリコン、あるいは
二枚の非晶質シリコンとして貼り合わせることを特徴と
するシリコン基板の形成方法。2. The method for forming a silicon substrate according to claim 1, wherein the surfaces of both substrates are bonded as two single crystal silicon or two amorphous silicon. .
せたシリコン基板の熱処理として、５５０〜８００℃の
窒素ガス、不活性ガス、水素ガス雰囲気、あるいは真空
中で行うことを特徴とするシリコン基板の形成方法。3. The heat treatment of the stacked silicon substrates according to claim 1 or 2 is performed in a nitrogen gas, inert gas or hydrogen gas atmosphere at 550 to 800 ° C. or in a vacuum. A method for forming a silicon substrate.
シリコン基板を形成するにおいて、 洗浄した基板Ａ表面に非晶質シリコン膜を堆積し、当該
基板を真空装置内に保存する工程と、 単結晶シリコン基板Ｂの表面自然酸化膜を除去すること
により清浄なシリコン表面を形成する工程と、 上記清浄なシリコン表面を形成した単結晶シリコン基板
Ｂに弗酸水溶液処理を行ない、上記非晶質シリコン膜を
堆積した基板Ａを保存する真空装置内に搬送する工程
と、 シリコン表面を有する基板ＡとＢの表面を真空中で接触
させることによって二枚のシリコン基板を重ね合わせる
工程と、 上記重ね合わせたシリコン基板を引き続き真空中で熱処
理する工程とを含むことを特徴とするシリコン基板の形
成方法。4. A step of depositing an amorphous silicon film on a surface of a cleaned substrate A and storing the substrate in a vacuum apparatus when the two silicon substrates are bonded to each other to form a new silicon substrate. The step of forming a clean silicon surface by removing the natural oxide film on the surface of the single crystal silicon substrate B, and the single crystal silicon substrate B on which the clean silicon surface has been formed are treated with an aqueous solution of hydrofluoric acid to obtain the amorphous silicon. A step of transporting the substrate A on which the silicon film is deposited into a vacuum device for storing, a step of superposing two silicon substrates by bringing the surfaces of the substrates A and B having silicon surfaces into contact with each other in vacuum, A step of subsequently heat treating the combined silicon substrate in a vacuum, the method for forming a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22250092A JPH0669087A (en) | 1992-08-21 | 1992-08-21 | Method for forming silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22250092A JPH0669087A (en) | 1992-08-21 | 1992-08-21 | Method for forming silicon substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0669087A true JPH0669087A (en) | 1994-03-11 |
Family
ID=16783408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22250092A Pending JPH0669087A (en) | 1992-08-21 | 1992-08-21 | Method for forming silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669087A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7031785B2 (en) | 2002-03-19 | 2006-04-18 | Sharp Kabushiki Kaisha | Method of production control and method of manufacturing electronic apparatus |
| US11217699B2 (en) | 2012-04-30 | 2022-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
-
1992
- 1992-08-21 JP JP22250092A patent/JPH0669087A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7031785B2 (en) | 2002-03-19 | 2006-04-18 | Sharp Kabushiki Kaisha | Method of production control and method of manufacturing electronic apparatus |
| US11217699B2 (en) | 2012-04-30 | 2022-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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