JPH0668728B2 - Virtual computer system - Google Patents

Description

The present invention relates to a virtual computer system including a plurality of program status words on hardware.

[Conventional technology]

Generally, for instruction execution control of an information processing device, a program status word (hereinafter abbreviated as PSW) provided on hardware.
Is used.

Instruction execution control information necessary for instruction execution is held in the PSW to control the instruction execution processing of hardware, and its general specification is the publication "IBM System / 1370 Prin" issued by IBM Corporation.
ciples of operation "(GA22-7000) and its publication" IBM System 1370 Extended Archi "
tecture Principles of Operation "(SA-22-7
085) describes the details.

As is apparent from the above-mentioned publication, in the conventional information processing apparatus, one PSW sufficiently fulfills its role.

In recent years, it has become extremely common to adopt a method called a virtual computer, and as a result, it is necessary for multiple operating systems to operate simultaneously and independently on a single computer system. It has become necessary to make the PSW used by each operating system independent.

P of a conventional virtual machine (hereinafter referred to as VM or guest)
The value of SW is collectively managed by a virtual computer control program (hereinafter referred to as VMCP), and the PSW value of each VM is controlled by operating a single PSW owned by VMCP (hereinafter referred to as current PSW). It is given to each VM. In this case, the single current PSW of the information processing device is managed by VMCP, and is never controlled by VM. But each V
In order to obtain the PSW value of M by the software simulation of VMCP, the overhead for the simulation is inevitably generated, which is a problem that cannot be ignored in terms of VM performance.

To remove the overhead of this simulation,
Recently, there has been proposed a virtual computer system in which each VM has an independent PSW and the VMSW performs the processing without intervention of the VMCP.

When the guest program or the guest's interrupt tries to change the VM's PSW, the VMCP
The control is not transferred to and the simulation is performed, but the PSW of the guest is directly changed and the processing is continued. In other words, the PSW controlled by VMCP (hereinafter referred to as host PSW) and the PSW controlled by VM (hereinafter referred to as guest PSW) exist independently and operate independently. As a general specification of this system, for example, a publication "IBM System1370" issued by IBM Corporation is used.
Extened Architecture Interpretive Execution "(S
The details are described in A22-7095).

[Problems to be solved by the invention]

It is self-evident that in order to realize an information processing apparatus that satisfies this specification, it can be realized by making the logical circuit of the PSW mechanism conventionally provided in hardware independent and making it redundant. However, simply duplicating requires two sets of PSW and its peripheral circuits, which causes an increase in cost.

Further, in the model having only one PSW like the conventional information processing apparatus, the above-mentioned independent PSW is used.
Therefore, if the PSW and its peripheral circuits are to be duplicated, the amount of change in the hardware logic is very large, and the cost is significantly increased.

Regarding the above-mentioned prior art, in that the PSW of the information processing apparatus is provided independently, the cost increase due to the duplication of the hardware logic and the hardware having only one set of PSW There is a problem that the change amount of the wear logic is large and the cost is increased.

An object of the present invention is to eliminate the above-mentioned problems, and one VM is realized by one PSW mechanism.
By correcting the PSW value of
It is to provide a virtual computer system including the.

[Means for solving problems]

A feature of the present invention is that, when a set of PSWs is made to function, a plurality of PSW values provided by a program are individually stored on hardware, and the value set in the PSW at the current is set under a certain condition. By providing a virtual computer system in which a mechanism capable of simultaneously operating a plurality of PSWs is added to an information processing apparatus having one set of PSW hardware by selecting a value and setting a corrected value. .

That is, the PSW when the VMCP is running (hereinafter referred to as the host PS
W) and PSW when VM runs (hereinafter referred to as guest PSW) are stored in hardware, and PSW that actually controls the hardware (hereinafter referred to as current PSW) is used when VMCP runs. Sets the host PSW, and when the VM runs, the host PSW and guest PSW
By setting a value obtained by merging the contents of SW, it is possible to provide a virtual computer system having a plurality of PSWs as seen from the program.

[Action]

First means for selecting one of a plurality of PSW values and setting it as a set of current PSWs, and a plurality of PSs described above.
When the W value is set to the current PSW, by the second means for correcting the PSW value according to the attribute of the PSW to be set, in the information processing apparatus having one set of PSW as hardware logic, It is possible to provide an efficient virtual computer system including a plurality of independent PSWs without increasing costs and changing hardware logic.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a virtual computer system including the PSW group of the present invention. In this example, P that can operate independently
Each SW has one host PSW and one guest PSW, but a plurality of SWs may be provided.

In FIG. 1, a control unit CU 101 is a control unit that controls the connected devices and executes command processing, and controls the current P via signal lines 151 and 154.
It is connected to an SW register (hereinafter abbreviated as CPSW) 102, and further connected via a signal line 156 to a host PSW storage register (hereinafter abbreviated as HPSW) 103 and a guest PSW storage register (hereinafter abbreviated as GPSW) 104. .

CPSW is a register that stores the current PSW that displays and controls the state of the program currently being executed, and is updated by the CU 101 as the instruction processing progresses.
51 and 154, 152, 153 and 155 respectively, CU101, merge circuit B106, merge circuit 10
5, connected to the HPSW 103.

The HPSW 103 is a register for temporarily storing the host PSW, and the CPSW 102, the merge circuit B 106, and the CU 1 are respectively connected via the signal lines 153, 155, and 156.
01 is connected.

The GPSW 104 is a register that temporarily stores the guest PSW, and is connected to the CU 101, the merge circuit A 105, and the merge circuit B 106 via signal lines 156, 157, and 158, respectively.

The merge circuit A (hereinafter abbreviated as MERGEA) 105 calculates the new guest PS from the value of the guest PSW of the current PSW.
A merge circuit that creates the value of W, and is a signal line 155, 1
57, 158 through CPSW 102 and GPSW10
4 is connected.

The merge circuit B (hereinafter abbreviated as MERGEB) 106 is a new current PSW based on the values of the host PSW and the guest PSW.
Is a merge circuit that creates the value of
CPSW102, HPSW103 via 3 and 158
And GPSW 104.

Next, the operation of the present invention will be described with reference to FIG.

When operating the information processing device as the virtual computer system, first, the VMCP is operated and then the VM is operated. After that, while the process reciprocates between the VMCP and the VM, the VM is executed under the control of the VMCP. That is, the information processing apparatus has two cases, one is operated under the control of the host PSW and the other is operated under the control of the guest PSW, and the processing is performed while switching the PSW.

Therefore, the information processing apparatus first operates under the control of the host PSW. In this case, the host PSW is set from the CPU 101 to the CPSW 102 via the signal line 151. The processing mode of this host PSW has a format that matches the processing mode of the bare information processing device.
P is executed.

Next, the procedure when the VMCP issues an instruction to activate the VM and starts executing the processing of the VM is as follows. First C
The host PSW value that was controlling the VMCP processing by the PSW 102 is set and stored in the HPSW 103 via the signal line 155. Subsequently, the CU 101 sends the guest PSW value to be activated to the GPSW1 via the signal line 156.
Set to 04. Host PSW set in HPSW 103 and guest PSW set in GPSW 104
Is merged by the MERGEB 106, converted into the guest PSW format that matches the hardware processing mode of the host information processing apparatus, and the CPS is transmitted via the signal line 152.
It is set to W102 and the VM processing is started.

FIG. 2 shows an example of the PSW format in various processing modes.

The merge content of the MERGEB 106 is a procedure for creating the current PSW for VM execution, and the operation content of this procedure is to select the content of the HPSW 103 for each bit of the PSW to be generated, select the content of the GPSW 104, H
For example, the contents of the PSW 103 and the contents of the GPSW 104 are logically operated and output. That is, the current PSW value for VM execution set in the CPSW 102 is the host PS
It is a value obtained by merging the W value and the guest PSW value.

FIG. 3 shows an example of processing contents.

Next, when the VM processing is being executed under the control of the CPSW 102, the operation when the control is transferred to the VMCP by the interrupt is as follows. The current PSW value for VM execution stored in the CPSW 102 (this is updated by the CU 101 as the processing is executed) and GPSW1
The guest PSW value stored in 04 is input to the MERGEA 105 via the signal lines 155 and 158, respectively. In MERGEA105, the input current P
A procedure for creating the latest guest PSW value from the SW value and the guest PSW value is executed. That is, the contents of the CPSW 102 are selected for each bit to be generated, GPSW104
Is selected, and the guest PSW value subjected to this merge processing is set in the GPSW 104. FIG. 4 shows an example of the processing contents (when the guest PSW is in the 370BC mode). Then, the host PSW value stored in the HPSW 103 is sent to the CPSW 102 via the signal line 153.
Is set to, and the processing of the VMCP which is the host is executed again. The VM processing is performed by repeating the above switching to form a virtual computer system.

Although the virtual computer system according to the present invention has been described above, the HPSW 103 and the GPSW 104 are hardware registers in this example, but a work memory on hardware or a main memory may be used. Further MER
The GEA 105 and the MERGEB 106 are merge circuits in this example, but the same function may be realized by a hardware microprogram.

Also, in this example, the register that stores the PSW value of the guest is 1
Although an example of individual pieces is shown, it goes without saying that a plurality of pieces may be formed.

〔The invention's effect〕

According to the present invention, one set of PS is used as hardware logic.
In an information processing apparatus having a W mechanism, a great effect that a higher performance virtual computer system having a plurality of independent PSW mechanisms can be realized with a minimum increase in cost and a change in hardware logic is realized. can get.

[Brief description of drawings]

FIG. 1 is a block diagram of a virtual computer system to which the present invention is applied. 101 ... Control device, 102 ... Current PSW register, 103 ... Host PSW register, 104 ... Guest PSW register, 105 ... Merge circuit A, 106 ...
... Merge circuit B. FIG. 2 is a diagram showing PSW formats in various processing modes. FIG. 3 is a diagram showing the processing contents of the merge circuit B. FIG. 4 is a diagram showing the processing contents of the merge circuit A.

Claims (1)

[Claims] 1. A program status word (PS) for controlling execution of instructions.
W) in an information processing device, in which one virtual computer control program manages a plurality of operating systems and each runs in a predetermined processing mode, the PSW (controlled by the virtual computer control program Register (HP) for storing host PSW
SW), a register (GPSW) that stores a PSW (guest PSW) controlled by a specific operating system among the plurality of operating systems, and a register (CPSW) that stores a PSW (current PSW) that actually controls hardware. ) And the contents of the HPSW are set in the CPSW when the virtual computer control program runs, and the contents of the GPSW corresponding to the processing mode of the particular operating system when the particular operating system runs. A virtual computer system characterized by setting the contents of the HPSW in the CPSW after performing a predetermined logical processing.